diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2005-05-31 07:49:19 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:31:17 -0400 |
commit | e50c0a8fa60da9ac0e0a70caa8a3a803815c1f2f (patch) | |
tree | 1928e8b0a4b7fb615e5a9f65dc934ba2e74cb9cd /include/asm-mips | |
parent | 10f650db1bcc193ea07d4f8c2f07315da38ea0c4 (diff) |
Support the MIPS32 / MIPS64 DSP ASE.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips')
-rw-r--r-- | include/asm-mips/abi.h | 25 | ||||
-rw-r--r-- | include/asm-mips/cpu-features.h | 4 | ||||
-rw-r--r-- | include/asm-mips/cpu.h | 2 | ||||
-rw-r--r-- | include/asm-mips/dsp.h | 83 | ||||
-rw-r--r-- | include/asm-mips/elf.h | 81 | ||||
-rw-r--r-- | include/asm-mips/inst.h | 8 | ||||
-rw-r--r-- | include/asm-mips/mach-ip22/cpu-feature-overrides.h | 2 | ||||
-rw-r--r-- | include/asm-mips/mach-ip27/cpu-feature-overrides.h | 1 | ||||
-rw-r--r-- | include/asm-mips/mach-ip32/cpu-feature-overrides.h | 1 | ||||
-rw-r--r-- | include/asm-mips/mach-ja/cpu-feature-overrides.h | 1 | ||||
-rw-r--r-- | include/asm-mips/mach-ocelot3/cpu-feature-overrides.h | 1 | ||||
-rw-r--r-- | include/asm-mips/mach-rm200/cpu-feature-overrides.h | 1 | ||||
-rw-r--r-- | include/asm-mips/mach-sibyte/cpu-feature-overrides.h | 1 | ||||
-rw-r--r-- | include/asm-mips/mach-yosemite/cpu-feature-overrides.h | 1 | ||||
-rw-r--r-- | include/asm-mips/mipsregs.h | 287 | ||||
-rw-r--r-- | include/asm-mips/processor.h | 22 | ||||
-rw-r--r-- | include/asm-mips/ptrace.h | 4 | ||||
-rw-r--r-- | include/asm-mips/sigcontext.h | 60 | ||||
-rw-r--r-- | include/asm-mips/signal.h | 29 | ||||
-rw-r--r-- | include/asm-mips/system.h | 11 |
20 files changed, 568 insertions, 57 deletions
diff --git a/include/asm-mips/abi.h b/include/asm-mips/abi.h new file mode 100644 index 000000000000..2e7e651c3e3f --- /dev/null +++ b/include/asm-mips/abi.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2005 by Ralf Baechle | ||
7 | * Copyright (C) 2005 MIPS Technologies, Inc. | ||
8 | */ | ||
9 | #ifndef _ASM_ABI_H | ||
10 | #define _ASM_ABI_H | ||
11 | |||
12 | #include <asm/signal.h> | ||
13 | #include <asm/siginfo.h> | ||
14 | |||
15 | struct mips_abi { | ||
16 | int (* const do_signal)(sigset_t *oldset, struct pt_regs *regs); | ||
17 | int (* const setup_frame)(struct k_sigaction * ka, | ||
18 | struct pt_regs *regs, int signr, | ||
19 | sigset_t *set); | ||
20 | int (* const setup_rt_frame)(struct k_sigaction * ka, | ||
21 | struct pt_regs *regs, int signr, | ||
22 | sigset_t *set, siginfo_t *info); | ||
23 | }; | ||
24 | |||
25 | #endif /* _ASM_ABI_H */ | ||
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 012deda63e68..4930824a43aa 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h | |||
@@ -105,6 +105,10 @@ | |||
105 | #endif | 105 | #endif |
106 | #endif | 106 | #endif |
107 | 107 | ||
108 | #ifndef cpu_has_dsp | ||
109 | #define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP) | ||
110 | #endif | ||
111 | |||
108 | /* | 112 | /* |
109 | * Certain CPUs may throw bizarre exceptions if not the whole cacheline | 113 | * Certain CPUs may throw bizarre exceptions if not the whole cacheline |
110 | * contains valid instructions. For these we ensure proper alignment of | 114 | * contains valid instructions. For these we ensure proper alignment of |
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index a4f85a279c52..2a109a5e0932 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h | |||
@@ -77,6 +77,7 @@ | |||
77 | #define PRID_IMP_4KEMPR2 0x9100 | 77 | #define PRID_IMP_4KEMPR2 0x9100 |
78 | #define PRID_IMP_4KSD 0x9200 | 78 | #define PRID_IMP_4KSD 0x9200 |
79 | #define PRID_IMP_24K 0x9300 | 79 | #define PRID_IMP_24K 0x9300 |
80 | #define PRID_IMP_24KE 0x9600 | ||
80 | 81 | ||
81 | #define PRID_IMP_UNKNOWN 0xff00 | 82 | #define PRID_IMP_UNKNOWN 0xff00 |
82 | 83 | ||
@@ -232,5 +233,6 @@ | |||
232 | #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ | 233 | #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ |
233 | #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ | 234 | #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ |
234 | #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ | 235 | #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ |
236 | #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */ | ||
235 | 237 | ||
236 | #endif /* _ASM_CPU_H */ | 238 | #endif /* _ASM_CPU_H */ |
diff --git a/include/asm-mips/dsp.h b/include/asm-mips/dsp.h new file mode 100644 index 000000000000..50f556bb4978 --- /dev/null +++ b/include/asm-mips/dsp.h | |||
@@ -0,0 +1,83 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2005 Mips Technologies | ||
3 | * Author: Chris Dearman, chris@mips.com derived from fpu.h | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify it | ||
6 | * under the terms of the GNU General Public License as published by the | ||
7 | * Free Software Foundation; either version 2 of the License, or (at your | ||
8 | * option) any later version. | ||
9 | */ | ||
10 | #ifndef _ASM_DSP_H | ||
11 | #define _ASM_DSP_H | ||
12 | |||
13 | #include <asm/cpu.h> | ||
14 | #include <asm/cpu-features.h> | ||
15 | #include <asm/hazards.h> | ||
16 | #include <asm/mipsregs.h> | ||
17 | |||
18 | #define DSP_DEFAULT 0x00000000 | ||
19 | #define DSP_MASK 0x1f | ||
20 | |||
21 | #define __enable_dsp_hazard() \ | ||
22 | do { \ | ||
23 | asm("_ehb"); \ | ||
24 | } while (0) | ||
25 | |||
26 | static inline void __init_dsp(void) | ||
27 | { | ||
28 | mthi1(0); | ||
29 | mtlo1(0); | ||
30 | mthi2(0); | ||
31 | mtlo2(0); | ||
32 | mthi3(0); | ||
33 | mtlo3(0); | ||
34 | wrdsp(DSP_DEFAULT, DSP_MASK); | ||
35 | } | ||
36 | |||
37 | static inline void init_dsp(void) | ||
38 | { | ||
39 | if (cpu_has_dsp) | ||
40 | __init_dsp(); | ||
41 | } | ||
42 | |||
43 | #define __save_dsp(tsk) \ | ||
44 | do { \ | ||
45 | tsk->thread.dsp.dspr[0] = mfhi1(); \ | ||
46 | tsk->thread.dsp.dspr[1] = mflo1(); \ | ||
47 | tsk->thread.dsp.dspr[2] = mfhi2(); \ | ||
48 | tsk->thread.dsp.dspr[3] = mflo2(); \ | ||
49 | tsk->thread.dsp.dspr[4] = mfhi3(); \ | ||
50 | tsk->thread.dsp.dspr[5] = mflo3(); \ | ||
51 | } while (0) | ||
52 | |||
53 | #define save_dsp(tsk) \ | ||
54 | do { \ | ||
55 | if (cpu_has_dsp) \ | ||
56 | __save_dsp(tsk); \ | ||
57 | } while (0) | ||
58 | |||
59 | #define __restore_dsp(tsk) \ | ||
60 | do { \ | ||
61 | mthi1(tsk->thread.dsp.dspr[0]); \ | ||
62 | mtlo1(tsk->thread.dsp.dspr[1]); \ | ||
63 | mthi2(tsk->thread.dsp.dspr[2]); \ | ||
64 | mtlo2(tsk->thread.dsp.dspr[3]); \ | ||
65 | mthi3(tsk->thread.dsp.dspr[4]); \ | ||
66 | mtlo3(tsk->thread.dsp.dspr[5]); \ | ||
67 | } while (0) | ||
68 | |||
69 | #define restore_dsp(tsk) \ | ||
70 | do { \ | ||
71 | if (cpu_has_dsp) \ | ||
72 | __restore_dsp(tsk); \ | ||
73 | } while (0) | ||
74 | |||
75 | #define __get_dsp_regs(tsk) \ | ||
76 | ({ \ | ||
77 | if (tsk == current) \ | ||
78 | __save_dsp(current); \ | ||
79 | \ | ||
80 | tsk->thread.dsp.dspr; \ | ||
81 | }) | ||
82 | |||
83 | #endif /* _ASM_DSP_H */ | ||
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index bb031f3cd4db..a4db9ec95665 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h | |||
@@ -193,33 +193,76 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; | |||
193 | 193 | ||
194 | #ifdef __KERNEL__ | 194 | #ifdef __KERNEL__ |
195 | 195 | ||
196 | struct mips_abi; | ||
197 | |||
198 | extern struct mips_abi mips_abi; | ||
199 | extern struct mips_abi mips_abi_32; | ||
200 | extern struct mips_abi mips_abi_n32; | ||
201 | |||
196 | #ifdef CONFIG_32BIT | 202 | #ifdef CONFIG_32BIT |
197 | 203 | ||
198 | #define SET_PERSONALITY(ex, ibcs2) \ | 204 | #define SET_PERSONALITY(ex, ibcs2) \ |
199 | do { \ | 205 | do { \ |
200 | if (ibcs2) \ | 206 | if (ibcs2) \ |
201 | set_personality(PER_SVR4); \ | 207 | set_personality(PER_SVR4); \ |
202 | set_personality(PER_LINUX); \ | 208 | set_personality(PER_LINUX); \ |
209 | \ | ||
210 | current->thread.abi = &mips_abi; \ | ||
203 | } while (0) | 211 | } while (0) |
204 | 212 | ||
205 | #endif /* CONFIG_32BIT */ | 213 | #endif /* CONFIG_32BIT */ |
206 | 214 | ||
207 | #ifdef CONFIG_64BIT | 215 | #ifdef CONFIG_64BIT |
208 | 216 | ||
209 | #define SET_PERSONALITY(ex, ibcs2) \ | 217 | #ifdef CONFIG_MIPS32_N32 |
210 | do { current->thread.mflags &= ~MF_ABI_MASK; \ | 218 | #define __SET_PERSONALITY32_N32() \ |
211 | if ((ex).e_ident[EI_CLASS] == ELFCLASS32) { \ | 219 | do { \ |
212 | if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \ | 220 | current->thread.mflags |= MF_N32; \ |
213 | ((ex).e_flags & EF_MIPS_ABI) == 0) \ | 221 | current->thread.abi = &mips_abi_n32; \ |
214 | current->thread.mflags |= MF_N32; \ | 222 | } while (0) |
215 | else \ | 223 | #else |
216 | current->thread.mflags |= MF_O32; \ | 224 | #define __SET_PERSONALITY32_N32() \ |
217 | } else \ | 225 | do { } while (0) |
218 | current->thread.mflags |= MF_N64; \ | 226 | #endif |
219 | if (ibcs2) \ | 227 | |
220 | set_personality(PER_SVR4); \ | 228 | #ifdef CONFIG_MIPS32_O32 |
221 | else if (current->personality != PER_LINUX32) \ | 229 | #define __SET_PERSONALITY32_O32() \ |
222 | set_personality(PER_LINUX); \ | 230 | do { \ |
231 | current->thread.mflags |= MF_O32; \ | ||
232 | current->thread.abi = &mips_abi_32; \ | ||
233 | } while (0) | ||
234 | #else | ||
235 | #define __SET_PERSONALITY32_O32() \ | ||
236 | do { } while (0) | ||
237 | #endif | ||
238 | |||
239 | #ifdef CONFIG_MIPS32_COMPAT | ||
240 | #define __SET_PERSONALITY32(ex) \ | ||
241 | do { \ | ||
242 | if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \ | ||
243 | ((ex).e_flags & EF_MIPS_ABI) == 0) \ | ||
244 | __SET_PERSONALITY32_N32(); \ | ||
245 | else \ | ||
246 | __SET_PERSONALITY32_O32(); \ | ||
247 | } while (0) | ||
248 | #else | ||
249 | #define __SET_PERSONALITY32(ex) do { } while (0) | ||
250 | #endif | ||
251 | |||
252 | #define SET_PERSONALITY(ex, ibcs2) \ | ||
253 | do { \ | ||
254 | current->thread.mflags &= ~MF_ABI_MASK; \ | ||
255 | if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \ | ||
256 | __SET_PERSONALITY32(ex); \ | ||
257 | else { \ | ||
258 | current->thread.mflags |= MF_N64; \ | ||
259 | current->thread.abi = &mips_abi; \ | ||
260 | } \ | ||
261 | \ | ||
262 | if (ibcs2) \ | ||
263 | set_personality(PER_SVR4); \ | ||
264 | else if (current->personality != PER_LINUX32) \ | ||
265 | set_personality(PER_LINUX); \ | ||
223 | } while (0) | 266 | } while (0) |
224 | 267 | ||
225 | #endif /* CONFIG_64BIT */ | 268 | #endif /* CONFIG_64BIT */ |
diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h index df912c2b381f..e0745f4ff624 100644 --- a/include/asm-mips/inst.h +++ b/include/asm-mips/inst.h | |||
@@ -62,10 +62,10 @@ enum rt_op { | |||
62 | spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, | 62 | spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07, |
63 | tgei_op, tgeiu_op, tlti_op, tltiu_op, | 63 | tgei_op, tgeiu_op, tlti_op, tltiu_op, |
64 | teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, | 64 | teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op, |
65 | bltzal_op, bgezal_op, bltzall_op, bgezall_op | 65 | bltzal_op, bgezal_op, bltzall_op, bgezall_op, |
66 | /* | 66 | rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17, |
67 | * The others (0x14 - 0x1f) are unused. | 67 | rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b, |
68 | */ | 68 | bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f |
69 | }; | 69 | }; |
70 | 70 | ||
71 | /* | 71 | /* |
diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h index 3c8896d9b133..a115940bd684 100644 --- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip22/cpu-feature-overrides.h | |||
@@ -23,6 +23,8 @@ | |||
23 | #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) | 23 | #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) |
24 | #define cpu_has_ic_fills_f_dc 0 | 24 | #define cpu_has_ic_fills_f_dc 0 |
25 | 25 | ||
26 | #define cpu_has_dsp 0 | ||
27 | |||
26 | #define cpu_has_nofpuex 0 | 28 | #define cpu_has_nofpuex 0 |
27 | #define cpu_has_64bits 1 | 29 | #define cpu_has_64bits 1 |
28 | 30 | ||
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h index fe96d7358517..4c8a90051fd0 100644 --- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip27/cpu-feature-overrides.h | |||
@@ -25,6 +25,7 @@ | |||
25 | #define cpu_has_vtag_icache 0 | 25 | #define cpu_has_vtag_icache 0 |
26 | #define cpu_has_dc_aliases 0 | 26 | #define cpu_has_dc_aliases 0 |
27 | #define cpu_has_ic_fills_f_dc 0 | 27 | #define cpu_has_ic_fills_f_dc 0 |
28 | #define cpu_has_dsp 0 | ||
28 | #define cpu_icache_snoops_remote_store 1 | 29 | #define cpu_icache_snoops_remote_store 1 |
29 | 30 | ||
30 | #define cpu_has_nofpuex 0 | 31 | #define cpu_has_nofpuex 0 |
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h index 04713973c6c3..ab37fc1842ba 100644 --- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h | |||
@@ -37,5 +37,6 @@ | |||
37 | #define cpu_has_ejtag 0 | 37 | #define cpu_has_ejtag 0 |
38 | #define cpu_has_vtag_icache 0 | 38 | #define cpu_has_vtag_icache 0 |
39 | #define cpu_has_ic_fills_f_dc 0 | 39 | #define cpu_has_ic_fills_f_dc 0 |
40 | #define cpu_has_dsp 0 | ||
40 | 41 | ||
41 | #endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */ | 42 | #endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */ |
diff --git a/include/asm-mips/mach-ja/cpu-feature-overrides.h b/include/asm-mips/mach-ja/cpu-feature-overrides.h index ca57e7db98bb..310609c0f4ad 100644 --- a/include/asm-mips/mach-ja/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ja/cpu-feature-overrides.h | |||
@@ -25,6 +25,7 @@ | |||
25 | #define cpu_has_vtag_icache 0 | 25 | #define cpu_has_vtag_icache 0 |
26 | #define cpu_has_dc_aliases 0 | 26 | #define cpu_has_dc_aliases 0 |
27 | #define cpu_has_ic_fills_f_dc 0 | 27 | #define cpu_has_ic_fills_f_dc 0 |
28 | #define cpu_has_dsp 0 | ||
28 | #define cpu_icache_snoops_remote_store 0 | 29 | #define cpu_icache_snoops_remote_store 0 |
29 | 30 | ||
30 | #define cpu_has_nofpuex 0 | 31 | #define cpu_has_nofpuex 0 |
diff --git a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h index 7473512384bc..1812fc0408d3 100644 --- a/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h +++ b/include/asm-mips/mach-ocelot3/cpu-feature-overrides.h | |||
@@ -28,6 +28,7 @@ | |||
28 | #define cpu_has_vtag_icache 0 | 28 | #define cpu_has_vtag_icache 0 |
29 | #define cpu_has_dc_aliases 0 | 29 | #define cpu_has_dc_aliases 0 |
30 | #define cpu_has_ic_fills_f_dc 0 | 30 | #define cpu_has_ic_fills_f_dc 0 |
31 | #define cpu_has_dsp 0 | ||
31 | #define cpu_icache_snoops_remote_store 0 | 32 | #define cpu_icache_snoops_remote_store 0 |
32 | 33 | ||
33 | #define cpu_has_nofpuex 0 | 34 | #define cpu_has_nofpuex 0 |
diff --git a/include/asm-mips/mach-rm200/cpu-feature-overrides.h b/include/asm-mips/mach-rm200/cpu-feature-overrides.h index f48736032b2a..9b2a40524679 100644 --- a/include/asm-mips/mach-rm200/cpu-feature-overrides.h +++ b/include/asm-mips/mach-rm200/cpu-feature-overrides.h | |||
@@ -31,6 +31,7 @@ | |||
31 | #define cpu_has_vtag_icache 0 | 31 | #define cpu_has_vtag_icache 0 |
32 | #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) | 32 | #define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) |
33 | #define cpu_has_ic_fills_f_dc 0 | 33 | #define cpu_has_ic_fills_f_dc 0 |
34 | #define cpu_has_dsp 0 | ||
34 | #define cpu_has_nofpuex 0 | 35 | #define cpu_has_nofpuex 0 |
35 | #define cpu_has_64bits 1 | 36 | #define cpu_has_64bits 1 |
36 | 37 | ||
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h index a3a2cc6014b2..193a666cd131 100644 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h | |||
@@ -25,6 +25,7 @@ | |||
25 | #define cpu_has_vtag_icache 1 | 25 | #define cpu_has_vtag_icache 1 |
26 | #define cpu_has_dc_aliases 0 | 26 | #define cpu_has_dc_aliases 0 |
27 | #define cpu_has_ic_fills_f_dc 0 | 27 | #define cpu_has_ic_fills_f_dc 0 |
28 | #define cpu_has_dsp 0 | ||
28 | #define cpu_icache_snoops_remote_store 0 | 29 | #define cpu_icache_snoops_remote_store 0 |
29 | 30 | ||
30 | #define cpu_has_nofpuex 0 | 31 | #define cpu_has_nofpuex 0 |
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h index 58603e3daca6..63e94342e087 100644 --- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h +++ b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h | |||
@@ -25,6 +25,7 @@ | |||
25 | #define cpu_has_vtag_icache 0 | 25 | #define cpu_has_vtag_icache 0 |
26 | #define cpu_has_dc_aliases 0 | 26 | #define cpu_has_dc_aliases 0 |
27 | #define cpu_has_ic_fills_f_dc 0 | 27 | #define cpu_has_ic_fills_f_dc 0 |
28 | #define cpu_has_dsp 0 | ||
28 | #define cpu_icache_snoops_remote_store 0 | 29 | #define cpu_icache_snoops_remote_store 0 |
29 | 30 | ||
30 | #define cpu_has_nofpuex 0 | 31 | #define cpu_has_nofpuex 0 |
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h index 9b0ce451286e..1fad6ec1daa0 100644 --- a/include/asm-mips/mipsregs.h +++ b/include/asm-mips/mipsregs.h | |||
@@ -281,6 +281,11 @@ | |||
281 | #define ST0_DL (_ULCAST_(1) << 24) | 281 | #define ST0_DL (_ULCAST_(1) << 24) |
282 | 282 | ||
283 | /* | 283 | /* |
284 | * Enable the MIPS DSP ASE | ||
285 | */ | ||
286 | #define ST0_MX 0x01000000 | ||
287 | |||
288 | /* | ||
284 | * Bitfields in the TX39 family CP0 Configuration Register 3 | 289 | * Bitfields in the TX39 family CP0 Configuration Register 3 |
285 | */ | 290 | */ |
286 | #define TX39_CONF_ICS_SHIFT 19 | 291 | #define TX39_CONF_ICS_SHIFT 19 |
@@ -510,6 +515,7 @@ | |||
510 | #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) | 515 | #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) |
511 | #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) | 516 | #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) |
512 | #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) | 517 | #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) |
518 | #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) | ||
513 | 519 | ||
514 | /* | 520 | /* |
515 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. | 521 | * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. |
@@ -986,6 +992,287 @@ do { \ | |||
986 | : "=r" (__res)); \ | 992 | : "=r" (__res)); \ |
987 | __res;}) | 993 | __res;}) |
988 | 994 | ||
995 | #define rddsp(mask) \ | ||
996 | ({ \ | ||
997 | unsigned int __res; \ | ||
998 | \ | ||
999 | __asm__ __volatile__( \ | ||
1000 | " .set push \n" \ | ||
1001 | " .set noat \n" \ | ||
1002 | " # rddsp $1, %x1 \n" \ | ||
1003 | " .word 0x7c000cb8 | (%x1 << 16) \n" \ | ||
1004 | " move %0, $1 \n" \ | ||
1005 | " .set pop \n" \ | ||
1006 | : "=r" (__res) \ | ||
1007 | : "i" (mask)); \ | ||
1008 | __res; \ | ||
1009 | }) | ||
1010 | |||
1011 | #define wrdsp(val, mask) \ | ||
1012 | do { \ | ||
1013 | unsigned int __res; \ | ||
1014 | \ | ||
1015 | __asm__ __volatile__( \ | ||
1016 | " .set push \n" \ | ||
1017 | " .set noat \n" \ | ||
1018 | " move $1, %0 \n" \ | ||
1019 | " # wrdsp $1, %x1 \n" \ | ||
1020 | " .word 0x7c2004f8 | (%x1 << 15) \n" \ | ||
1021 | " .set pop \n" \ | ||
1022 | : \ | ||
1023 | : "r" (val), "i" (mask)); \ | ||
1024 | __res; \ | ||
1025 | } while (0) | ||
1026 | |||
1027 | #if 0 /* Need DSP ASE capable assembler ... */ | ||
1028 | #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) | ||
1029 | #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) | ||
1030 | #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) | ||
1031 | #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) | ||
1032 | |||
1033 | #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) | ||
1034 | #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) | ||
1035 | #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) | ||
1036 | #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) | ||
1037 | |||
1038 | #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) | ||
1039 | #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) | ||
1040 | #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) | ||
1041 | #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) | ||
1042 | |||
1043 | #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) | ||
1044 | #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) | ||
1045 | #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) | ||
1046 | #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) | ||
1047 | |||
1048 | #else | ||
1049 | |||
1050 | #define mfhi0() \ | ||
1051 | ({ \ | ||
1052 | unsigned long __treg; \ | ||
1053 | \ | ||
1054 | __asm__ __volatile__( \ | ||
1055 | " .set push \n" \ | ||
1056 | " .set noat \n" \ | ||
1057 | " # mfhi %0, $ac0 \n" \ | ||
1058 | " .word 0x00000810 \n" \ | ||
1059 | " move %0, $1 \n" \ | ||
1060 | " .set pop \n" \ | ||
1061 | : "=r" (__treg)); \ | ||
1062 | __treg; \ | ||
1063 | }) | ||
1064 | |||
1065 | #define mfhi1() \ | ||
1066 | ({ \ | ||
1067 | unsigned long __treg; \ | ||
1068 | \ | ||
1069 | __asm__ __volatile__( \ | ||
1070 | " .set push \n" \ | ||
1071 | " .set noat \n" \ | ||
1072 | " # mfhi %0, $ac1 \n" \ | ||
1073 | " .word 0x00200810 \n" \ | ||
1074 | " move %0, $1 \n" \ | ||
1075 | " .set pop \n" \ | ||
1076 | : "=r" (__treg)); \ | ||
1077 | __treg; \ | ||
1078 | }) | ||
1079 | |||
1080 | #define mfhi2() \ | ||
1081 | ({ \ | ||
1082 | unsigned long __treg; \ | ||
1083 | \ | ||
1084 | __asm__ __volatile__( \ | ||
1085 | " .set push \n" \ | ||
1086 | " .set noat \n" \ | ||
1087 | " # mfhi %0, $ac2 \n" \ | ||
1088 | " .word 0x00400810 \n" \ | ||
1089 | " move %0, $1 \n" \ | ||
1090 | " .set pop \n" \ | ||
1091 | : "=r" (__treg)); \ | ||
1092 | __treg; \ | ||
1093 | }) | ||
1094 | |||
1095 | #define mfhi3() \ | ||
1096 | ({ \ | ||
1097 | unsigned long __treg; \ | ||
1098 | \ | ||
1099 | __asm__ __volatile__( \ | ||
1100 | " .set push \n" \ | ||
1101 | " .set noat \n" \ | ||
1102 | " # mfhi %0, $ac3 \n" \ | ||
1103 | " .word 0x00600810 \n" \ | ||
1104 | " move %0, $1 \n" \ | ||
1105 | " .set pop \n" \ | ||
1106 | : "=r" (__treg)); \ | ||
1107 | __treg; \ | ||
1108 | }) | ||
1109 | |||
1110 | #define mflo0() \ | ||
1111 | ({ \ | ||
1112 | unsigned long __treg; \ | ||
1113 | \ | ||
1114 | __asm__ __volatile__( \ | ||
1115 | " .set push \n" \ | ||
1116 | " .set noat \n" \ | ||
1117 | " # mflo %0, $ac0 \n" \ | ||
1118 | " .word 0x00000812 \n" \ | ||
1119 | " move %0, $1 \n" \ | ||
1120 | " .set pop \n" \ | ||
1121 | : "=r" (__treg)); \ | ||
1122 | __treg; \ | ||
1123 | }) | ||
1124 | |||
1125 | #define mflo1() \ | ||
1126 | ({ \ | ||
1127 | unsigned long __treg; \ | ||
1128 | \ | ||
1129 | __asm__ __volatile__( \ | ||
1130 | " .set push \n" \ | ||
1131 | " .set noat \n" \ | ||
1132 | " # mflo %0, $ac1 \n" \ | ||
1133 | " .word 0x00200812 \n" \ | ||
1134 | " move %0, $1 \n" \ | ||
1135 | " .set pop \n" \ | ||
1136 | : "=r" (__treg)); \ | ||
1137 | __treg; \ | ||
1138 | }) | ||
1139 | |||
1140 | #define mflo2() \ | ||
1141 | ({ \ | ||
1142 | unsigned long __treg; \ | ||
1143 | \ | ||
1144 | __asm__ __volatile__( \ | ||
1145 | " .set push \n" \ | ||
1146 | " .set noat \n" \ | ||
1147 | " # mflo %0, $ac2 \n" \ | ||
1148 | " .word 0x00400812 \n" \ | ||
1149 | " move %0, $1 \n" \ | ||
1150 | " .set pop \n" \ | ||
1151 | : "=r" (__treg)); \ | ||
1152 | __treg; \ | ||
1153 | }) | ||
1154 | |||
1155 | #define mflo3() \ | ||
1156 | ({ \ | ||
1157 | unsigned long __treg; \ | ||
1158 | \ | ||
1159 | __asm__ __volatile__( \ | ||
1160 | " .set push \n" \ | ||
1161 | " .set noat \n" \ | ||
1162 | " # mflo %0, $ac3 \n" \ | ||
1163 | " .word 0x00600812 \n" \ | ||
1164 | " move %0, $1 \n" \ | ||
1165 | " .set pop \n" \ | ||
1166 | : "=r" (__treg)); \ | ||
1167 | __treg; \ | ||
1168 | }) | ||
1169 | |||
1170 | #define mthi0(x) \ | ||
1171 | do { \ | ||
1172 | __asm__ __volatile__( \ | ||
1173 | " .set push \n" \ | ||
1174 | " .set noat \n" \ | ||
1175 | " move $1, %0 \n" \ | ||
1176 | " # mthi $1, $ac0 \n" \ | ||
1177 | " .word 0x00200011 \n" \ | ||
1178 | " .set pop \n" \ | ||
1179 | : \ | ||
1180 | : "r" (x)); \ | ||
1181 | } while (0) | ||
1182 | |||
1183 | #define mthi1(x) \ | ||
1184 | do { \ | ||
1185 | __asm__ __volatile__( \ | ||
1186 | " .set push \n" \ | ||
1187 | " .set noat \n" \ | ||
1188 | " move $1, %0 \n" \ | ||
1189 | " # mthi $1, $ac1 \n" \ | ||
1190 | " .word 0x00200811 \n" \ | ||
1191 | " .set pop \n" \ | ||
1192 | : \ | ||
1193 | : "r" (x)); \ | ||
1194 | } while (0) | ||
1195 | |||
1196 | #define mthi2(x) \ | ||
1197 | do { \ | ||
1198 | __asm__ __volatile__( \ | ||
1199 | " .set push \n" \ | ||
1200 | " .set noat \n" \ | ||
1201 | " move $1, %0 \n" \ | ||
1202 | " # mthi $1, $ac2 \n" \ | ||
1203 | " .word 0x00201011 \n" \ | ||
1204 | " .set pop \n" \ | ||
1205 | : \ | ||
1206 | : "r" (x)); \ | ||
1207 | } while (0) | ||
1208 | |||
1209 | #define mthi3(x) \ | ||
1210 | do { \ | ||
1211 | __asm__ __volatile__( \ | ||
1212 | " .set push \n" \ | ||
1213 | " .set noat \n" \ | ||
1214 | " move $1, %0 \n" \ | ||
1215 | " # mthi $1, $ac3 \n" \ | ||
1216 | " .word 0x00201811 \n" \ | ||
1217 | " .set pop \n" \ | ||
1218 | : \ | ||
1219 | : "r" (x)); \ | ||
1220 | } while (0) | ||
1221 | |||
1222 | #define mtlo0(x) \ | ||
1223 | do { \ | ||
1224 | __asm__ __volatile__( \ | ||
1225 | " .set push \n" \ | ||
1226 | " .set noat \n" \ | ||
1227 | " move $1, %0 \n" \ | ||
1228 | " # mtlo $1, $ac0 \n" \ | ||
1229 | " .word 0x00200013 \n" \ | ||
1230 | " .set pop \n" \ | ||
1231 | : \ | ||
1232 | : "r" (x)); \ | ||
1233 | } while (0) | ||
1234 | |||
1235 | #define mtlo1(x) \ | ||
1236 | do { \ | ||
1237 | __asm__ __volatile__( \ | ||
1238 | " .set push \n" \ | ||
1239 | " .set noat \n" \ | ||
1240 | " move $1, %0 \n" \ | ||
1241 | " # mtlo $1, $ac1 \n" \ | ||
1242 | " .word 0x00200813 \n" \ | ||
1243 | " .set pop \n" \ | ||
1244 | : \ | ||
1245 | : "r" (x)); \ | ||
1246 | } while (0) | ||
1247 | |||
1248 | #define mtlo2(x) \ | ||
1249 | do { \ | ||
1250 | __asm__ __volatile__( \ | ||
1251 | " .set push \n" \ | ||
1252 | " .set noat \n" \ | ||
1253 | " move $1, %0 \n" \ | ||
1254 | " # mtlo $1, $ac2 \n" \ | ||
1255 | " .word 0x00201013 \n" \ | ||
1256 | " .set pop \n" \ | ||
1257 | : \ | ||
1258 | : "r" (x)); \ | ||
1259 | } while (0) | ||
1260 | |||
1261 | #define mtlo3(x) \ | ||
1262 | do { \ | ||
1263 | __asm__ __volatile__( \ | ||
1264 | " .set push \n" \ | ||
1265 | " .set noat \n" \ | ||
1266 | " move $1, %0 \n" \ | ||
1267 | " # mtlo $1, $ac3 \n" \ | ||
1268 | " .word 0x00201813 \n" \ | ||
1269 | " .set pop \n" \ | ||
1270 | : \ | ||
1271 | : "r" (x)); \ | ||
1272 | } while (0) | ||
1273 | |||
1274 | #endif | ||
1275 | |||
989 | /* | 1276 | /* |
990 | * TLB operations. | 1277 | * TLB operations. |
991 | * | 1278 | * |
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h index d6466aa09fb7..f1980c6c3bcc 100644 --- a/include/asm-mips/processor.h +++ b/include/asm-mips/processor.h | |||
@@ -96,12 +96,26 @@ union mips_fpu_union { | |||
96 | {{0,},} \ | 96 | {{0,},} \ |
97 | } | 97 | } |
98 | 98 | ||
99 | #define NUM_DSP_REGS 6 | ||
100 | |||
101 | typedef __u32 dspreg_t; | ||
102 | |||
103 | struct mips_dsp_state { | ||
104 | dspreg_t dspr[NUM_DSP_REGS]; | ||
105 | unsigned int dspcontrol; | ||
106 | unsigned short used_dsp; | ||
107 | }; | ||
108 | |||
109 | #define INIT_DSP {{0,},} | ||
110 | |||
99 | typedef struct { | 111 | typedef struct { |
100 | unsigned long seg; | 112 | unsigned long seg; |
101 | } mm_segment_t; | 113 | } mm_segment_t; |
102 | 114 | ||
103 | #define ARCH_MIN_TASKALIGN 8 | 115 | #define ARCH_MIN_TASKALIGN 8 |
104 | 116 | ||
117 | struct mips_abi; | ||
118 | |||
105 | /* | 119 | /* |
106 | * If you change thread_struct remember to change the #defines below too! | 120 | * If you change thread_struct remember to change the #defines below too! |
107 | */ | 121 | */ |
@@ -117,6 +131,9 @@ struct thread_struct { | |||
117 | /* Saved fpu/fpu emulator stuff. */ | 131 | /* Saved fpu/fpu emulator stuff. */ |
118 | union mips_fpu_union fpu; | 132 | union mips_fpu_union fpu; |
119 | 133 | ||
134 | /* Saved state of the DSP ASE, if available. */ | ||
135 | struct mips_dsp_state dsp; | ||
136 | |||
120 | /* Other stuff associated with the thread. */ | 137 | /* Other stuff associated with the thread. */ |
121 | unsigned long cp0_badvaddr; /* Last user fault */ | 138 | unsigned long cp0_badvaddr; /* Last user fault */ |
122 | unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ | 139 | unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */ |
@@ -129,6 +146,7 @@ struct thread_struct { | |||
129 | unsigned long mflags; | 146 | unsigned long mflags; |
130 | unsigned long irix_trampoline; /* Wheee... */ | 147 | unsigned long irix_trampoline; /* Wheee... */ |
131 | unsigned long irix_oldctx; | 148 | unsigned long irix_oldctx; |
149 | struct mips_abi *abi; | ||
132 | }; | 150 | }; |
133 | 151 | ||
134 | #define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR) | 152 | #define MF_ABI_MASK (MF_32BIT_REGS | MF_32BIT_ADDR) |
@@ -151,6 +169,10 @@ struct thread_struct { | |||
151 | */ \ | 169 | */ \ |
152 | INIT_FPU, \ | 170 | INIT_FPU, \ |
153 | /* \ | 171 | /* \ |
172 | * saved dsp/dsp emulator stuff \ | ||
173 | */ \ | ||
174 | INIT_DSP, \ | ||
175 | /* \ | ||
154 | * Other stuff associated with the process \ | 176 | * Other stuff associated with the process \ |
155 | */ \ | 177 | */ \ |
156 | 0, 0, 0, 0, \ | 178 | 0, 0, 0, 0, \ |
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h index 2b5c624c3d4f..8441a5ae96e3 100644 --- a/include/asm-mips/ptrace.h +++ b/include/asm-mips/ptrace.h | |||
@@ -22,6 +22,8 @@ | |||
22 | #define MMLO 68 | 22 | #define MMLO 68 |
23 | #define FPC_CSR 69 | 23 | #define FPC_CSR 69 |
24 | #define FPC_EIR 70 | 24 | #define FPC_EIR 70 |
25 | #define DSP_BASE 71 /* 3 more hi / lo register pairs */ | ||
26 | #define DSP_CONTROL 77 | ||
25 | 27 | ||
26 | /* | 28 | /* |
27 | * This struct defines the way the registers are stored on the stack during a | 29 | * This struct defines the way the registers are stored on the stack during a |
@@ -38,8 +40,8 @@ struct pt_regs { | |||
38 | 40 | ||
39 | /* Saved special registers. */ | 41 | /* Saved special registers. */ |
40 | unsigned long cp0_status; | 42 | unsigned long cp0_status; |
41 | unsigned long lo; | ||
42 | unsigned long hi; | 43 | unsigned long hi; |
44 | unsigned long lo; | ||
43 | unsigned long cp0_badvaddr; | 45 | unsigned long cp0_badvaddr; |
44 | unsigned long cp0_cause; | 46 | unsigned long cp0_cause; |
45 | unsigned long cp0_epc; | 47 | unsigned long cp0_epc; |
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h index f7fbebaa0744..8edabb0be23f 100644 --- a/include/asm-mips/sigcontext.h +++ b/include/asm-mips/sigcontext.h | |||
@@ -27,14 +27,15 @@ struct sigcontext { | |||
27 | unsigned int sc_fpc_csr; | 27 | unsigned int sc_fpc_csr; |
28 | unsigned int sc_fpc_eir; /* Unused */ | 28 | unsigned int sc_fpc_eir; /* Unused */ |
29 | unsigned int sc_used_math; | 29 | unsigned int sc_used_math; |
30 | unsigned int sc_ssflags; /* Unused */ | 30 | unsigned int sc_dsp; /* dsp status, was sc_ssflags */ |
31 | unsigned long long sc_mdhi; | 31 | unsigned long long sc_mdhi; |
32 | unsigned long long sc_mdlo; | 32 | unsigned long long sc_mdlo; |
33 | 33 | unsigned long sc_hi1; /* Was sc_cause */ | |
34 | unsigned int sc_cause; /* Unused */ | 34 | unsigned long sc_lo1; /* Was sc_badvaddr */ |
35 | unsigned int sc_badvaddr; /* Unused */ | 35 | unsigned long sc_hi2; /* Was sc_sigset[4] */ |
36 | 36 | unsigned long sc_lo2; | |
37 | unsigned long sc_sigset[4]; /* kernel's sigset_t */ | 37 | unsigned long sc_hi3; |
38 | unsigned long sc_lo3; | ||
38 | }; | 39 | }; |
39 | 40 | ||
40 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ | 41 | #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */ |
@@ -48,19 +49,19 @@ struct sigcontext { | |||
48 | * Warning: this structure illdefined with sc_badvaddr being just an unsigned | 49 | * Warning: this structure illdefined with sc_badvaddr being just an unsigned |
49 | * int so it was changed to unsigned long in 2.6.0-test1. This may break | 50 | * int so it was changed to unsigned long in 2.6.0-test1. This may break |
50 | * binary compatibility - no prisoners. | 51 | * binary compatibility - no prisoners. |
52 | * DSP ASE in 2.6.12-rc4. Turn sc_mdhi and sc_mdlo into an array of four | ||
53 | * entries, add sc_dsp and sc_reserved for padding. No prisoners. | ||
51 | */ | 54 | */ |
52 | struct sigcontext { | 55 | struct sigcontext { |
53 | unsigned long sc_regs[32]; | 56 | unsigned long sc_regs[32]; |
54 | unsigned long sc_fpregs[32]; | 57 | unsigned long sc_fpregs[32]; |
55 | unsigned long sc_mdhi; | 58 | unsigned long sc_hi[4]; |
56 | unsigned long sc_mdlo; | 59 | unsigned long sc_lo[4]; |
57 | unsigned long sc_pc; | 60 | unsigned long sc_pc; |
58 | unsigned long sc_badvaddr; | ||
59 | unsigned int sc_status; | ||
60 | unsigned int sc_fpc_csr; | 61 | unsigned int sc_fpc_csr; |
61 | unsigned int sc_fpc_eir; | ||
62 | unsigned int sc_used_math; | 62 | unsigned int sc_used_math; |
63 | unsigned int sc_cause; | 63 | unsigned int sc_dsp; |
64 | unsigned int sc_reserved; | ||
64 | }; | 65 | }; |
65 | 66 | ||
66 | #ifdef __KERNEL__ | 67 | #ifdef __KERNEL__ |
@@ -68,23 +69,24 @@ struct sigcontext { | |||
68 | #include <linux/posix_types.h> | 69 | #include <linux/posix_types.h> |
69 | 70 | ||
70 | struct sigcontext32 { | 71 | struct sigcontext32 { |
71 | __u32 sc_regmask; /* Unused */ | 72 | __u32 sc_regmask; /* Unused */ |
72 | __u32 sc_status; | 73 | __u32 sc_status; |
73 | __u64 sc_pc; | 74 | __u64 sc_pc; |
74 | __u64 sc_regs[32]; | 75 | __u64 sc_regs[32]; |
75 | __u64 sc_fpregs[32]; | 76 | __u64 sc_fpregs[32]; |
76 | __u32 sc_ownedfp; /* Unused */ | 77 | __u32 sc_ownedfp; /* Unused */ |
77 | __u32 sc_fpc_csr; | 78 | __u32 sc_fpc_csr; |
78 | __u32 sc_fpc_eir; /* Unused */ | 79 | __u32 sc_fpc_eir; /* Unused */ |
79 | __u32 sc_used_math; | 80 | __u32 sc_used_math; |
80 | __u32 sc_ssflags; /* Unused */ | 81 | __u32 sc_dsp; /* dsp status, was sc_ssflags */ |
81 | __u64 sc_mdhi; | 82 | __u64 sc_mdhi; |
82 | __u64 sc_mdlo; | 83 | __u64 sc_mdlo; |
83 | 84 | __u32 sc_hi1; /* Was sc_cause */ | |
84 | __u32 sc_cause; /* Unused */ | 85 | __u32 sc_lo1; /* Was sc_badvaddr */ |
85 | __u32 sc_badvaddr; /* Unused */ | 86 | __u32 sc_hi2; /* Was sc_sigset[4] */ |
86 | 87 | __u32 sc_lo2; | |
87 | __u32 sc_sigset[4]; /* kernel's sigset_t */ | 88 | __u32 sc_hi3; |
89 | __u32 sc_lo3; | ||
88 | }; | 90 | }; |
89 | #endif /* __KERNEL__ */ | 91 | #endif /* __KERNEL__ */ |
90 | 92 | ||
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h index f2c470f1d369..8ca539e80d87 100644 --- a/include/asm-mips/signal.h +++ b/include/asm-mips/signal.h | |||
@@ -98,12 +98,39 @@ typedef unsigned long old_sigset_t; /* at least 32 bits */ | |||
98 | #define MINSIGSTKSZ 2048 | 98 | #define MINSIGSTKSZ 2048 |
99 | #define SIGSTKSZ 8192 | 99 | #define SIGSTKSZ 8192 |
100 | 100 | ||
101 | #ifdef __KERNEL__ | ||
102 | |||
103 | /* | ||
104 | * These values of sa_flags are used only by the kernel as part of the | ||
105 | * irq handling routines. | ||
106 | * | ||
107 | * SA_INTERRUPT is also used by the irq handling routines. | ||
108 | * SA_SHIRQ flag is for shared interrupt support on PCI and EISA. | ||
109 | */ | ||
110 | #define SA_SAMPLE_RANDOM SA_RESTART | ||
111 | |||
112 | #ifdef CONFIG_TRAD_SIGNALS | ||
113 | #define sig_uses_siginfo(ka) ((ka)->sa.sa_flags & SA_SIGINFO) | ||
114 | #else | ||
115 | #define sig_uses_siginfo(ka) (1) | ||
116 | #endif | ||
117 | |||
118 | #endif /* __KERNEL__ */ | ||
119 | |||
101 | #define SIG_BLOCK 1 /* for blocking signals */ | 120 | #define SIG_BLOCK 1 /* for blocking signals */ |
102 | #define SIG_UNBLOCK 2 /* for unblocking signals */ | 121 | #define SIG_UNBLOCK 2 /* for unblocking signals */ |
103 | #define SIG_SETMASK 3 /* for setting the signal mask */ | 122 | #define SIG_SETMASK 3 /* for setting the signal mask */ |
104 | #define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility: | 123 | #define SIG_SETMASK32 256 /* Goodie from SGI for BSD compatibility: |
105 | set only the low 32 bit of the sigset. */ | 124 | set only the low 32 bit of the sigset. */ |
106 | #include <asm-generic/signal.h> | 125 | |
126 | /* Type of a signal handler. */ | ||
127 | typedef void __signalfn_t(int); | ||
128 | typedef __signalfn_t __user *__sighandler_t; | ||
129 | |||
130 | /* Fake signal functions */ | ||
131 | #define SIG_DFL ((__sighandler_t)0) /* default signal handling */ | ||
132 | #define SIG_IGN ((__sighandler_t)1) /* ignore signal */ | ||
133 | #define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ | ||
107 | 134 | ||
108 | struct sigaction { | 135 | struct sigaction { |
109 | unsigned int sa_flags; | 136 | unsigned int sa_flags; |
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 6663efd49b27..cd3a6bca7abd 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h | |||
@@ -17,6 +17,7 @@ | |||
17 | 17 | ||
18 | #include <asm/addrspace.h> | 18 | #include <asm/addrspace.h> |
19 | #include <asm/cpu-features.h> | 19 | #include <asm/cpu-features.h> |
20 | #include <asm/dsp.h> | ||
20 | #include <asm/ptrace.h> | 21 | #include <asm/ptrace.h> |
21 | #include <asm/war.h> | 22 | #include <asm/war.h> |
22 | #include <asm/interrupt.h> | 23 | #include <asm/interrupt.h> |
@@ -154,9 +155,13 @@ extern asmlinkage void *resume(void *last, void *next, void *next_ti); | |||
154 | 155 | ||
155 | struct task_struct; | 156 | struct task_struct; |
156 | 157 | ||
157 | #define switch_to(prev,next,last) \ | 158 | #define switch_to(prev,next,last) \ |
158 | do { \ | 159 | do { \ |
159 | (last) = resume(prev, next, next->thread_info); \ | 160 | if (cpu_has_dsp) \ |
161 | __save_dsp(prev); \ | ||
162 | (last) = resume(prev, next, next->thread_info); \ | ||
163 | if (cpu_has_dsp) \ | ||
164 | __restore_dsp(current); \ | ||
160 | } while(0) | 165 | } while(0) |
161 | 166 | ||
162 | #define ROT_IN_PIECES \ | 167 | #define ROT_IN_PIECES \ |