Merge /spare/repo/linux-2.6/

89 files changed, 585 insertions, 1100 deletions

diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h
index e42b3093e903..2b3dc3bed4da 100644
--- a/include/asm-mips/a.out.h
+++ b/include/asm-mips/a.out.h
@@ -35,10 +35,10 @@ struct exec
 
 #ifdef __KERNEL__
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define STACK_TOP       TASK_SIZE
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #define STACK_TOP       (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE)
 #endif
 
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 2caa8c427204..7dc2619f5006 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -48,7 +48,7 @@
 #define CPHYSADDR(a)            ((_ACAST32_ (a)) & 0x1fffffff)
 #define XPHYSADDR(a)            ((_ACAST64_ (a)) & 0x000000ffffffffff)
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 /*
  * Memory segments (64bit kernel mode addresses)
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
index 37a460aa0378..30b18ea6cb11 100644
--- a/include/asm-mips/asmmacro.h
+++ b/include/asm-mips/asmmacro.h
@@ -7,14 +7,14 @@
  */
 #ifndef _ASM_ASMMACRO_H
 #define _ASM_ASMMACRO_H
- 
+
 #include <linux/config.h>
 #include <asm/hazards.h>
- 
-#ifdef CONFIG_MIPS32
+
+#ifdef CONFIG_32BIT
 #include <asm/asmmacro-32.h>
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #include <asm/asmmacro-64.h>
 #endif
 
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 7d89e87bc8c6..c0bd8d014e14 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -334,7 +334,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
  */
 #define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0)
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 typedef struct { volatile __s64 counter; } atomic64_t;
 
@@ -639,7 +639,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
  */
 #define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0)
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 /*
  * atomic*_return operations are serializing but not the non-*_return
diff --git a/include/asm-mips/auxvec.h b/include/asm-mips/auxvec.h
new file mode 100644
index 000000000000..7cf7f2d21943
--- /dev/null
+++ b/include/asm-mips/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef _ASM_AUXVEC_H
+#define _ASM_AUXVEC_H
+
+#endif /* _ASM_AUXVEC_H */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 779d2187a6a4..eb8d79dba11c 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -20,13 +20,13 @@
 #define SZLONG_MASK 31UL
 #define __LL    "ll     "
 #define __SC    "sc     "
-#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x)) 
+#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
 #elif (_MIPS_SZLONG == 64)
 #define SZLONG_LOG 6
 #define SZLONG_MASK 63UL
 #define __LL    "lld    "
 #define __SC    "scd    "
-#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x)) 
+#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
 #endif
 
 #ifdef __KERNEL__
@@ -533,14 +533,14 @@ static inline unsigned long ffz(unsigned long word)
         int b = 0, s;
 
         word = ~word;
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
         s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s;
         s =  8; if (word << 24 != 0) s = 0; b += s; word >>= s;
         s =  4; if (word << 28 != 0) s = 0; b += s; word >>= s;
         s =  2; if (word << 30 != 0) s = 0; b += s; word >>= s;
         s =  1; if (word << 31 != 0) s = 0; b += s;
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
         s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s;
         s = 16; if (word << 48 != 0) s = 0; b += s; word >>= s;
         s =  8; if (word << 56 != 0) s = 0; b += s; word >>= s;
@@ -683,7 +683,7 @@ found_middle:
  */
 static inline int sched_find_first_bit(const unsigned long *b)
 {
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
         if (unlikely(b[0]))
                 return __ffs(b[0]);
         if (unlikely(b[1]))
@@ -694,7 +694,7 @@ static inline int sched_find_first_bit(const unsigned long *b)
                 return __ffs(b[3]) + 96;
         return __ffs(b[4]) + 128;
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
         if (unlikely(b[0]))
                 return __ffs(b[0]);
         if (unlikely(b[1]))
diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h
index 18cced19cca4..b14b961c2100 100644
--- a/include/asm-mips/bugs.h
+++ b/include/asm-mips/bugs.h
@@ -15,7 +15,7 @@ extern void check_bugs64(void);
 static inline void check_bugs(void)
 {
         check_bugs32();
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
         check_bugs64();
 #endif
 }
diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h
index c25cc92b9950..c1ea5a8714f3 100644
--- a/include/asm-mips/checksum.h
+++ b/include/asm-mips/checksum.h
@@ -128,7 +128,7 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr,
 {
         __asm__(
         ".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t"
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
         "addu\t%0, %2\n\t"
         "sltu\t$1, %0, %2\n\t"
         "addu\t%0, $1\n\t"
@@ -141,7 +141,7 @@ static inline unsigned int csum_tcpudp_nofold(unsigned long saddr,
         "sltu\t$1, %0, %4\n\t"
         "addu\t%0, $1\n\t"
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
         "daddu\t%0, %2\n\t"
         "daddu\t%0, %3\n\t"
         "daddu\t%0, %4\n\t"
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h
index d78002afb1e1..2c084cd4bc0a 100644
--- a/include/asm-mips/compat.h
+++ b/include/asm-mips/compat.h
@@ -15,8 +15,10 @@ typedef s32		compat_clock_t;
 typedef s32             compat_suseconds_t;
 
 typedef s32             compat_pid_t;
-typedef s32             compat_uid_t;
-typedef s32             compat_gid_t;
+typedef u32             __compat_uid_t;
+typedef u32             __compat_gid_t;
+typedef u32             __compat_uid32_t;
+typedef u32             __compat_gid32_t;
 typedef u32             compat_mode_t;
 typedef u32             compat_ino_t;
 typedef u32             compat_dev_t;
@@ -52,8 +54,8 @@ struct compat_stat {
         compat_ino_t    st_ino;
         compat_mode_t   st_mode;
         compat_nlink_t  st_nlink;
-        compat_uid_t    st_uid;
-        compat_gid_t    st_gid;
+        __compat_uid32_t        st_uid;
+        __compat_gid32_t        st_gid;
         compat_dev_t    st_rdev;
         s32             st_pad2[2];
         compat_off_t    st_size;
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 1df2c299de82..9a2de642eee6 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -106,7 +106,7 @@
 #define PLAT_TRAMPOLINE_STUFF_LINE      0UL
 #endif
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 # ifndef cpu_has_nofpuex
 # define cpu_has_nofpuex        (cpu_data[0].options & MIPS_CPU_NOFPUEX)
 # endif
@@ -124,7 +124,7 @@
 # endif
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 # ifndef cpu_has_nofpuex
 # define cpu_has_nofpuex                0
 # endif
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h
index ae3e2a38fd5f..a438548e6ef3 100644
--- a/include/asm-mips/ddb5xxx/ddb5477.h
+++ b/include/asm-mips/ddb5xxx/ddb5477.h
@@ -247,7 +247,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
  *  All PCI irq but INTC are active low.
  */
 
-/* 
+/*
  * irq number block assignment
  */
 
@@ -285,7 +285,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
 #define VRC5477_IRQ_IOPCI_INTB  (17 + VRC5477_IRQ_BASE)      /* USB-P */
 #define VRC5477_IRQ_IOPCI_INTC  (18 + VRC5477_IRQ_BASE)      /* AC97 */
 #define VRC5477_IRQ_IOPCI_INTD  (19 + VRC5477_IRQ_BASE)      /* Reserved */
-#define VRC5477_IRQ_UART1       (20 + VRC5477_IRQ_BASE)     
+#define VRC5477_IRQ_UART1       (20 + VRC5477_IRQ_BASE)
 #define VRC5477_IRQ_SPT0        (21 + VRC5477_IRQ_BASE)      /* special purpose timer 0 */
 #define VRC5477_IRQ_GPT0        (22 + VRC5477_IRQ_BASE)      /* general purpose timer 0 */
 #define VRC5477_IRQ_GPT1        (23 + VRC5477_IRQ_BASE)      /* general purpose timer 1 */
@@ -301,7 +301,7 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq);
 /*
  * i2859 irq assignment
  */
-#define I8259_IRQ_RESERVED_0    (0 + I8259_IRQ_BASE)    
+#define I8259_IRQ_RESERVED_0    (0 + I8259_IRQ_BASE)
 #define I8259_IRQ_KEYBOARD      (1 + I8259_IRQ_BASE)    /* M1543 default */
 #define I8259_IRQ_CASCADE       (2 + I8259_IRQ_BASE)
 #define I8259_IRQ_UART_B        (3 + I8259_IRQ_BASE)    /* M1543 default, may conflict with RTC according to schematic diagram  */
diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h
index b63e2f2317d1..a05d6d3395fe 100644
--- a/include/asm-mips/dec/prom.h
+++ b/include/asm-mips/dec/prom.h
@@ -48,15 +48,15 @@
  */
 #define REX_PROM_MAGIC          0x30464354
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define prom_is_rex(magic)      1       /* KN04 and KN05 are REX PROMs.  */
 
-#else /* !CONFIG_MIPS64 */
+#else /* !CONFIG_64BIT */
 
 #define prom_is_rex(magic)      ((magic) == REX_PROM_MAGIC)
 
-#endif /* !CONFIG_MIPS64 */
+#endif /* !CONFIG_64BIT */
 
 
 /*
@@ -105,7 +105,7 @@ extern int (*__pmax_read)(int, void *, int);
 extern int (*__pmax_close)(int);
 
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 /*
  * On MIPS64 we have to call PROM functions via a helper
@@ -138,7 +138,7 @@ int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32;
 #define prom_getenv(x)          _prom_getenv(__prom_getenv, x)
 #define prom_printf(x...)       _prom_printf(__prom_printf, x)
 
-#else /* !CONFIG_MIPS64 */
+#else /* !CONFIG_64BIT */
 
 /*
  * On plain MIPS we just call PROM functions directly.
@@ -160,7 +160,7 @@ int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32;
 #define pmax_read               __pmax_read
 #define pmax_close              __pmax_close
 
-#endif /* !CONFIG_MIPS64 */
+#endif /* !CONFIG_64BIT */
 
 
 extern void prom_meminit(u32);
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
index d0f68447e5a7..a606dbee0412 100644
--- a/include/asm-mips/delay.h
+++ b/include/asm-mips/delay.h
@@ -57,11 +57,11 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
          * The common rates of 1000 and 128 are rounded wrongly by the
          * catchall case for 64-bit.  Excessive precission?  Probably ...
          */
-#if defined(CONFIG_MIPS64) && (HZ == 128)
+#if defined(CONFIG_64BIT) && (HZ == 128)
         usecs *= 0x0008637bd05af6c7UL;          /* 2**64 / (1000000 / HZ) */
-#elif defined(CONFIG_MIPS64) && (HZ == 1000)
+#elif defined(CONFIG_64BIT) && (HZ == 1000)
         usecs *= 0x004189374BC6A7f0UL;          /* 2**64 / (1000000 / HZ) */
-#elif defined(CONFIG_MIPS64)
+#elif defined(CONFIG_64BIT)
         usecs *= (0x8000000000000000UL / (500000 / HZ));
 #else /* 32-bit junk follows here */
         usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) +
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h
index 7b92c8045cc2..e48811440015 100644
--- a/include/asm-mips/elf.h
+++ b/include/asm-mips/elf.h
@@ -125,7 +125,7 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG];
 typedef double elf_fpreg_t;
 typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 /*
  * This is used to ensure we don't load something for the wrong architecture.
@@ -153,9 +153,9 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
  */
 #define ELF_CLASS       ELFCLASS32
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 /*
  * This is used to ensure we don't load something for the wrong architecture.
  */
@@ -177,7 +177,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
  */
 #define ELF_CLASS       ELFCLASS64
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 /*
  * These are used to set parameters in the core dumps.
@@ -193,7 +193,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 
 #ifdef __KERNEL__
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define SET_PERSONALITY(ex, ibcs2)                      \
 do {                                                    \
@@ -202,9 +202,9 @@ do {							\
         set_personality(PER_LINUX);                     \
 } while (0)
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define SET_PERSONALITY(ex, ibcs2)                              \
 do {    current->thread.mflags &= ~MF_ABI_MASK;                 \
@@ -222,7 +222,7 @@ do {	current->thread.mflags &= ~MF_ABI_MASK;			\
                 set_personality(PER_LINUX);                     \
 } while (0)
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 extern void dump_regs(elf_greg_t *, struct pt_regs *regs);
 extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h
index 2436392e7990..06c5d13faf66 100644
--- a/include/asm-mips/fcntl.h
+++ b/include/asm-mips/fcntl.h
@@ -8,33 +8,16 @@
 #ifndef _ASM_FCNTL_H
 #define _ASM_FCNTL_H
 
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_ACCMODE       0x0003
-#define O_RDONLY        0x0000
-#define O_WRONLY        0x0001
-#define O_RDWR          0x0002
 #define O_APPEND        0x0008
 #define O_SYNC          0x0010
 #define O_NONBLOCK      0x0080
 #define O_CREAT         0x0100  /* not fcntl */
-#define O_TRUNC         0x0200  /* not fcntl */
 #define O_EXCL          0x0400  /* not fcntl */
 #define O_NOCTTY        0x0800  /* not fcntl */
 #define FASYNC          0x1000  /* fcntl, for BSD compatibility */
 #define O_LARGEFILE     0x2000  /* allow large file opens */
 #define O_DIRECT        0x8000  /* direct disk access hint */
-#define O_DIRECTORY     0x10000 /* must be a directory */
-#define O_NOFOLLOW      0x20000 /* don't follow links */
-#define O_NOATIME       0x40000
 
-#define O_NDELAY        O_NONBLOCK
-
-#define F_DUPFD         0       /* dup */
-#define F_GETFD         1       /* get close_on_exec */
-#define F_SETFD         2       /* set/clear close_on_exec */
-#define F_GETFL         3       /* get file->f_flags */
-#define F_SETFL         4       /* set file->f_flags */
 #define F_GETLK         14
 #define F_SETLK         6
 #define F_SETLKW        7
@@ -50,33 +33,6 @@
 #define F_SETLKW64      35
 #endif
 
-/* for F_[GET|SET]FL */
-#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         0
-#define F_WRLCK         1
-#define F_UNLCK         2
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         4       /* or 3 */
-#define F_SHLCK         8       /* or 4 */
-
-/* for leases */
-#define F_INPROGRESS    16
-
-/* operations for bsd flock(), also used by the kernel implementation */
-#define LOCK_SH         1       /* shared lock */
-#define LOCK_EX         2       /* exclusive lock */
-#define LOCK_NB         4       /* or'd with one of the above to prevent
-                                   blocking */
-#define LOCK_UN         8       /* remove lock */
-
-#define LOCK_MAND       32      /* This is a mandatory flock */
-#define LOCK_READ       64      /* ... Which allows concurrent read operations */
-#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
-#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
-
 /*
  * The flavours of struct flock.  "struct flock" is the ABI compliant
  * variant.  Finally struct flock64 is the LFS variant of struct flock.  As
@@ -86,7 +42,7 @@
 
 #ifndef __mips64
 
-typedef struct flock {
+struct flock {
         short   l_type;
         short   l_whence;
         __kernel_off_t l_start;
@@ -94,32 +50,17 @@ typedef struct flock {
         long    l_sysid;
         __kernel_pid_t l_pid;
         long    pad[4];
-} flock_t;
-
-typedef struct flock64 {
-        short   l_type;
-        short   l_whence;
-        loff_t  l_start;
-        loff_t  l_len;
-        pid_t   l_pid;
-} flock64_t;
+};
 
-#else /* 64-bit definitions */
+#define HAVE_ARCH_STRUCT_FLOCK
 
-typedef struct flock {
-        short   l_type;
-        short   l_whence;
-        __kernel_off_t l_start;
-        __kernel_off_t l_len;
-        __kernel_pid_t l_pid;
-} flock_t;
-
-#ifdef __KERNEL__
-#define flock64         flock
 #endif
 
-#endif
+#include <asm-generic/fcntl.h>
 
-#define F_LINUX_SPECIFIC_BASE   1024
+typedef struct flock flock_t;
+#ifndef __mips64
+typedef struct flock64 flock64_t;
+#endif
 
 #endif /* _ASM_FCNTL_H */
diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h
index 1d9aa0979181..2b5fddc8f487 100644
--- a/include/asm-mips/fpregdef.h
+++ b/include/asm-mips/fpregdef.h
@@ -13,7 +13,7 @@
 #define _ASM_FPREGDEF_H
 
 #include <asm/sgidefs.h>
-                                                                                
+
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 /*
@@ -56,7 +56,7 @@
 #define fcr31   $31      /* FPU status register */
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-                                                                                
+
 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
 
 #define fv0     $f0     /* return value */
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
index 6cb38d5c0407..ea24e733b1bc 100644
--- a/include/asm-mips/fpu.h
+++ b/include/asm-mips/fpu.h
@@ -82,7 +82,7 @@ do {									\
 
 static inline int is_fpu_owner(void)
 {
-        return cpu_has_fpu && test_thread_flag(TIF_USEDFPU); 
+        return cpu_has_fpu && test_thread_flag(TIF_USEDFPU);
 }
 
 static inline void own_fpu(void)
@@ -90,7 +90,7 @@ static inline void own_fpu(void)
         if (cpu_has_fpu) {
                 __enable_fpu();
                 KSTK_STATUS(current) |= ST0_CU1;
-                set_thread_flag(TIF_USEDFPU); 
+                set_thread_flag(TIF_USEDFPU);
         }
 }
 
@@ -98,7 +98,7 @@ static inline void lose_fpu(void)
 {
         if (cpu_has_fpu) {
                 KSTK_STATUS(current) &= ~ST0_CU1;
-                clear_thread_flag(TIF_USEDFPU); 
+                clear_thread_flag(TIF_USEDFPU);
                 __disable_fpu();
         }
 }
@@ -127,7 +127,7 @@ static inline void restore_fp(struct task_struct *tsk)
 static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
 {
         if (cpu_has_fpu) {
-                if ((tsk == current) && is_fpu_owner()) 
+                if ((tsk == current) && is_fpu_owner())
                         _save_fp(current);
                 return tsk->thread.fpu.hard.fpr;
         }
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
new file mode 100644
index 000000000000..9feff4ce1424
--- /dev/null
+++ b/include/asm-mips/futex.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#ifdef __KERNEL__
+
+#include <linux/futex.h>
+#include <asm/errno.h>
+#include <asm/uaccess.h>
+
+static inline int
+futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
+{
+        int op = (encoded_op >> 28) & 7;
+        int cmp = (encoded_op >> 24) & 15;
+        int oparg = (encoded_op << 8) >> 20;
+        int cmparg = (encoded_op << 20) >> 20;
+        int oldval = 0, ret;
+        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+                oparg = 1 << oparg;
+
+        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        inc_preempt_count();
+
+        switch (op) {
+        case FUTEX_OP_SET:
+        case FUTEX_OP_ADD:
+        case FUTEX_OP_OR:
+        case FUTEX_OP_ANDN:
+        case FUTEX_OP_XOR:
+        default:
+                ret = -ENOSYS;
+        }
+
+        dec_preempt_count();
+
+        if (!ret) {
+                switch (cmp) {
+                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+                default: ret = -ENOSYS;
+                }
+        }
+        return ret;
+}
+
+#endif
+#endif
diff --git a/include/asm-mips/hdreg.h b/include/asm-mips/hdreg.h
deleted file mode 100644
index 5989bbc97cbf..000000000000
--- a/include/asm-mips/hdreg.h
+++ /dev/null
@@ -1 +0,0 @@
-#warning this file is obsolete, please do not use it
diff --git a/include/asm-mips/hp-lj/asic.h b/include/asm-mips/hp-lj/asic.h
deleted file mode 100644
index fc2ca656da00..000000000000
--- a/include/asm-mips/hp-lj/asic.h
+++ /dev/null
@@ -1,7 +0,0 @@
-
-typedef enum { IllegalAsic, UnknownAsic, AndrosAsic, HarmonyAsic } AsicId;
-
-AsicId GetAsicId(void);
-
-const char* const GetAsicName(void);
-
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
index 2b7b0fdeac19..432011b16c26 100644
--- a/include/asm-mips/ip32/mace.h
+++ b/include/asm-mips/ip32/mace.h
@@ -94,7 +94,7 @@ struct mace_video {
         unsigned long xxx;      /* later... */
 };
 
-/* 
+/*
  * Ethernet interface
  */
 struct mace_ethernet {
@@ -129,7 +129,7 @@ struct mace_ethernet {
         volatile unsigned long rx_fifo;
 };
 
-/* 
+/*
  * Peripherals
  */
 
@@ -251,7 +251,7 @@ struct mace_timers {
         timer_reg audio_out2;
         timer_reg video_in1;
         timer_reg video_in2;
-        timer_reg video_out;    
+        timer_reg video_out;
 };
 
 struct mace_perif {
@@ -272,7 +272,7 @@ struct mace_perif {
 };
 
 
-/* 
+/*
  * ISA peripherals
  */
 
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
index 21d0fb7cee64..9e88c7669c7a 100644
--- a/include/asm-mips/lasat/serial.h
+++ b/include/asm-mips/lasat/serial.h
@@ -1,13 +1,13 @@
 #include <asm/lasat/lasat.h>
 
 /* Lasat 100 boards serial configuration */
-#define LASAT_BASE_BAUD_100             ( 7372800 / 16 ) 
+#define LASAT_BASE_BAUD_100             ( 7372800 / 16 )
 #define LASAT_UART_REGS_BASE_100        0x1c8b0000
 #define LASAT_UART_REGS_SHIFT_100       2
 #define LASATINT_UART_100               8
 
 /* * LASAT 200 boards serial configuration */
-#define LASAT_BASE_BAUD_200             (100000000 / 16 / 12) 
+#define LASAT_BASE_BAUD_200             (100000000 / 16 / 12)
 #define LASAT_UART_REGS_BASE_200        (Vrc5074_PHYS_BASE + 0x0300)
 #define LASAT_UART_REGS_SHIFT_200       3
 #define LASATINT_UART_200               13
diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h
index 7eb6bf661b80..c38844f615fc 100644
--- a/include/asm-mips/local.h
+++ b/include/asm-mips/local.h
@@ -5,7 +5,7 @@
 #include <linux/percpu.h>
 #include <asm/atomic.h>
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 typedef atomic_t local_t;
 
@@ -20,7 +20,7 @@ typedef atomic_t local_t;
 
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 typedef atomic64_t local_t;
 
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 2b36ea346910..148bae2fa7d3 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -1383,7 +1383,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define PCI_IO_START    0
 #define PCI_IO_END      0
 #define PCI_MEM_START   0
-#define PCI_MEM_END     0 
+#define PCI_MEM_END     0
 #define PCI_FIRST_DEVFN 0
 #define PCI_LAST_DEVFN  0
 #endif
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
index 4691398a414f..efafe65258b6 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -23,7 +23,7 @@
  *
  * ########################################################################
  *
- * 
+ *
  */
 #ifndef __ASM_DB1X00_H
 #define __ASM_DB1X00_H
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h
index 63c0a81c7832..5a2c1efb4eb7 100644
--- a/include/asm-mips/mach-generic/spaces.h
+++ b/include/asm-mips/mach-generic/spaces.h
@@ -12,7 +12,7 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define CAC_BASE                0x80000000
 #define IO_BASE                 0xa0000000
@@ -32,9 +32,9 @@
 #define HIGHMEM_START           0x20000000UL
 #endif
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 /*
  * This handles the memory map.
@@ -67,6 +67,6 @@
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
 #define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 #endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h
index 30d42fcafe3d..e96166f27c49 100644
--- a/include/asm-mips/mach-ip22/spaces.h
+++ b/include/asm-mips/mach-ip22/spaces.h
@@ -12,7 +12,7 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define CAC_BASE                0x80000000
 #define IO_BASE                 0xa0000000
@@ -32,9 +32,9 @@
 #define HIGHMEM_START           0x20000000UL
 #endif
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #define PAGE_OFFSET             0xffffffff80000000UL
 
 #ifndef HIGHMEM_START
@@ -50,6 +50,6 @@
 #define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
 #define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 #endif /* __ASM_MACH_IP22_SPACES_H */
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
index b932237f2193..04713973c6c3 100644
--- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
@@ -18,7 +18,7 @@
  * so, for 64bit IP32 kernel we just don't use ll/sc.
  * This does not affect luserland.
  */
-#if defined(CONFIG_CPU_R5000) && defined(CONFIG_MIPS64)
+#if defined(CONFIG_CPU_R5000) && defined(CONFIG_64BIT)
 #define cpu_has_llsc            0
 #else
 #define cpu_has_llsc            1
diff --git a/include/asm-mips/mach-jazz/floppy.h b/include/asm-mips/mach-jazz/floppy.h
index 8cf0d042c864..c9dad99b1232 100644
--- a/include/asm-mips/mach-jazz/floppy.h
+++ b/include/asm-mips/mach-jazz/floppy.h
@@ -92,7 +92,7 @@ static inline int fd_request_irq(void)
         return request_irq(FLOPPY_IRQ, floppy_interrupt,
                            SA_INTERRUPT | SA_SAMPLE_RANDOM, "floppy", NULL);
 }
-                                                                                
+
 static inline void fd_free_irq(void)
 {
         free_irq(FLOPPY_IRQ, NULL);
diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h
index d6c779747b3c..ff6d40c87a25 100644
--- a/include/asm-mips/mach-pb1x00/pb1500.h
+++ b/include/asm-mips/mach-pb1x00/pb1500.h
@@ -33,11 +33,11 @@
 #define PCI_BOARD_REG             0xAE000010
 #define PCMCIA_BOARD_REG          0xAE000010
   #define PC_DEASSERT_RST               0x80
-  #define PC_DRV_EN                     0x10 
+  #define PC_DRV_EN                     0x10
 #define PB1500_G_CONTROL          0xAE000014
 #define PB1500_RST_VDDI           0xAE00001C
 #define PB1500_LEDS               0xAE000018
-  
+
 #define PB1500_HEX_LED            0xAF000004
 #define PB1500_HEX_LED_BLANK      0xAF000008
 
diff --git a/include/asm-mips/mach-qemu/cpu-feature-overrides.h b/include/asm-mips/mach-qemu/cpu-feature-overrides.h
new file mode 100644
index 000000000000..f4e370e27168
--- /dev/null
+++ b/include/asm-mips/mach-qemu/cpu-feature-overrides.h
@@ -0,0 +1,31 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ */
+#ifndef __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * QEMU only comes with a hazard-free MIPS32 processor, so things are easy.
+ */
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_prefetch        0
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
+#define cpu_has_ic_fills_f_dc   0
+
+#define cpu_has_dsp             0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          0
+
+#endif /* __ASM_MACH_QEMU_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-qemu/param.h b/include/asm-mips/mach-qemu/param.h
new file mode 100644
index 000000000000..cb30ee490ae6
--- /dev/null
+++ b/include/asm-mips/mach-qemu/param.h
@@ -0,0 +1,13 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 by Ralf Baechle
+ */
+#ifndef __ASM_MACH_QEMU_PARAM_H
+#define __ASM_MACH_QEMU_PARAM_H
+
+#define HZ              100             /* Internal kernel timer frequency */
+
+#endif /* __ASM_MACH_QEMU_PARAM_H */
diff --git a/include/asm-mips/mach-vr41xx/timex.h b/include/asm-mips/mach-vr41xx/timex.h
deleted file mode 100644
index 8d71485d003a..000000000000
--- a/include/asm-mips/mach-vr41xx/timex.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 by Ralf Baechle
- */
-/*
- * Changes:
- *  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
- *  - CLOCK_TICK_RATE is changed into 32768 from 6144000.
- */
-#ifndef __ASM_MACH_VR41XX_TIMEX_H
-#define __ASM_MACH_VR41XX_TIMEX_H
-
-#define CLOCK_TICK_RATE         32768
-
-#endif /* __ASM_MACH_VR41XX_TIMEX_H */
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
index 48b77c9fb4f2..45cd72d172e8 100644
--- a/include/asm-mips/mmu_context.h
+++ b/include/asm-mips/mmu_context.h
@@ -28,17 +28,17 @@ extern unsigned long pgd_current[];
 #define TLBMISS_HANDLER_SETUP_PGD(pgd) \
         pgd_current[smp_processor_id()] = (unsigned long)(pgd)
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define TLBMISS_HANDLER_SETUP()                                         \
         write_c0_context((unsigned long) smp_processor_id() << 23);     \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
-#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
 #define TLBMISS_HANDLER_SETUP()                                         \
         write_c0_context((unsigned long) &pgd_current[smp_processor_id()] << 23); \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
 #endif
-#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
 #define TLBMISS_HANDLER_SETUP()                                         \
         write_c0_context((unsigned long) smp_processor_id() << 23);     \
         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
index 90ee24aad955..0be58b2aeb9f 100644
--- a/include/asm-mips/module.h
+++ b/include/asm-mips/module.h
@@ -25,7 +25,7 @@ typedef struct
   Elf64_Sxword r_addend;                /* Addend.  */
 } Elf64_Mips_Rela;
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define Elf_Shdr        Elf32_Shdr
 #define Elf_Sym         Elf32_Sym
@@ -33,7 +33,7 @@ typedef struct
 
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define Elf_Shdr        Elf64_Shdr
 #define Elf_Sym         Elf64_Sym
diff --git a/include/asm-mips/msgbuf.h b/include/asm-mips/msgbuf.h
index 513b2824838b..a1533959742e 100644
--- a/include/asm-mips/msgbuf.h
+++ b/include/asm-mips/msgbuf.h
@@ -15,25 +15,25 @@
 
 struct msqid64_ds {
         struct ipc64_perm msg_perm;
-#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused1;
 #endif
         __kernel_time_t msg_stime;      /* last msgsnd time */
-#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused1;
 #endif
-#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused2;
 #endif
         __kernel_time_t msg_rtime;      /* last msgrcv time */
-#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused2;
 #endif
-#if defined(CONFIG_MIPS32) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused3;
 #endif
         __kernel_time_t msg_ctime;      /* last change time */
-#if defined(CONFIG_MIPS32) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
         unsigned long   __unused3;
 #endif
         unsigned long  msg_cbytes;      /* current number of bytes on queue */
diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h
index 36cec9e31696..309bc3099f68 100644
--- a/include/asm-mips/paccess.h
+++ b/include/asm-mips/paccess.h
@@ -16,10 +16,10 @@
 #include <linux/config.h>
 #include <linux/errno.h>
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define __PA_ADDR       ".word"
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #define __PA_ADDR       ".dword"
 #endif
 
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 5cae35cd9ba9..652b6d67a571 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -103,20 +103,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
 #define __pgd(x)        ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
 
-/* Pure 2^n version of get_order */
-static __inline__ int get_order(unsigned long size)
-{
-        int order;
-
-        size = (size-1) >> (PAGE_SHIFT-1);
-        order = -1;
-        do {
-                size >>= 1;
-                order++;
-        } while (size);
-        return order;
-}
-
 #endif /* !__ASSEMBLY__ */
 
 /* to align the pointer to the (next) page boundary */
@@ -148,4 +134,6 @@ static __inline__ int get_order(unsigned long size)
 #define WANT_PAGE_VIRTUAL
 #endif
 
+#include <asm-generic/page.h>
+
 #endif /* _ASM_PAGE_H */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index d70dc355c1f3..c9a00ca1c012 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -94,7 +94,7 @@ struct pci_dev;
  */
 extern unsigned int PCI_DMA_BUS_IS_PHYS;
 
-#ifdef CONFIG_MAPPED_DMA_IO
+#ifdef CONFIG_DMA_NEED_PCI_MAP_STATE
 
 /* pci_unmap_{single,page} is not a nop, thus... */
 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       dma_addr_t ADDR_NAME;
@@ -104,7 +104,7 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS;
 #define pci_unmap_len(PTR, LEN_NAME)            ((PTR)->LEN_NAME)
 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   (((PTR)->LEN_NAME) = (VAL))
 
-#else /* CONFIG_MAPPED_DMA_IO  */
+#else /* CONFIG_DMA_NEED_PCI_MAP_STATE  */
 
 /* pci_unmap_{page,single} is a nop so... */
 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
@@ -114,7 +114,7 @@ extern unsigned int PCI_DMA_BUS_IS_PHYS;
 #define pci_unmap_len(PTR, LEN_NAME)            (0)
 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
 
-#endif /* CONFIG_MAPPED_DMA_IO  */
+#endif /* CONFIG_DMA_NEED_PCI_MAP_STATE  */
 
 /* This is always fine. */
 #define pci_dac_dma_supported(pci_dev, mask)    (1)
@@ -142,6 +142,8 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 
 extern void pcibios_resource_to_bus(struct pci_dev *dev,
         struct pci_bus_region *region, struct resource *res);
+extern void pcibios_bus_to_resource(struct pci_dev *dev,
+        struct resource *res, struct pci_bus_region *region);
 
 #ifdef CONFIG_PCI_DOMAINS
 
@@ -167,4 +169,17 @@ static inline void pcibios_add_platform_entries(struct pci_dev *dev)
 /* Do platform specific device initialization at pci_enable_device() time */
 extern int pcibios_plat_dev_init(struct pci_dev *dev);
 
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+        struct resource *root = NULL;
+
+        if (res->flags & IORESOURCE_IO)
+                root = &ioport_resource;
+        if (res->flags & IORESOURCE_MEM)
+                root = &iomem_resource;
+
+        return root;
+}
+
 #endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h
index 2d63f5ba403f..ce57288d43bd 100644
--- a/include/asm-mips/pgalloc.h
+++ b/include/asm-mips/pgalloc.h
@@ -85,7 +85,7 @@ static inline void pte_free(struct page *pte)
 
 #define __pte_free_tlb(tlb,pte)         tlb_remove_page((tlb),(pte))
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define pgd_populate(mm, pmd, pte)      BUG()
 
 /*
@@ -97,7 +97,7 @@ static inline void pte_free(struct page *pte)
 #define __pmd_free_tlb(tlb,x)           do { } while (0)
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define pgd_populate(mm, pgd, pmd)      set_pgd(pgd, __pgd(pmd))
 
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index e76ccd6e3a5d..dbe13da0bdad 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -11,10 +11,10 @@
 #include <asm-generic/4level-fixup.h>
 
 #include <linux/config.h>
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #include <asm/pgtable-32.h>
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #include <asm/pgtable-64.h>
 #endif
 
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index 13c54d5b3b48..d6466aa09fb7 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -33,7 +33,7 @@ extern void (*cpu_wait)(void);
 
 extern unsigned int vced_count, vcei_count;
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 /*
  * User space process size: 2GB. This is hardcoded into a few places,
  * so don't change it unless you know what you are doing.
@@ -47,7 +47,7 @@ extern unsigned int vced_count, vcei_count;
 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
 #endif
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 /*
  * User space process size: 1TB. This is hardcoded into a few places,
  * so don't change it unless you know what you are doing.  TASK_SIZE
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index d3c46d633826..2b5c624c3d4f 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -28,7 +28,7 @@
  * system call/exception. As usual the registers k0/k1 aren't being saved.
  */
 struct pt_regs {
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
         /* Pad bytes for argument save space on the stack. */
         unsigned long pad0[6];
 #endif
diff --git a/include/asm-mips/qemu.h b/include/asm-mips/qemu.h
new file mode 100644
index 000000000000..905c39585903
--- /dev/null
+++ b/include/asm-mips/qemu.h
@@ -0,0 +1,24 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2005 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_QEMU_H
+#define __ASM_QEMU_H
+
+/*
+ * Interrupt numbers
+ */
+#define Q_PIC_IRQ_BASE          0
+#define Q_COUNT_COMPARE_IRQ     16
+
+/*
+ * Qemu clock rate.  Unlike on real MIPS this has no relation to the
+ * instruction issue rate, so the choosen value is pure fiction, just needs
+ * to match the value in Qemu itself.
+ */
+#define QEMU_C0_COUNTER_CLOCK   100000000
+
+#endif /* __ASM_QEMU_H */
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index da03a32c1ca7..5bea49feec66 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -171,11 +171,11 @@ static inline void blast_dcache16(void)
         unsigned long start = INDEX_BASE;
         unsigned long end = start + current_cpu_data.dcache.waysize;
         unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-        unsigned long ws_end = current_cpu_data.dcache.ways << 
+        unsigned long ws_end = current_cpu_data.dcache.ways <<
                                current_cpu_data.dcache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
@@ -200,8 +200,8 @@ static inline void blast_dcache16_page_indexed(unsigned long page)
                                current_cpu_data.dcache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x200) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
 
@@ -214,8 +214,8 @@ static inline void blast_icache16(void)
                                current_cpu_data.icache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x200) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -239,8 +239,8 @@ static inline void blast_icache16_page_indexed(unsigned long page)
                                current_cpu_data.icache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x200) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -249,11 +249,11 @@ static inline void blast_scache16(void)
         unsigned long start = INDEX_BASE;
         unsigned long end = start + current_cpu_data.scache.waysize;
         unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-        unsigned long ws_end = current_cpu_data.scache.ways << 
+        unsigned long ws_end = current_cpu_data.scache.ways <<
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -278,8 +278,8 @@ static inline void blast_scache16_page_indexed(unsigned long page)
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x200) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x200)
                         cache16_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
@@ -318,8 +318,8 @@ static inline void blast_dcache32(void)
                                current_cpu_data.dcache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x400) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
 
@@ -343,8 +343,8 @@ static inline void blast_dcache32_page_indexed(unsigned long page)
                                current_cpu_data.dcache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x400) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
 }
 
@@ -357,8 +357,8 @@ static inline void blast_icache32(void)
                                current_cpu_data.icache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x400) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -383,7 +383,7 @@ static inline void blast_icache32_page_indexed(unsigned long page)
         unsigned long ws, addr;
 
         for (ws = 0; ws < ws_end; ws += ws_inc)
-                for (addr = start; addr < end; addr += 0x400) 
+                for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -392,11 +392,11 @@ static inline void blast_scache32(void)
         unsigned long start = INDEX_BASE;
         unsigned long end = start + current_cpu_data.scache.waysize;
         unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-        unsigned long ws_end = current_cpu_data.scache.ways << 
+        unsigned long ws_end = current_cpu_data.scache.ways <<
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -421,8 +421,8 @@ static inline void blast_scache32_page_indexed(unsigned long page)
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x400) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x400)
                         cache32_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
@@ -461,8 +461,8 @@ static inline void blast_icache64(void)
                                current_cpu_data.icache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x800) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x800)
                         cache64_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -487,7 +487,7 @@ static inline void blast_icache64_page_indexed(unsigned long page)
         unsigned long ws, addr;
 
         for (ws = 0; ws < ws_end; ws += ws_inc)
-                for (addr = start; addr < end; addr += 0x800) 
+                for (addr = start; addr < end; addr += 0x800)
                         cache64_unroll32(addr|ws,Index_Invalidate_I);
 }
 
@@ -496,11 +496,11 @@ static inline void blast_scache64(void)
         unsigned long start = INDEX_BASE;
         unsigned long end = start + current_cpu_data.scache.waysize;
         unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-        unsigned long ws_end = current_cpu_data.scache.ways << 
+        unsigned long ws_end = current_cpu_data.scache.ways <<
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x800)
                         cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -525,8 +525,8 @@ static inline void blast_scache64_page_indexed(unsigned long page)
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x800) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x800)
                         cache64_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
@@ -561,11 +561,11 @@ static inline void blast_scache128(void)
         unsigned long start = INDEX_BASE;
         unsigned long end = start + current_cpu_data.scache.waysize;
         unsigned long ws_inc = 1UL << current_cpu_data.scache.waybit;
-        unsigned long ws_end = current_cpu_data.scache.ways << 
+        unsigned long ws_end = current_cpu_data.scache.ways <<
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
                 for (addr = start; addr < end; addr += 0x1000)
                         cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
@@ -590,8 +590,8 @@ static inline void blast_scache128_page_indexed(unsigned long page)
                                current_cpu_data.scache.waybit;
         unsigned long ws, addr;
 
-        for (ws = 0; ws < ws_end; ws += ws_inc) 
-                for (addr = start; addr < end; addr += 0x1000) 
+        for (ws = 0; ws < ws_end; ws += ws_inc)
+                for (addr = start; addr < end; addr += 0x1000)
                         cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
 }
 
diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h
index 7b33bbca9585..6173004cc88e 100644
--- a/include/asm-mips/reg.h
+++ b/include/asm-mips/reg.h
@@ -14,7 +14,7 @@
 
 #include <linux/config.h>
 
-#if defined(CONFIG_MIPS32) || defined(WANT_COMPAT_REG_H)
+#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
 
 #define EF_R0                   6
 #define EF_R1                   7
@@ -70,7 +70,7 @@
 
 #endif
 
-#if CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define EF_R0                    0
 #define EF_R1                    1
@@ -124,6 +124,6 @@
 
 #define EF_SIZE                 304     /* size in bytes */
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 #endif /* __ASM_MIPS_REG_H */
diff --git a/include/asm-mips/resource.h b/include/asm-mips/resource.h
index fd3c6d17a5f6..1fba00c22077 100644
--- a/include/asm-mips/resource.h
+++ b/include/asm-mips/resource.h
@@ -27,7 +27,7 @@
  * but we keep the old value on MIPS32,
  * for compatibility:
  */
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 # define RLIM_INFINITY          0x7fffffffUL
 #endif
 
diff --git a/include/asm-mips/rtc.h b/include/asm-mips/rtc.h
index 31c0c2347f4f..3c4b637fd925 100644
--- a/include/asm-mips/rtc.h
+++ b/include/asm-mips/rtc.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-mips/rtc.h 
+ * include/asm-mips/rtc.h
  *
  * (Really an interface for drivers/char/genrtc.c)
  *
diff --git a/include/asm-mips/sgi/gio.h b/include/asm-mips/sgi/gio.h
index a38d66f99872..889cf028c95d 100644
--- a/include/asm-mips/sgi/gio.h
+++ b/include/asm-mips/sgi/gio.h
@@ -16,7 +16,7 @@
  *
  * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
  * three physical connectors, but only two slots, GFX and EXP0.
- * 
+ *
  * There is 10MB of GIO address space for GIO64 slot devices
  * slot#   slot type address range            size
  * -----   --------- ----------------------- -----
diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h
index a5b988d7327a..ac3dfc7af5b0 100644
--- a/include/asm-mips/sgi/hpc3.h
+++ b/include/asm-mips/sgi/hpc3.h
@@ -221,7 +221,7 @@ struct hpc3_regs {
 #define HPC3_BESTAT_PIDMASK     0x3f700 /* DMA channel parity identifier */
 
         u32 _unused1[0x14000/4 - 5];    /* padding */
-        
+
         /* Now direct PIO per-HPC3 peripheral access to external regs. */
         volatile u32 scsi0_ext[256];    /* SCSI channel 0 external regs */
         u32 _unused2[0x7c00/4];
@@ -304,7 +304,7 @@ struct hpc3_regs {
         volatile u32 bbram[8192-50-14]; /* Battery backed ram */
 };
 
-/* 
+/*
  * It is possible to have two HPC3's within the address space on
  * one machine, though only having one is more likely on an Indy.
  */
diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h
index 169187f53fbc..f3e3dc9bb732 100644
--- a/include/asm-mips/sgi/ioc.h
+++ b/include/asm-mips/sgi/ioc.h
@@ -16,7 +16,7 @@
 #include <linux/types.h>
 #include <asm/sgi/pi1.h>
 
-/* 
+/*
  * All registers are 8-bit wide alligned on 32-bit boundary. Bad things
  * happen if you try word access them. You have been warned.
  */
@@ -138,7 +138,7 @@ struct sgioc_regs {
         u8 _sysid[3];
         volatile u8 sysid;
 #define SGIOC_SYSID_FULLHOUSE   0x01
-#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5) 
+#define SGIOC_SYSID_BOARDREV(x) ((x & 0xe0) > 5)
 #define SGIOC_SYSID_CHIPREV(x)  ((x & 0x1e) > 1)
         u32 _unused2;
         u8 _read[3];
diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h
index 97d73adb4e40..bbfc05c3cab9 100644
--- a/include/asm-mips/sgi/ip22.h
+++ b/include/asm-mips/sgi/ip22.h
@@ -12,7 +12,7 @@
 #ifndef _SGI_IP22_H
 #define _SGI_IP22_H
 
-/* 
+/*
  * These are the virtual IRQ numbers, we divide all IRQ's into
  * 'spaces', the 'space' determines where and how to enable/disable
  * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrups
diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h
index fd98f930607c..c52f7834c7c8 100644
--- a/include/asm-mips/sgi/mc.h
+++ b/include/asm-mips/sgi/mc.h
@@ -182,14 +182,14 @@ struct sgimc_regs {
         volatile u32 dtlb_hi3;
         u32 _unused33;
         volatile u32 dtlb_lo3;
-        
+
         u32 _unused34[0x0392];
-        
+
         u32 _unused35;
         volatile u32 rpsscounter;       /* Chirps at 100ns */
 
         u32 _unused36[0x1000/4-2*4];
-        
+
         u32 _unused37;
         volatile u32 maddronly;         /* Address DMA goes at */
         u32 _unused38;
diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h
index 59450335f049..722b77a8c5e5 100644
--- a/include/asm-mips/sgiarcs.h
+++ b/include/asm-mips/sgiarcs.h
@@ -367,7 +367,7 @@ struct linux_smonblock {
  * Macros for calling a 32-bit ARC implementation from 64-bit code
  */
 
-#if defined(CONFIG_MIPS64) && defined(CONFIG_ARC32)
+#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32)
 
 #define __arc_clobbers                                                  \
         "$2","$3" /* ... */, "$8","$9","$10","$11",                     \
@@ -476,10 +476,10 @@ struct linux_smonblock {
         __res;                                                          \
 })
 
-#endif /* defined(CONFIG_MIPS64) && defined(CONFIG_ARC32) */
+#endif /* defined(CONFIG_64BIT) && defined(CONFIG_ARC32) */
 
-#if (defined(CONFIG_MIPS32) && defined(CONFIG_ARC32)) ||                \
-    (defined(CONFIG_MIPS64) && defined(CONFIG_ARC64))
+#if (defined(CONFIG_32BIT) && defined(CONFIG_ARC32)) ||         \
+    (defined(CONFIG_64BIT) && defined(CONFIG_ARC64))
 
 #define ARC_CALL0(dest)                                                 \
 ({      long __res;                                                     \
diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h
index 7ac5da13ce8a..b5e7dae19f0f 100644
--- a/include/asm-mips/sibyte/carmel.h
+++ b/include/asm-mips/sibyte/carmel.h
@@ -25,12 +25,12 @@
 
 #define SIBYTE_BOARD_NAME "Carmel"
 
-#define GPIO_PHY_INTERRUPT      2 
-#define GPIO_NONMASKABLE_INT    3 
-#define GPIO_CF_INSERTED        6 
-#define GPIO_MONTEREY_RESET     7 
-#define GPIO_QUADUART_INT       8 
-#define GPIO_CF_INT             9 
+#define GPIO_PHY_INTERRUPT      2
+#define GPIO_NONMASKABLE_INT    3
+#define GPIO_CF_INSERTED        6
+#define GPIO_MONTEREY_RESET     7
+#define GPIO_QUADUART_INT       8
+#define GPIO_CF_INT             9
 #define GPIO_FPGA_CCLK          10
 #define GPIO_FPGA_DOUT          11
 #define GPIO_FPGA_DIN           12
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
index 96088fb074a4..40ef97c76c8b 100644
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
-    *  Global constants and macros              File: sb1250_defs.h     
-    *  
+    *
+    *  Global constants and macros              File: sb1250_defs.h
+    *
     *  This file contains macros and definitions used by the other
     *  include files.
     *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -105,7 +105,7 @@
 #define SIBYTE_HDR_FMASK_112x_ALL               0x0000f00
 #define SIBYTE_HDR_FMASK_112x_PASS1             0x0000100
 
-/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */ 
+/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */
 #define SIBYTE_HDR_FMASK(chip, pass)                                    \
     (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
 #define SIBYTE_HDR_FMASK_ALLREVS(chip)                                  \
@@ -150,31 +150,31 @@
 
 /*  *********************************************************************
     *  Naming schemes for constants in these files:
-    *  
-    *  M_xxx           MASK constant (identifies bits in a register). 
+    *
+    *  M_xxx           MASK constant (identifies bits in a register).
     *                  For multi-bit fields, all bits in the field will
     *                  be set.
     *
     *  K_xxx           "Code" constant (value for data in a multi-bit
     *                  field).  The value is right justified.
     *
-    *  V_xxx           "Value" constant.  This is the same as the 
+    *  V_xxx           "Value" constant.  This is the same as the
     *                  corresponding "K_xxx" constant, except it is
     *                  shifted to the correct position in the register.
     *
     *  S_xxx           SHIFT constant.  This is the number of bits that
-    *                  a field value (code) needs to be shifted 
+    *                  a field value (code) needs to be shifted
     *                  (towards the left) to put the value in the right
     *                  position for the register.
     *
-    *  A_xxx           ADDRESS constant.  This will be a physical 
+    *  A_xxx           ADDRESS constant.  This will be a physical
     *                  address.  Use the PHYS_TO_K1 macro to generate
     *                  a K1SEG address.
     *
     *  R_xxx           RELATIVE offset constant.  This is an offset from
     *                  an A_xxx constant (usually the first register in
     *                  a group).
-    *  
+    *
     *  G_xxx(X)        GET value.  This macro obtains a multi-bit field
     *                  from a register, masks it, and shifts it to
     *                  the bottom of the register (retrieving a K_xxx
@@ -189,7 +189,7 @@
 
 
 /*
- * Cast to 64-bit number.  Presumably the syntax is different in 
+ * Cast to 64-bit number.  Presumably the syntax is different in
  * assembly language.
  *
  * Note: you'll need to define uint32_t and uint64_t in your headers.
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
index f1b08d32338d..3cdb48f50ed0 100644
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -1,24 +1,24 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  DMA definitions                          File: sb1250_dma.h
-    *  
+    *
     *  This module contains constants and macros useful for
     *  programming the SB1250's DMA controllers, both the data mover
     *  and the Ethernet DMA.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -28,7 +28,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -43,9 +43,9 @@
     *  DMA Registers
     ********************************************************************* */
 
-/* 
+/*
  * Ethernet and Serial DMA Configuration Register 0  (Table 7-4)
- * Registers: DMA_CONFIG0_MAC_x_RX_CH_0 
+ * Registers: DMA_CONFIG0_MAC_x_RX_CH_0
  * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
  * Registers: DMA_CONFIG0_SER_x_RX
  * Registers: DMA_CONFIG0_SER_x_TX
@@ -98,7 +98,7 @@
 
 /*
  * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
- * Registers: DMA_CONFIG1_MAC_x_RX_CH_0 
+ * Registers: DMA_CONFIG1_MAC_x_RX_CH_0
  * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
  * Registers: DMA_CONFIG1_SER_x_RX
  * Registers: DMA_CONFIG1_SER_x_TX
@@ -152,11 +152,11 @@
 /*
  * DMA Descriptor Count Registers (Table 7-8)
  */
- 
+
 /* No bitfields */
 
 
-/* 
+/*
  * Current Descriptor Address Register (Table 7-11)
  */
 
@@ -275,14 +275,14 @@
 #define V_DMA_DSCRB_STATUS(x)       _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS)
 #define G_DMA_DSCRB_STATUS(x)       _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS)
 
-/* 
+/*
  * Ethernet Descriptor Status Bits (Table 7-15)
  */
 
 #define M_DMA_ETHRX_BADIP4CS        _SB_MAKEMASK1(51)
 #define M_DMA_ETHRX_DSCRERR         _SB_MAKEMASK1(52)
 
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 
+#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 /* Note: BADTCPCS is actually in DSCR_B options field */
 #define M_DMA_ETHRX_BADTCPCS    _SB_MAKEMASK1(0)
 #endif /* 1250 PASS2 || 112x PASS1 */
@@ -324,7 +324,7 @@
 
 #define M_DMA_ETHTX_SOP             _SB_MAKEMASK1(63)
 
-/* 
+/*
  * Ethernet Transmit Options (Table 7-17)
  */
 
@@ -377,7 +377,7 @@
     *  Data Mover Registers
     ********************************************************************* */
 
-/* 
+/*
  * Data Mover Descriptor Base Address Register (Table 7-22)
  * Register: DM_DSCR_BASE_0
  * Register: DM_DSCR_BASE_1
@@ -414,7 +414,7 @@
 #define M_DM_DSCR_BASE_ABORT        _SB_MAKEMASK1(62)
 #define M_DM_DSCR_BASE_ENABL        _SB_MAKEMASK1(63)
 
-/* 
+/*
  * Data Mover Descriptor Count Register (Table 7-25)
  */
 
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h
index 0d9dfac3d7db..f1f509f295c4 100644
--- a/include/asm-mips/sibyte/sb1250_genbus.h
+++ b/include/asm-mips/sibyte/sb1250_genbus.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  Generic Bus Constants                     File: sb1250_genbus.h
-    *  
-    *  This module contains constants and macros useful for 
+    *
+    *  This module contains constants and macros useful for
     *  manipulating the SB1250's Generic Bus interface
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
index c3f74df211f4..e173e2ea4c98 100644
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  Interrupt Mapper definitions             File: sb1250_int.h
-    *  
+    *
     *  This module contains constants for manipulating the SB1250's
     *  interrupt mapper and definitions for the interrupt sources.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -43,7 +43,7 @@
 
 /*
  * Interrupt sources (Table 4-8, UM 0.2)
- * 
+ *
  * First, the interrupt numbers.
  */
 
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h
index 799db828d963..8afe8e01581b 100644
--- a/include/asm-mips/sibyte/sb1250_l2c.h
+++ b/include/asm-mips/sibyte/sb1250_l2c.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  L2 Cache constants and macros            File: sb1250_l2c.h
-    *  
+    *
     *  This module contains constants useful for manipulating the
     *  level 2 cache.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h
index d8753885df17..f2617ded0a8f 100644
--- a/include/asm-mips/sibyte/sb1250_ldt.h
+++ b/include/asm-mips/sibyte/sb1250_ldt.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  LDT constants                            File: sb1250_ldt.h
-    *  
-    *  This module contains constants and macros to describe 
-    *  the LDT interface on the SB1250.  
-    *  
+    *
+    *  This module contains constants and macros to describe
+    *  the LDT interface on the SB1250.
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -155,7 +155,7 @@
 
 /*
  * LDT Status Register (Table 8-14).  Note that these constants
- * assume you've read the command and status register 
+ * assume you've read the command and status register
  * together (32-bit read at offset 0x04)
  *
  * These bits also apply to the secondary status
@@ -183,8 +183,8 @@
 #define M_LDT_STATUS_DETPARERR          _SB_MAKEMASK1_32(31)
 
 /*
- * Bridge Control Register (Table 8-16).  Note that these 
- * constants assume you've read the register as a 32-bit 
+ * Bridge Control Register (Table 8-16).  Note that these
+ * constants assume you've read the register as a 32-bit
  * read (offset 0x3C)
  */
 
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
index 81f603f03a98..18e74e43f4a2 100644
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  MAC constants and macros                 File: sb1250_mac.h
-    *  
+    *
     *  This module contains constants and macros for the SB1250's
     *  ethernet controllers.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -311,7 +311,7 @@
 
 /*
  * These constants are used to configure the fields within the Frame
- * Configuration Register.  
+ * Configuration Register.
  */
 
 #define K_MAC_IFG_RX_10             _SB_MAKE64(0)       /* See table 176, not used */
@@ -393,7 +393,7 @@
  * Register: MAC_INT_MASK_2
  */
 
-/* 
+/*
  * Use these constants to shift the appropriate channel
  * into the CH0 position so the same tests can be used
  * on each channel.
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
index 93a48334b874..1dd41c927996 100644
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
-    *  Memory Controller constants              File: sb1250_mc.h       
-    *  
+    *
+    *  Memory Controller constants              File: sb1250_mc.h
+    *
     *  This module contains constants and macros useful for
     *  programming the memory controller.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -166,7 +166,7 @@
 
 #define K_MC_REF_RATE_100MHz         0x62
 #define K_MC_REF_RATE_133MHz         0x81
-#define K_MC_REF_RATE_200MHz         0xC4 
+#define K_MC_REF_RATE_200MHz         0xC4
 
 #define V_MC_REF_RATE_100MHz         V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
 #define V_MC_REF_RATE_133MHz         V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
@@ -228,7 +228,7 @@
                                      V_MC_ADDR_DRIVE_DEFAULT | \
                                      V_MC_DATA_DRIVE_DEFAULT | \
                                      V_MC_CLOCK_DRIVE_DEFAULT | \
-                                     V_MC_REF_RATE_DEFAULT 
+                                     V_MC_REF_RATE_DEFAULT
 
 
 
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
index 5d496c6faba6..9db80cd13a79 100644
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  Register Definitions                     File: sb1250_regs.h
-    *  
+    *
     *  This module contains the addresses of the on-chip peripherals
     *  on the SB1250.
-    *  
+    *
     *  SB1250 specification level:  01/02/2002
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -40,20 +40,20 @@
 
 /*  *********************************************************************
     *  Some general notes:
-    *  
+    *
     *  For the most part, when there is more than one peripheral
     *  of the same type on the SOC, the constants below will be
     *  offsets from the base of each peripheral.  For example,
     *  the MAC registers are described as offsets from the first
     *  MAC register, and there will be a MAC_REGISTER() macro
-    *  to calculate the base address of a given MAC.  
-    *  
+    *  to calculate the base address of a given MAC.
+    *
     *  The information in this file is based on the SB1250 SOC
     *  manual version 0.2, July 2000.
     ********************************************************************* */
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * Memory Controller Registers
     ********************************************************************* */
 
@@ -101,7 +101,7 @@
 #define R_MC_TEST_ECC               0x0000000420
 #define R_MC_MCLK_CFG               0x0000000500
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * L2 Cache Control Registers
     ********************************************************************* */
 
@@ -126,7 +126,7 @@
 #define A_L2_EEC_ADDRESS            A_L2_ECC_TAG
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * PCI Interface Registers
     ********************************************************************* */
 
@@ -134,7 +134,7 @@
 #define A_PCI_TYPE01_HEADER         0x00DE000800
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * Ethernet DMA and MACs
     ********************************************************************* */
 
@@ -184,7 +184,7 @@
             (R_MAC_DMA_CHANNEL_BASE(txrx,chan) +    \
             (reg))
 
-/* 
+/*
  * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
  */
 
@@ -259,7 +259,7 @@
 #define MAC_CHMAP_COUNT                 4
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * DUART Registers
     ********************************************************************* */
 
@@ -363,7 +363,7 @@
 #endif /* 1250 PASS2 || 112x PASS1 */
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * Synchronous Serial Registers
     ********************************************************************* */
 
@@ -397,7 +397,7 @@
             (reg))
 
 
-/* 
+/*
  * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
  */
 
@@ -457,7 +457,7 @@
 #define R_SER_RMON_RX_ERRORS        0x000001F0
 #define R_SER_RMON_RX_BADADDR       0x000001F8
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * Generic Bus Registers
     ********************************************************************* */
 
@@ -513,7 +513,7 @@
 #define R_IO_PCMCIA_CFG             0x0A60
 #define R_IO_PCMCIA_STATUS          0x0A70
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * GPIO Registers
     ********************************************************************* */
 
@@ -537,7 +537,7 @@
 #define R_GPIO_PIN_CLR              0x30
 #define R_GPIO_PIN_SET              0x38
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * SMBus Registers
     ********************************************************************* */
 
@@ -573,7 +573,7 @@
 #define R_SMB_CONTROL               0x0000000060
 #define R_SMB_PEC                   0x0000000070
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * Timer Registers
     ********************************************************************* */
 
@@ -641,7 +641,7 @@
 #endif /* 1250 PASS2 || 112x PASS1 */
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Control Registers
     ********************************************************************* */
 
@@ -649,7 +649,7 @@
 #define A_SCD_SYSTEM_CFG            0x0010020008
 #define A_SCD_SYSTEM_MANUF          0x0010038000
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Address Trap Registers
     ********************************************************************* */
 
@@ -672,7 +672,7 @@
 #endif /* 1250 PASS2 || 112x PASS1 */
 
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Interrupt Mapper Registers
     ********************************************************************* */
 
@@ -701,7 +701,7 @@
 #define R_IMR_INTERRUPT_MAP_BASE        0x0200
 #define R_IMR_INTERRUPT_MAP_COUNT       64
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Performance Counter Registers
     ********************************************************************* */
 
@@ -711,7 +711,7 @@
 #define A_SCD_PERF_CNT_2            0x00100204E0
 #define A_SCD_PERF_CNT_3            0x00100204E8
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Bus Watcher Registers
     ********************************************************************* */
 
@@ -726,13 +726,13 @@
 #define A_BUS_L2_ERRORS             0x00100208C0
 #define A_BUS_MEM_IO_ERRORS         0x00100208C8
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Debug Controller Registers
     ********************************************************************* */
 
 #define A_SCD_JTAG_BASE             0x0010000000
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Trace Buffer Registers
     ********************************************************************* */
 
@@ -755,7 +755,7 @@
 #define A_SCD_TRACE_SEQUENCE_6      0x0010020A90
 #define A_SCD_TRACE_SEQUENCE_7      0x0010020A98
 
-/*  ********************************************************************* 
+/*  *********************************************************************
     * System Generic DMA Registers
     ********************************************************************* */
 
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
index 22e8041959e2..dbbd682fb47e 100644
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  SCD Constants and Macros                 File: sb1250_scd.h
-    *  
+    *
     *  This module contains constants and macros useful for
     *  manipulating the System Control and Debug module on the 1250.
-    *  
+    *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -130,40 +130,40 @@
 /* System Manufacturing Register
 * Register: SCD_SYSTEM_MANUF
 */
- 
+
 /* Wafer ID: bits 31:0 */
 #define S_SYS_WAFERID1_200        _SB_MAKE64(0)
 #define M_SYS_WAFERID1_200        _SB_MAKEMASK(32,S_SYS_WAFERID1_200)
 #define V_SYS_WAFERID1_200(x)     _SB_MAKEVALUE(x,S_SYS_WAFERID1_200)
 #define G_SYS_WAFERID1_200(x)     _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200)
- 
+
 #define S_SYS_BIN                 _SB_MAKE64(32)
 #define M_SYS_BIN                 _SB_MAKEMASK(4,S_SYS_BIN)
 #define V_SYS_BIN                 _SB_MAKEVALUE(x,S_SYS_BIN)
 #define G_SYS_BIN                 _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
- 
+
 /* Wafer ID: bits 39:36 */
 #define S_SYS_WAFERID2_200        _SB_MAKE64(36)
 #define M_SYS_WAFERID2_200        _SB_MAKEMASK(4,S_SYS_WAFERID2_200)
 #define V_SYS_WAFERID2_200(x)     _SB_MAKEVALUE(x,S_SYS_WAFERID2_200)
 #define G_SYS_WAFERID2_200(x)     _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200)
- 
+
 /* Wafer ID: bits 39:0 */
 #define S_SYS_WAFERID_300         _SB_MAKE64(0)
 #define M_SYS_WAFERID_300         _SB_MAKEMASK(40,S_SYS_WAFERID_300)
 #define V_SYS_WAFERID_300(x)      _SB_MAKEVALUE(x,S_SYS_WAFERID_300)
 #define G_SYS_WAFERID_300(x)      _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300)
- 
+
 #define S_SYS_XPOS                _SB_MAKE64(40)
 #define M_SYS_XPOS                _SB_MAKEMASK(6,S_SYS_XPOS)
 #define V_SYS_XPOS(x)             _SB_MAKEVALUE(x,S_SYS_XPOS)
 #define G_SYS_XPOS(x)             _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS)
- 
+
 #define S_SYS_YPOS                _SB_MAKE64(46)
 #define M_SYS_YPOS                _SB_MAKEMASK(6,S_SYS_YPOS)
 #define V_SYS_YPOS(x)             _SB_MAKEVALUE(x,S_SYS_YPOS)
 #define G_SYS_YPOS(x)             _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
- 
+
 /*
  * System Config Register (Table 4-2)
  * Register: SCD_SYSTEM_CFG
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h
index 287cbfe9efa2..335c53e92936 100644
--- a/include/asm-mips/sibyte/sb1250_smbus.h
+++ b/include/asm-mips/sibyte/sb1250_smbus.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  SMBUS Constants                          File: sb1250_smbus.h
-    *  
-    *  This module contains constants and macros useful for 
+    *
+    *  This module contains constants and macros useful for
     *  manipulating the SB1250's SMbus devices.
-    *  
+    *
     *  SB1250 specification level:  01/02/2002
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h
index 8d5e8edd3c4b..fa2760d38b8b 100644
--- a/include/asm-mips/sibyte/sb1250_syncser.h
+++ b/include/asm-mips/sibyte/sb1250_syncser.h
@@ -7,17 +7,17 @@
     *  manipulating the SB1250's Synchronous Serial
     *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
     *
     *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h
index 7655d6945cca..923ea4f44e0f 100644
--- a/include/asm-mips/sibyte/sb1250_uart.h
+++ b/include/asm-mips/sibyte/sb1250_uart.h
@@ -1,23 +1,23 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
-    *  
+    *
     *  UART Constants                           File: sb1250_uart.h
-    *  
-    *  This module contains constants and macros useful for 
+    *
+    *  This module contains constants and macros useful for
     *  manipulating the SB1250's UARTs
     *
     *  SB1250 specification level:  User's manual 1/02/02
-    *  
+    *
     *  Author:  Mitch Lichtenberg
-    *  
-    *********************************************************************  
+    *
+    *********************************************************************
     *
     *  Copyright 2000,2001,2002,2003
     *  Broadcom Corporation. All rights reserved.
-    *  
-    *  This program is free software; you can redistribute it and/or 
-    *  modify it under the terms of the GNU General Public License as 
-    *  published by the Free Software Foundation; either version 2 of 
+    *
+    *  This program is free software; you can redistribute it and/or
+    *  modify it under the terms of the GNU General Public License as
+    *  published by the Free Software Foundation; either version 2 of
     *  the License, or (at your option) any later version.
     *
     *  This program is distributed in the hope that it will be useful,
@@ -27,7 +27,7 @@
     *
     *  You should have received a copy of the GNU General Public License
     *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, 
+    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     *  MA 02111-1307 USA
     ********************************************************************* */
 
@@ -37,7 +37,7 @@
 
 #include "sb1250_defs.h"
 
-/* ********************************************************************** 
+/* **********************************************************************
    * DUART Registers
    ********************************************************************** */
 
@@ -145,7 +145,7 @@
 #define V_DUART_MISC_CMD_START_BREAK     V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
 #define V_DUART_MISC_CMD_STOP_BREAK      V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
 
-#define M_DUART_CMD_RESERVED             _SB_MAKEMASK1(7) 
+#define M_DUART_CMD_RESERVED             _SB_MAKEMASK1(7)
 
 /*
  * DUART Status Register (Table 10-6)
@@ -165,7 +165,7 @@
 
 /*
  * DUART Baud Rate Register (Table 10-7)
- * Register: DUART_CLK_SEL_A 
+ * Register: DUART_CLK_SEL_A
  * Register: DUART_CLK_SEL_B
  */
 
@@ -332,7 +332,7 @@
     (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-/* 
+/*
  * Full Interrupt Control Register
  */
 
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h
index 18939e84b6f2..f7fbebaa0744 100644
--- a/include/asm-mips/sigcontext.h
+++ b/include/asm-mips/sigcontext.h
@@ -10,7 +10,7 @@
 #define _ASM_SIGCONTEXT_H
 
 #include <asm/sgidefs.h>
-                                                                                
+
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 /*
@@ -38,7 +38,7 @@ struct sigcontext {
 };
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-                                                                                
+
 #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
 
 /*
diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h
index a0e26e6c994d..698becab5a9e 100644
--- a/include/asm-mips/siginfo.h
+++ b/include/asm-mips/siginfo.h
@@ -25,10 +25,10 @@ struct siginfo;
 /*
  * Careful to keep union _sifields from shifting ...
  */
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
 #endif
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 #define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
 #endif
 
diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h
index 6333169be329..3ccfe09fa744 100644
--- a/include/asm-mips/sim.h
+++ b/include/asm-mips/sim.h
@@ -16,7 +16,7 @@
 #define __str2(x) #x
 #define __str(x) __str2(x)
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define save_static_function(symbol)                                    \
 __asm__ (                                                               \
@@ -42,9 +42,9 @@ __asm__ (								\
 
 #define nabi_no_regargs
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define save_static_function(symbol)                                    \
 __asm__ (                                                               \
@@ -78,6 +78,6 @@ __asm__ (								\
         unsigned long __dummy6,                                         \
         unsigned long __dummy7,
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 #endif /* _ASM_SIM_H */
diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h
index d478a86294ee..753b6620e6fa 100644
--- a/include/asm-mips/socket.h
+++ b/include/asm-mips/socket.h
@@ -82,7 +82,7 @@ To add: #define SO_REUSEPORT 0x0200	/* Allow local address and port reuse.  */
  * @SOCK_STREAM - stream (connection) socket
  * @SOCK_RAW - raw socket
  * @SOCK_RDM - reliably-delivered message
- * @SOCK_SEQPACKET - sequential packet socket 
+ * @SOCK_SEQPACKET - sequential packet socket
  * @SOCK_PACKET - linux specific way of getting packets at the dev level.
  *                For writing rarp and other similar things on the user level.
  */
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 86283c25fd5b..fb42f99f8527 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -26,7 +26,7 @@
 
                 .macro  SAVE_TEMP
                 mfhi    v1
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
                 LONG_S  $8, PT_R8(sp)
                 LONG_S  $9, PT_R9(sp)
 #endif
@@ -56,7 +56,7 @@
 
 #ifdef CONFIG_SMP
                 .macro  get_saved_sp    /* SMP variation */
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
                 mfc0    k0, CP0_CONTEXT
                 lui     k1, %hi(kernelsp)
                 srl     k0, k0, 23
@@ -64,7 +64,7 @@
                 addu    k1, k0
                 LONG_L  k1, %lo(kernelsp)(k1)
 #endif
-#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
                 MFC0    k1, CP0_CONTEXT
                 dsra    k1, 23
                 lui     k0, %hi(pgd_current)
@@ -74,7 +74,7 @@
                 daddu   k1, k0
                 LONG_L  k1, %lo(kernelsp)(k1)
 #endif
-#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
                 MFC0    k1, CP0_CONTEXT
                 dsrl    k1, 23
                 dsll    k1, k1, 3
@@ -83,20 +83,20 @@
                 .endm
 
                 .macro  set_saved_sp stackp temp temp2
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
                 mfc0    \temp, CP0_CONTEXT
                 srl     \temp, 23
                 sll     \temp, 2
                 LONG_S  \stackp, kernelsp(\temp)
 #endif
-#if defined(CONFIG_MIPS64) && !defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64)
                 lw      \temp, TI_CPU(gp)
                 dsll    \temp, 3
                 lui     \temp2, %hi(kernelsp)
                 daddu   \temp, \temp2
                 LONG_S  \stackp, %lo(kernelsp)(\temp)
 #endif
-#if defined(CONFIG_MIPS64) && defined(CONFIG_BUILD_ELF64)
+#if defined(CONFIG_64BIT) && defined(CONFIG_BUILD_ELF64)
                 lw      \temp, TI_CPU(gp)
                 dsll    \temp, 3
                 LONG_S  \stackp, kernelsp(\temp)
@@ -140,7 +140,7 @@
                 LONG_S  $6, PT_R6(sp)
                 MFC0    v1, CP0_EPC
                 LONG_S  $7, PT_R7(sp)
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                 LONG_S  $8, PT_R8(sp)
                 LONG_S  $9, PT_R9(sp)
 #endif
@@ -169,7 +169,7 @@
 
                 .macro  RESTORE_TEMP
                 LONG_L  $24, PT_LO(sp)
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
                 LONG_L  $8, PT_R8(sp)
                 LONG_L  $9, PT_R9(sp)
 #endif
@@ -217,7 +217,7 @@
                 LONG_L  $31, PT_R31(sp)
                 LONG_L  $28, PT_R28(sp)
                 LONG_L  $25, PT_R25(sp)
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                 LONG_L  $8, PT_R8(sp)
                 LONG_L  $9, PT_R9(sp)
 #endif
@@ -262,7 +262,7 @@
                 LONG_L  $31, PT_R31(sp)
                 LONG_L  $28, PT_R28(sp)
                 LONG_L  $25, PT_R25(sp)
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                 LONG_L  $8, PT_R8(sp)
                 LONG_L  $9, PT_R9(sp)
 #endif
diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h
index 5076fec65780..c3ddf973c1c0 100644
--- a/include/asm-mips/statfs.h
+++ b/include/asm-mips/statfs.h
@@ -57,7 +57,7 @@ struct statfs64 {
 };
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
- 
+
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
 struct statfs64 {                       /* Same as struct statfs */
diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h
index b18345504f8a..5a06f6d13899 100644
--- a/include/asm-mips/string.h
+++ b/include/asm-mips/string.h
@@ -16,7 +16,7 @@
  * Most of the inline functions are rather naive implementations so I just
  * didn't bother updating them for 64-bit ...
  */
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #ifndef IN_STRING_C
 
@@ -130,7 +130,7 @@ strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
 
         return __res;
 }
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
 #define __HAVE_ARCH_MEMSET
 extern void *memset(void *__s, int __c, size_t __count);
@@ -141,7 +141,7 @@ extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
 #define __HAVE_ARCH_MEMMOVE
 extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
 
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 #define __HAVE_ARCH_MEMSCAN
 static __inline__ void *memscan(void *__addr, int __c, size_t __size)
 {
@@ -161,6 +161,6 @@ static __inline__ void *memscan(void *__addr, int __c, size_t __size)
 
         return __addr;
 }
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
 #endif /* _ASM_STRING_H */
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 169f3d4265b1..6663efd49b27 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -208,7 +208,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
         return retval;
 }
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 {
         __u64 retval;
@@ -330,7 +330,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
         return retval;
 }
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
         unsigned long new)
 {
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h
index 42fcd6f2c206..a70cb0854c8a 100644
--- a/include/asm-mips/thread_info.h
+++ b/include/asm-mips/thread_info.h
@@ -62,10 +62,10 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define current_thread_info()  __current_thread_info
 
 /* thread information allocation */
-#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS32)
+#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)
 #define THREAD_SIZE_ORDER (1)
 #endif
-#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_MIPS64)
+#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_64BIT)
 #define THREAD_SIZE_ORDER (2)
 #endif
 #ifdef CONFIG_PAGE_SIZE_8KB
diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h
index fd9599e40a0a..fee1908c65d2 100644
--- a/include/asm-mips/titan_dep.h
+++ b/include/asm-mips/titan_dep.h
@@ -228,4 +228,4 @@ extern unsigned long ocd_base;
 #define RM9K_READ_8(ofs, val)   *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
 #define RM9K_READ_16(ofs, val)  *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
 
-#endif 
+#endif
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index 5d939db6e220..3bb7f0087d68 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -45,14 +45,14 @@
 
 
 /* TX4927 SDRAM controller (64-bit registers) */
-#define TX4927_SDRAMC_BASE              0x8000 
-#define TX4927_SDRAMC_SDCCR0            0x8000 
+#define TX4927_SDRAMC_BASE              0x8000
+#define TX4927_SDRAMC_SDCCR0            0x8000
 #define TX4927_SDRAMC_SDCCR1            0x8008
 #define TX4927_SDRAMC_SDCCR2            0x8010
 #define TX4927_SDRAMC_SDCCR3            0x8018
 #define TX4927_SDRAMC_SDCTR             0x8040
 #define TX4927_SDRAMC_SDCMD             0x8058
-#define TX4927_SDRAMC_LIMIT             0x8fff 
+#define TX4927_SDRAMC_LIMIT             0x8fff
 
 
 /* TX4927 external bus controller (64-bit registers) */
@@ -289,8 +289,8 @@
 
 
 /* TX4927 serial port 0 (32-bit registers) */
-#define TX4927_SIO0_BASE                         0xf300 
-#define TX4927_SIO0_SILCR0                       0xf300 
+#define TX4927_SIO0_BASE                         0xf300
+#define TX4927_SIO0_SILCR0                       0xf300
 #define TX4927_SIO0_SILCR0_RESERVED_16_31                BM_16_31
 #define TX4927_SIO0_SILCR0_RWUB                          BM_15_15
 #define TX4927_SIO0_SILCR0_TWUB                          BM_14_14
@@ -309,7 +309,7 @@
 #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT            (~BM_00_01)
 #define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC           BM_01_01
 #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC           BM_00_01
-#define TX4927_SIO0_SIDICR0                      0xf304 
+#define TX4927_SIO0_SIDICR0                      0xf304
 #define TX4927_SIO0_SIDICR0_RESERVED_16_31               BM_16_31
 #define TX4927_SIO0_SIDICR0_TDE                          BM_15_15
 #define TX4927_SIO0_SIDICR0_RDE                          BM_14_14
@@ -330,7 +330,7 @@
 #define TX4927_SIO0_SIDICR0_STIE_TRDY                    BM_02_02
 #define TX4927_SIO0_SIDICR0_STIE_TXALS                   BM_01_01
 #define TX4927_SIO0_SIDICR0_STIE_UBRKD                   BM_00_00
-#define TX4927_SIO0_SIDISR0                      0xf308 
+#define TX4927_SIO0_SIDISR0                      0xf308
 #define TX4927_SIO0_SIDISR0_RESERVED_16_31               BM_16_31
 #define TX4927_SIO0_SIDISR0_UBRK                         BM_15_15
 #define TX4927_SIO0_SIDISR0_UVALID                       BM_14_14
@@ -344,7 +344,7 @@
 #define TX4927_SIO0_SIDISR0_STIS                         BM_06_06
 #define TX4927_SIO0_SIDISR0_RESERVED_05_05               BM_05_05
 #define TX4927_SIO0_SIDISR0_RFDN                         BM_00_04
-#define TX4927_SIO0_SISCISR0                     0xf30c 
+#define TX4927_SIO0_SISCISR0                     0xf30c
 #define TX4927_SIO0_SISCISR0_RESERVED_06_31              BM_06_31
 #define TX4927_SIO0_SISCISR0_OERS                        BM_05_05
 #define TX4927_SIO0_SISCISR0_CTSS                        BM_04_04
@@ -352,7 +352,7 @@
 #define TX4927_SIO0_SISCISR0_TRDY                        BM_02_02
 #define TX4927_SIO0_SISCISR0_TXALS                       BM_01_01
 #define TX4927_SIO0_SISCISR0_UBRKD                       BM_00_00
-#define TX4927_SIO0_SIFCR0                       0xf310 
+#define TX4927_SIO0_SIFCR0                       0xf310
 #define TX4927_SIO0_SIFCR0_RESERVED_16_31                BM_16_31
 #define TX4927_SIO0_SIFCR0_SWRST                         BM_16_31
 #define TX4927_SIO0_SIFCR0_RESERVED_09_14                BM_09_14
@@ -370,7 +370,7 @@
 #define TX4927_SIO0_SIFCR0_TFRST                         BM_02_02
 #define TX4927_SIO0_SIFCR0_RFRST                         BM_01_01
 #define TX4927_SIO0_SIFCR0_FRSTE                         BM_00_00
-#define TX4927_SIO0_SIFLCR0                      0xf314 
+#define TX4927_SIO0_SIFLCR0                      0xf314
 #define TX4927_SIO0_SIFLCR0_RESERVED_13_31               BM_13_31
 #define TX4927_SIO0_SIFLCR0_RCS                          BM_12_12
 #define TX4927_SIO0_SIFLCR0_TES                          BM_11_11
@@ -381,7 +381,7 @@
 #define TX4927_SIO0_SIFLCR0_RESERVED_05_06               BM_05_06
 #define TX4927_SIO0_SIFLCR0_RTSTL                        BM_01_04
 #define TX4927_SIO0_SIFLCR0_TBRK                         BM_00_00
-#define TX4927_SIO0_SIBGR0                       0xf318 
+#define TX4927_SIO0_SIBGR0                       0xf318
 #define TX4927_SIO0_SIBGR0_RESERVED_10_31                BM_10_31
 #define TX4927_SIO0_SIBGR0_BCLK                          BM_08_09
 #define TX4927_SIO0_SIBGR0_BCLK_T0                     (~BM_08_09)
@@ -389,28 +389,28 @@
 #define TX4927_SIO0_SIBGR0_BCLK_T4                       BM_09_09
 #define TX4927_SIO0_SIBGR0_BCLK_T6                       BM_08_09
 #define TX4927_SIO0_SIBGR0_BRD                           BM_00_07
-#define TX4927_SIO0_SITFIF00                     0xf31c 
+#define TX4927_SIO0_SITFIF00                     0xf31c
 #define TX4927_SIO0_SITFIF00_RESERVED_08_31              BM_08_31
 #define TX4927_SIO0_SITFIF00_TXD                         BM_00_07
-#define TX4927_SIO0_SIRFIFO0                     0xf320          
+#define TX4927_SIO0_SIRFIFO0                     0xf320
 #define TX4927_SIO0_SIRFIFO0_RESERVED_08_31              BM_08_31
 #define TX4927_SIO0_SIRFIFO0_RXD                         BM_00_07
-#define TX4927_SIO0_SIRFIFO0                     0xf320          
-#define TX4927_SIO0_LIMIT                        0xf3ff 
+#define TX4927_SIO0_SIRFIFO0                     0xf320
+#define TX4927_SIO0_LIMIT                        0xf3ff
 
 
 /* TX4927 serial port 1 (32-bit registers) */
-#define TX4927_SIO1_BASE                0xf400 
-#define TX4927_SIO1_SILCR1              0xf400 
-#define TX4927_SIO1_SIDICR1             0xf404 
-#define TX4927_SIO1_SIDISR1             0xf408 
-#define TX4927_SIO1_SISCISR1            0xf40c 
-#define TX4927_SIO1_SIFCR1              0xf410 
-#define TX4927_SIO1_SIFLCR1             0xf414 
-#define TX4927_SIO1_SIBGR1              0xf418 
-#define TX4927_SIO1_SITFIF01            0xf41c 
-#define TX4927_SIO1_SIRFIFO1            0xf420 
-#define TX4927_SIO1_LIMIT               0xf4ff 
+#define TX4927_SIO1_BASE                0xf400
+#define TX4927_SIO1_SILCR1              0xf400
+#define TX4927_SIO1_SIDICR1             0xf404
+#define TX4927_SIO1_SIDISR1             0xf408
+#define TX4927_SIO1_SISCISR1            0xf40c
+#define TX4927_SIO1_SIFCR1              0xf410
+#define TX4927_SIO1_SIFLCR1             0xf414
+#define TX4927_SIO1_SIBGR1              0xf418
+#define TX4927_SIO1_SITFIF01            0xf41c
+#define TX4927_SIO1_SIRFIFO1            0xf420
+#define TX4927_SIO1_LIMIT               0xf4ff
 
 
 /* TX4927 parallel port (32-bit registers) */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index 170433492246..165f6b8b217f 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -5,8 +5,8 @@
  *
  * Copyright (C) 2000-2001 Toshiba Corporation
  */
-#ifndef __ASM_TX4927_TX4927_PCI_H 
-#define __ASM_TX4927_TX4927_PCI_H 
+#ifndef __ASM_TX4927_TX4927_PCI_H
+#define __ASM_TX4927_TX4927_PCI_H
 
 #define TX4927_CCFG_TOE 0x00004000
 
diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h
index d2f0c76b00a9..421b3aea14cc 100644
--- a/include/asm-mips/types.h
+++ b/include/asm-mips/types.h
@@ -78,7 +78,7 @@ typedef unsigned long long u64;
 #endif
 
 #if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
-    || defined(CONFIG_MIPS64)
+    || defined(CONFIG_64BIT)
 typedef u64 dma_addr_t;
 #else
 typedef u32 dma_addr_t;
@@ -99,8 +99,6 @@ typedef u64 sector_t;
 #define HAVE_SECTOR_T
 #endif
 
-typedef unsigned short kmem_bufctl_t;
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
index 07114898e065..5c2c98329012 100644
--- a/include/asm-mips/uaccess.h
+++ b/include/asm-mips/uaccess.h
@@ -22,7 +22,7 @@
  *
  * For historical reasons, these macros are grossly misnamed.
  */
-#ifdef CONFIG_MIPS32
+#ifdef CONFIG_32BIT
 
 #define __UA_LIMIT      0x80000000UL
 
@@ -32,9 +32,9 @@
 #define __UA_t0         "$8"
 #define __UA_t1         "$9"
 
-#endif /* CONFIG_MIPS32 */
+#endif /* CONFIG_32BIT */
 
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
 
 #define __UA_LIMIT      (- TASK_SIZE)
 
@@ -44,7 +44,7 @@
 #define __UA_t0         "$12"
 #define __UA_t1         "$13"
 
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
 /*
  * USER_DS is a bitmask that has the bits set that may not be set in a valid
@@ -112,29 +112,6 @@
         likely(__access_ok((unsigned long)(addr), (size),__access_mask))
 
 /*
- * verify_area: - Obsolete/deprecated and will go away soon,
- * use access_ok() instead.
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE
- * @addr: User space pointer to start of block to check
- * @size: Size of block to check
- *
- * Context: User context only.  This function may sleep.
- *
- * This function has been replaced by access_ok().
- *
- * Checks if a pointer to a block of memory in user space is valid.
- *
- * Returns zero if the memory block may be valid, -EFAULT
- * if it is definitely invalid.
- *
- * See access_ok() for more details.
- */
-static inline int __deprecated verify_area(int type, const void * addr, unsigned long size)
-{
-        return access_ok(type, addr, size) ? 0 : -EFAULT;
-}
-
-/*
  * put_user: - Write a simple value into user space.
  * @x:   Value to copy to user space.
  * @ptr: Destination address, in user space.
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index 6d21cc964f76..ad4d48056307 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -1124,7 +1124,7 @@ type name (atype a,btype b,ctype c,dtype d,etype e,ftype f) \
 # ifndef __mips64
 #  define __ARCH_WANT_STAT64
 # endif
-# ifdef CONFIG_MIPS32
+# ifdef CONFIG_32BIT
 #  define __ARCH_WANT_SYS_TIME
 # endif
 # ifdef CONFIG_MIPS32_O32
diff --git a/include/asm-mips/vr4181/irq.h b/include/asm-mips/vr4181/irq.h
deleted file mode 100644
index 4bf0ea970ed0..000000000000
--- a/include/asm-mips/vr4181/irq.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Macros for vr4181 IRQ numbers.
- *
- * Copyright (C) 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-/*
- * Strategy:
- *
- * Vr4181 has conceptually three levels of interrupt controllers:
- *  1. the CPU itself with 8 intr level.
- *  2. system interrupt controller, cascaded from int0 pin in CPU, 32 intrs
- *  3. GPIO interrupts : forwarding external interrupts to sys intr controller
- */
-
-/* decide the irq block assignment */
-#define VR4181_NUM_CPU_IRQ      8
-#define VR4181_NUM_SYS_IRQ      32
-#define VR4181_NUM_GPIO_IRQ     16
-
-#define VR4181_IRQ_BASE         0
-
-#define VR4181_CPU_IRQ_BASE     VR4181_IRQ_BASE
-#define VR4181_SYS_IRQ_BASE     (VR4181_CPU_IRQ_BASE + VR4181_NUM_CPU_IRQ)
-#define VR4181_GPIO_IRQ_BASE    (VR4181_SYS_IRQ_BASE + VR4181_NUM_SYS_IRQ)
-
-/* CPU interrupts */
-
-/*
-   IP0 - Software interrupt
-   IP1 - Software interrupt
-   IP2 - All but battery, high speed modem, and real time clock
-   IP3 - RTC Long1 (system timer)
-   IP4 - RTC Long2
-   IP5 - High Speed Modem (unused on VR4181)
-   IP6 - Unused
-   IP7 - Timer interrupt from CPO_COMPARE
-*/
-
-#define VR4181_IRQ_SW1       (VR4181_CPU_IRQ_BASE + 0)
-#define VR4181_IRQ_SW2       (VR4181_CPU_IRQ_BASE + 1)
-#define VR4181_IRQ_INT0      (VR4181_CPU_IRQ_BASE + 2)
-#define VR4181_IRQ_INT1      (VR4181_CPU_IRQ_BASE + 3)
-#define VR4181_IRQ_INT2      (VR4181_CPU_IRQ_BASE + 4)
-#define VR4181_IRQ_INT3      (VR4181_CPU_IRQ_BASE + 5)
-#define VR4181_IRQ_INT4      (VR4181_CPU_IRQ_BASE + 6)
-#define VR4181_IRQ_TIMER     (VR4181_CPU_IRQ_BASE + 7)
-
-
-/* Cascaded from VR4181_IRQ_INT0 (ICU mapped interrupts) */
-
-/*
-   IP2 - same as VR4181_IRQ_INT1
-   IP8 - This is a cascade to GPIO IRQ's. Do not use.
-   IP16 - same as VR4181_IRQ_INT2
-   IP18 - CompactFlash
-*/
-
-#define VR4181_IRQ_BATTERY   (VR4181_SYS_IRQ_BASE + 0)
-#define VR4181_IRQ_POWER     (VR4181_SYS_IRQ_BASE + 1)
-#define VR4181_IRQ_RTCL1     (VR4181_SYS_IRQ_BASE + 2)
-#define VR4181_IRQ_ETIMER    (VR4181_SYS_IRQ_BASE + 3)
-#define VR4181_IRQ_RFU12     (VR4181_SYS_IRQ_BASE + 4)
-#define VR4181_IRQ_PIU       (VR4181_SYS_IRQ_BASE + 5)
-#define VR4181_IRQ_AIU       (VR4181_SYS_IRQ_BASE + 6)
-#define VR4181_IRQ_KIU       (VR4181_SYS_IRQ_BASE + 7)
-#define VR4181_IRQ_GIU       (VR4181_SYS_IRQ_BASE + 8)
-#define VR4181_IRQ_SIU       (VR4181_SYS_IRQ_BASE + 9)
-#define VR4181_IRQ_RFU18     (VR4181_SYS_IRQ_BASE + 10)
-#define VR4181_IRQ_SOFT      (VR4181_SYS_IRQ_BASE + 11)
-#define VR4181_IRQ_RFU20     (VR4181_SYS_IRQ_BASE + 12)
-#define VR4181_IRQ_DOZEPIU   (VR4181_SYS_IRQ_BASE + 13)
-#define VR4181_IRQ_RFU22     (VR4181_SYS_IRQ_BASE + 14)
-#define VR4181_IRQ_RFU23     (VR4181_SYS_IRQ_BASE + 15)
-#define VR4181_IRQ_RTCL2     (VR4181_SYS_IRQ_BASE + 16)
-#define VR4181_IRQ_LED       (VR4181_SYS_IRQ_BASE + 17)
-#define VR4181_IRQ_ECU       (VR4181_SYS_IRQ_BASE + 18)
-#define VR4181_IRQ_CSU       (VR4181_SYS_IRQ_BASE + 19)
-#define VR4181_IRQ_USB       (VR4181_SYS_IRQ_BASE + 20)
-#define VR4181_IRQ_DMA       (VR4181_SYS_IRQ_BASE + 21)
-#define VR4181_IRQ_LCD       (VR4181_SYS_IRQ_BASE + 22)
-#define VR4181_IRQ_RFU31     (VR4181_SYS_IRQ_BASE + 23)
-#define VR4181_IRQ_RFU32     (VR4181_SYS_IRQ_BASE + 24)
-#define VR4181_IRQ_RFU33     (VR4181_SYS_IRQ_BASE + 25)
-#define VR4181_IRQ_RFU34     (VR4181_SYS_IRQ_BASE + 26)
-#define VR4181_IRQ_RFU35     (VR4181_SYS_IRQ_BASE + 27)
-#define VR4181_IRQ_RFU36     (VR4181_SYS_IRQ_BASE + 28)
-#define VR4181_IRQ_RFU37     (VR4181_SYS_IRQ_BASE + 29)
-#define VR4181_IRQ_RFU38     (VR4181_SYS_IRQ_BASE + 30)
-#define VR4181_IRQ_RFU39     (VR4181_SYS_IRQ_BASE + 31)
-
-/* Cascaded from VR4181_IRQ_GIU */
-#define VR4181_IRQ_GPIO0     (VR4181_GPIO_IRQ_BASE + 0)
-#define VR4181_IRQ_GPIO1     (VR4181_GPIO_IRQ_BASE + 1)
-#define VR4181_IRQ_GPIO2     (VR4181_GPIO_IRQ_BASE + 2)
-#define VR4181_IRQ_GPIO3     (VR4181_GPIO_IRQ_BASE + 3)
-#define VR4181_IRQ_GPIO4     (VR4181_GPIO_IRQ_BASE + 4)
-#define VR4181_IRQ_GPIO5     (VR4181_GPIO_IRQ_BASE + 5)
-#define VR4181_IRQ_GPIO6     (VR4181_GPIO_IRQ_BASE + 6)
-#define VR4181_IRQ_GPIO7     (VR4181_GPIO_IRQ_BASE + 7)
-#define VR4181_IRQ_GPIO8     (VR4181_GPIO_IRQ_BASE + 8)
-#define VR4181_IRQ_GPIO9     (VR4181_GPIO_IRQ_BASE + 9)
-#define VR4181_IRQ_GPIO10    (VR4181_GPIO_IRQ_BASE + 10)
-#define VR4181_IRQ_GPIO11    (VR4181_GPIO_IRQ_BASE + 11)
-#define VR4181_IRQ_GPIO12    (VR4181_GPIO_IRQ_BASE + 12)
-#define VR4181_IRQ_GPIO13    (VR4181_GPIO_IRQ_BASE + 13)
-#define VR4181_IRQ_GPIO14    (VR4181_GPIO_IRQ_BASE + 14)
-#define VR4181_IRQ_GPIO15    (VR4181_GPIO_IRQ_BASE + 15)
-
-
-// Alternative to above GPIO IRQ defines
-#define VR4181_IRQ_GPIO(pin) ((VR4181_IRQ_GPIO0) + (pin))
-
-#define VR4181_IRQ_MAX       (VR4181_IRQ_BASE + VR4181_NUM_CPU_IRQ + \
-                              VR4181_NUM_SYS_IRQ + VR4181_NUM_GPIO_IRQ)
diff --git a/include/asm-mips/vr4181/vr4181.h b/include/asm-mips/vr4181/vr4181.h
deleted file mode 100644
index 5c5d60741515..000000000000
--- a/include/asm-mips/vr4181/vr4181.h
+++ /dev/null
@@ -1,413 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999 by Michael Klar
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- */
-#ifndef __ASM_VR4181_VR4181_H
-#define __ASM_VR4181_VR4181_H
-
-#include <asm/addrspace.h>
-
-#include <asm/vr4181/irq.h>
-
-#ifndef __ASSEMBLY__
-#define __preg8         (volatile unsigned char*)
-#define __preg16        (volatile unsigned short*)
-#define __preg32        (volatile unsigned int*)
-#else
-#define __preg8
-#define __preg16
-#define __preg32
-#endif
-
-// Embedded CPU peripheral registers
-// Note that many of the registers have different physical address for VR4181
-
-// Bus Control Unit (BCU)
-#define VR4181_BCUCNTREG1       __preg16(KSEG1 + 0x0A000000)    /* BCU control register 1 (R/W) */
-#define VR4181_CMUCLKMSK        __preg16(KSEG1 + 0x0A000004)    /* Clock mask register (R/W) */
-#define VR4181_CMUCLKMSK_MSKCSUPCLK  0x0040
-#define VR4181_CMUCLKMSK_MSKAIUPCLK  0x0020
-#define VR4181_CMUCLKMSK_MSKPIUPCLK  0x0010
-#define VR4181_CMUCLKMSK_MSKADUPCLK  0x0008
-#define VR4181_CMUCLKMSK_MSKSIU18M   0x0004
-#define VR4181_CMUCLKMSK_MSKADU18M   0x0002
-#define VR4181_CMUCLKMSK_MSKUSB      0x0001
-#define VR4181_CMUCLKMSK_MSKSIU      VR4181_CMUCLKMSK_MSKSIU18M
-#define VR4181_BCUSPEEDREG      __preg16(KSEG1 + 0x0A00000C)    /* BCU access time parameter (R/W) */
-#define VR4181_BCURFCNTREG      __preg16(KSEG1 + 0x0A000010)    /* BCU refresh control register (R/W) */
-#define VR4181_REVIDREG         __preg16(KSEG1 + 0x0A000014)    /* Revision ID register (R) */
-#define VR4181_CLKSPEEDREG      __preg16(KSEG1 + 0x0A000018)    /* Clock speed register (R) */
-#define VR4181_EDOMCYTREG       __preg16(KSEG1 + 0x0A000300)    /* Memory cycle timing register (R/W) */
-#define VR4181_MEMCFG_REG       __preg16(KSEG1 + 0x0A000304)    /* Memory configuration register (R/W) */
-#define VR4181_MODE_REG         __preg16(KSEG1 + 0x0A000308)    /* SDRAM mode register (R/W) */
-#define VR4181_SDTIMINGREG      __preg16(KSEG1 + 0x0A00030C)    /* SDRAM timing register (R/W) */
-
-// DMA Control Unit (DCU)
-#define VR4181_MICDEST1REG1     __preg16(KSEG1 + 0x0A000020)    /* Microphone destination 1 address register 1 (R/W) */
-#define VR4181_MICDEST1REG2     __preg16(KSEG1 + 0x0A000022)    /* Microphone destination 1 address register 2 (R/W) */
-#define VR4181_MICDEST2REG1     __preg16(KSEG1 + 0x0A000024)    /* Microphone destination 2 address register 1 (R/W) */
-#define VR4181_MICDEST2REG2     __preg16(KSEG1 + 0x0A000026)    /* Microphone destination 2 address register 2 (R/W) */
-#define VR4181_SPKRRC1REG1      __preg16(KSEG1 + 0x0A000028)    /* Speaker Source 1 address register 1 (R/W) */
-#define VR4181_SPKRRC1REG2      __preg16(KSEG1 + 0x0A00002A)    /* Speaker Source 1 address register 2 (R/W) */
-#define VR4181_SPKRRC2REG1      __preg16(KSEG1 + 0x0A00002C)    /* Speaker Source 2 address register 1 (R/W) */
-#define VR4181_SPKRRC2REG2      __preg16(KSEG1 + 0x0A00002E)    /* Speaker Source 2 address register 2 (R/W) */
-#define VR4181_DMARSTREG        __preg16(KSEG1 + 0x0A000040)    /* DMA Reset register (R/W) */
-#define VR4181_AIUDMAMSKREG     __preg16(KSEG1 + 0x0A000046)    /* Audio DMA mask register (R/W) */
-#define VR4181_USBDMAMSKREG     __preg16(KSEG1 + 0x0A000600)    /* USB DMA Mask register (R/W) */
-#define VR4181_USBRXS1AREG1     __preg16(KSEG1 + 0x0A000602)    /* USB Rx source 1 address register 1 (R/W) */
-#define VR4181_USBRXS1AREG2     __preg16(KSEG1 + 0x0A000604)    /* USB Rx source 1 address register 2 (R/W) */
-#define VR4181_USBRXS2AREG1     __preg16(KSEG1 + 0x0A000606)    /* USB Rx source 2 address register 1 (R/W) */
-#define VR4181_USBRXS2AREG2     __preg16(KSEG1 + 0x0A000608)    /* USB Rx source 2 address register 2 (R/W) */
-#define VR4181_USBTXS1AREG1     __preg16(KSEG1 + 0x0A00060A)    /* USB Tx source 1 address register 1 (R/W) */
-#define VR4181_USBTXS1AREG2     __preg16(KSEG1 + 0x0A00060C)    /* USB Tx source 1 address register 2 (R/W) */
-#define VR4181_USBTXS2AREG1     __preg16(KSEG1 + 0x0A00060E)    /* USB Tx source 2 address register 1 (R/W) */
-#define VR4181_USBTXS2AREG2     __preg16(KSEG1 + 0x0A000610)    /* USB Tx source 2 address register 2 (R/W) */
-#define VR4181_USBRXD1AREG1     __preg16(KSEG1 + 0x0A00062A)    /* USB Rx destination 1 address register 1 (R/W) */
-#define VR4181_USBRXD1AREG2     __preg16(KSEG1 + 0x0A00062C)    /* USB Rx destination 1 address register 2 (R/W) */
-#define VR4181_USBRXD2AREG1     __preg16(KSEG1 + 0x0A00062E)    /* USB Rx destination 2 address register 1 (R/W) */
-#define VR4181_USBRXD2AREG2     __preg16(KSEG1 + 0x0A000630)    /* USB Rx destination 2 address register 2 (R/W) */
-#define VR4181_USBTXD1AREG1     __preg16(KSEG1 + 0x0A000632)    /* USB Tx destination 1 address register 1 (R/W) */
-#define VR4181_USBTXD1AREG2     __preg16(KSEG1 + 0x0A000634)    /* USB Tx destination 1 address register 2 (R/W) */
-#define VR4181_USBTXD2AREG1     __preg16(KSEG1 + 0x0A000636)    /* USB Tx destination 2 address register 1 (R/W) */
-#define VR4181_USBTXD2AREG2     __preg16(KSEG1 + 0x0A000638)    /* USB Tx destination 2 address register 2 (R/W) */
-#define VR4181_RxRCLENREG       __preg16(KSEG1 + 0x0A000652)    /* USB Rx record length register (R/W) */
-#define VR4181_TxRCLENREG       __preg16(KSEG1 + 0x0A000654)    /* USB Tx record length register (R/W) */
-#define VR4181_MICRCLENREG      __preg16(KSEG1 + 0x0A000658)    /* Microphone record length register (R/W) */
-#define VR4181_SPKRCLENREG      __preg16(KSEG1 + 0x0A00065A)    /* Speaker record length register (R/W) */
-#define VR4181_USBCFGREG        __preg16(KSEG1 + 0x0A00065C)    /* USB configuration register (R/W) */
-#define VR4181_MICDMACFGREG     __preg16(KSEG1 + 0x0A00065E)    /* Microphone DMA configuration register (R/W) */
-#define VR4181_SPKDMACFGREG     __preg16(KSEG1 + 0x0A000660)    /* Speaker DMA configuration register (R/W) */
-#define VR4181_DMAITRQREG       __preg16(KSEG1 + 0x0A000662)    /* DMA interrupt request register (R/W) */
-#define VR4181_DMACLTREG        __preg16(KSEG1 + 0x0A000664)    /* DMA control register (R/W) */
-#define VR4181_DMAITMKREG       __preg16(KSEG1 + 0x0A000666)    /* DMA interrupt mask register (R/W) */
-
-// ISA Bridge
-#define VR4181_ISABRGCTL        __preg16(KSEG1 + 0x0B0002C0)    /* ISA Bridge Control Register (R/W) */
-#define VR4181_ISABRGSTS        __preg16(KSEG1 + 0x0B0002C2)    /* ISA Bridge Status Register (R/W) */
-#define VR4181_XISACTL          __preg16(KSEG1 + 0x0B0002C4)    /* External ISA Control Register (R/W) */
-
-// Clocked Serial Interface (CSI)
-#define VR4181_CSIMODE          __preg16(KSEG1 + 0x0B000900)    /* CSI Mode Register (R/W) */
-#define VR4181_CSIRXDATA        __preg16(KSEG1 + 0x0B000902)    /* CSI Receive Data Register (R) */
-#define VR4181_CSITXDATA        __preg16(KSEG1 + 0x0B000904)    /* CSI Transmit Data Register (R/W) */
-#define VR4181_CSILSTAT         __preg16(KSEG1 + 0x0B000906)    /* CSI Line Status Register (R/W) */
-#define VR4181_CSIINTMSK        __preg16(KSEG1 + 0x0B000908)    /* CSI Interrupt Mask Register (R/W) */
-#define VR4181_CSIINTSTAT       __preg16(KSEG1 + 0x0B00090a)    /* CSI Interrupt Status Register (R/W) */
-#define VR4181_CSITXBLEN        __preg16(KSEG1 + 0x0B00090c)    /* CSI Transmit Burst Length Register (R/W) */
-#define VR4181_CSIRXBLEN        __preg16(KSEG1 + 0x0B00090e)    /* CSI Receive Burst Length Register (R/W) */
-
-// Interrupt Control Unit (ICU)
-#define VR4181_SYSINT1REG       __preg16(KSEG1 + 0x0A000080)    /* Level 1 System interrupt register 1 (R) */
-#define VR4181_MSYSINT1REG      __preg16(KSEG1 + 0x0A00008C)    /* Level 1 mask system interrupt register 1 (R/W) */
-#define VR4181_NMIREG           __preg16(KSEG1 + 0x0A000098)    /* NMI register (R/W) */
-#define VR4181_SOFTINTREG       __preg16(KSEG1 + 0x0A00009A)    /* Software interrupt register (R/W) */
-#define VR4181_SYSINT2REG       __preg16(KSEG1 + 0x0A000200)    /* Level 1 System interrupt register 2 (R) */
-#define VR4181_MSYSINT2REG      __preg16(KSEG1 + 0x0A000206)    /* Level 1 mask system interrupt register 2 (R/W) */
-#define VR4181_PIUINTREGro      __preg16(KSEG1 + 0x0B000082)    /* Level 2 PIU interrupt register (R) */
-#define VR4181_AIUINTREG        __preg16(KSEG1 + 0x0B000084)    /* Level 2 AIU interrupt register (R) */
-#define VR4181_MPIUINTREG       __preg16(KSEG1 + 0x0B00008E)    /* Level 2 mask PIU interrupt register (R/W) */
-#define VR4181_MAIUINTREG       __preg16(KSEG1 + 0x0B000090)    /* Level 2 mask AIU interrupt register (R/W) */
-#define VR4181_MKIUINTREG       __preg16(KSEG1 + 0x0B000092)    /* Level 2 mask KIU interrupt register (R/W) */
-#define VR4181_KIUINTREG        __preg16(KSEG1 + 0x0B000198)    /* Level 2 KIU interrupt register (R) */
-
-// Power Management Unit (PMU)
-#define VR4181_PMUINTREG        __preg16(KSEG1 + 0x0B0000A0)    /* PMU Status Register (R/W) */
-#define VR4181_PMUINT_POWERSW  0x1      /* Power switch */
-#define VR4181_PMUINT_BATT     0x2      /* Low batt during normal operation */
-#define VR4181_PMUINT_DEADMAN  0x4      /* Deadman's switch */
-#define VR4181_PMUINT_RESET    0x8      /* Reset switch */
-#define VR4181_PMUINT_RTCRESET 0x10     /* RTC Reset */
-#define VR4181_PMUINT_TIMEOUT  0x20     /* HAL Timer Reset */
-#define VR4181_PMUINT_BATTLOW  0x100    /* Battery low */
-#define VR4181_PMUINT_RTC      0x200    /* RTC Alarm */
-#define VR4181_PMUINT_DCD      0x400    /* DCD# */
-#define VR4181_PMUINT_GPIO0    0x1000   /* GPIO0 */
-#define VR4181_PMUINT_GPIO1    0x2000   /* GPIO1 */
-#define VR4181_PMUINT_GPIO2    0x4000   /* GPIO2 */
-#define VR4181_PMUINT_GPIO3    0x8000   /* GPIO3 */
-
-#define VR4181_PMUCNTREG        __preg16(KSEG1 + 0x0B0000A2)    /* PMU Control Register (R/W) */
-#define VR4181_PMUWAITREG       __preg16(KSEG1 + 0x0B0000A8)    /* PMU Wait Counter Register (R/W) */
-#define VR4181_PMUDIVREG        __preg16(KSEG1 + 0x0B0000AC)    /* PMU Divide Mode Register (R/W) */
-#define VR4181_DRAMHIBCTL       __preg16(KSEG1 + 0x0B0000B2)    /* DRAM Hibernate Control Register (R/W) */
-
-// Real Time Clock Unit (RTC)
-#define VR4181_ETIMELREG        __preg16(KSEG1 + 0x0B0000C0)    /* Elapsed Time L Register (R/W) */
-#define VR4181_ETIMEMREG        __preg16(KSEG1 + 0x0B0000C2)    /* Elapsed Time M Register (R/W) */
-#define VR4181_ETIMEHREG        __preg16(KSEG1 + 0x0B0000C4)    /* Elapsed Time H Register (R/W) */
-#define VR4181_ECMPLREG         __preg16(KSEG1 + 0x0B0000C8)    /* Elapsed Compare L Register (R/W) */
-#define VR4181_ECMPMREG         __preg16(KSEG1 + 0x0B0000CA)    /* Elapsed Compare M Register (R/W) */
-#define VR4181_ECMPHREG         __preg16(KSEG1 + 0x0B0000CC)    /* Elapsed Compare H Register (R/W) */
-#define VR4181_RTCL1LREG        __preg16(KSEG1 + 0x0B0000D0)    /* RTC Long 1 L Register (R/W) */
-#define VR4181_RTCL1HREG        __preg16(KSEG1 + 0x0B0000D2)    /* RTC Long 1 H Register (R/W) */
-#define VR4181_RTCL1CNTLREG     __preg16(KSEG1 + 0x0B0000D4)    /* RTC Long 1 Count L Register (R) */
-#define VR4181_RTCL1CNTHREG     __preg16(KSEG1 + 0x0B0000D6)    /* RTC Long 1 Count H Register (R) */
-#define VR4181_RTCL2LREG        __preg16(KSEG1 + 0x0B0000D8)    /* RTC Long 2 L Register (R/W) */
-#define VR4181_RTCL2HREG        __preg16(KSEG1 + 0x0B0000DA)    /* RTC Long 2 H Register (R/W) */
-#define VR4181_RTCL2CNTLREG     __preg16(KSEG1 + 0x0B0000DC)    /* RTC Long 2 Count L Register (R) */
-#define VR4181_RTCL2CNTHREG     __preg16(KSEG1 + 0x0B0000DE)    /* RTC Long 2 Count H Register (R) */
-#define VR4181_RTCINTREG        __preg16(KSEG1 + 0x0B0001DE)    /* RTC Interrupt Register (R/W) */
-
-// Deadman's Switch Unit (DSU)
-#define VR4181_DSUCNTREG        __preg16(KSEG1 + 0x0B0000E0)    /* DSU Control Register (R/W) */
-#define VR4181_DSUSETREG        __preg16(KSEG1 + 0x0B0000E2)    /* DSU Dead Time Set Register (R/W) */
-#define VR4181_DSUCLRREG        __preg16(KSEG1 + 0x0B0000E4)    /* DSU Clear Register (W) */
-#define VR4181_DSUTIMREG        __preg16(KSEG1 + 0x0B0000E6)    /* DSU Elapsed Time Register (R/W) */
-
-// General Purpose I/O Unit (GIU)
-#define VR4181_GPMD0REG         __preg16(KSEG1 + 0x0B000300)    /* GPIO Mode 0 Register (R/W) */
-#define VR4181_GPMD1REG         __preg16(KSEG1 + 0x0B000302)    /* GPIO Mode 1 Register (R/W) */
-#define VR4181_GPMD2REG         __preg16(KSEG1 + 0x0B000304)    /* GPIO Mode 2 Register (R/W) */
-#define VR4181_GPMD3REG         __preg16(KSEG1 + 0x0B000306)    /* GPIO Mode 3 Register (R/W) */
-#define VR4181_GPDATHREG        __preg16(KSEG1 + 0x0B000308)    /* GPIO Data High Register (R/W) */
-#define VR4181_GPDATHREG_GPIO16  0x0001
-#define VR4181_GPDATHREG_GPIO17  0x0002
-#define VR4181_GPDATHREG_GPIO18  0x0004
-#define VR4181_GPDATHREG_GPIO19  0x0008
-#define VR4181_GPDATHREG_GPIO20  0x0010
-#define VR4181_GPDATHREG_GPIO21  0x0020
-#define VR4181_GPDATHREG_GPIO22  0x0040
-#define VR4181_GPDATHREG_GPIO23  0x0080
-#define VR4181_GPDATHREG_GPIO24  0x0100
-#define VR4181_GPDATHREG_GPIO25  0x0200
-#define VR4181_GPDATHREG_GPIO26  0x0400
-#define VR4181_GPDATHREG_GPIO27  0x0800
-#define VR4181_GPDATHREG_GPIO28  0x1000
-#define VR4181_GPDATHREG_GPIO29  0x2000
-#define VR4181_GPDATHREG_GPIO30  0x4000
-#define VR4181_GPDATHREG_GPIO31  0x8000
-#define VR4181_GPDATLREG        __preg16(KSEG1 + 0x0B00030A)    /* GPIO Data Low Register (R/W) */
-#define VR4181_GPDATLREG_GPIO0   0x0001
-#define VR4181_GPDATLREG_GPIO1   0x0002
-#define VR4181_GPDATLREG_GPIO2   0x0004
-#define VR4181_GPDATLREG_GPIO3   0x0008
-#define VR4181_GPDATLREG_GPIO4   0x0010
-#define VR4181_GPDATLREG_GPIO5   0x0020
-#define VR4181_GPDATLREG_GPIO6   0x0040
-#define VR4181_GPDATLREG_GPIO7   0x0080
-#define VR4181_GPDATLREG_GPIO8   0x0100
-#define VR4181_GPDATLREG_GPIO9   0x0200
-#define VR4181_GPDATLREG_GPIO10  0x0400
-#define VR4181_GPDATLREG_GPIO11  0x0800
-#define VR4181_GPDATLREG_GPIO12  0x1000
-#define VR4181_GPDATLREG_GPIO13  0x2000
-#define VR4181_GPDATLREG_GPIO14  0x4000
-#define VR4181_GPDATLREG_GPIO15  0x8000
-#define VR4181_GPINTEN          __preg16(KSEG1 + 0x0B00030C)    /* GPIO Interrupt Enable Register (R/W) */
-#define VR4181_GPINTMSK         __preg16(KSEG1 + 0x0B00030E)    /* GPIO Interrupt Mask Register (R/W) */
-#define VR4181_GPINTTYPH        __preg16(KSEG1 + 0x0B000310)    /* GPIO Interrupt Type High Register (R/W) */
-#define VR4181_GPINTTYPL        __preg16(KSEG1 + 0x0B000312)    /* GPIO Interrupt Type Low Register (R/W) */
-#define VR4181_GPINTSTAT        __preg16(KSEG1 + 0x0B000314)    /* GPIO Interrupt Status Register (R/W) */
-#define VR4181_GPHIBSTH         __preg16(KSEG1 + 0x0B000316)    /* GPIO Hibernate Pin State High Register (R/W) */
-#define VR4181_GPHIBSTL         __preg16(KSEG1 + 0x0B000318)    /* GPIO Hibernate Pin State Low Register (R/W) */
-#define VR4181_GPSICTL          __preg16(KSEG1 + 0x0B00031A)    /* GPIO Serial Interface Control Register (R/W) */
-#define VR4181_KEYEN            __preg16(KSEG1 + 0x0B00031C)    /* Keyboard Scan Pin Enable Register (R/W) */
-#define VR4181_PCS0STRA         __preg16(KSEG1 + 0x0B000320)    /* Programmable Chip Select [0] Start Address Register (R/W) */
-#define VR4181_PCS0STPA         __preg16(KSEG1 + 0x0B000322)    /* Programmable Chip Select [0] Stop Address Register (R/W) */
-#define VR4181_PCS0HIA          __preg16(KSEG1 + 0x0B000324)    /* Programmable Chip Select [0] High Address Register (R/W) */
-#define VR4181_PCS1STRA         __preg16(KSEG1 + 0x0B000326)    /* Programmable Chip Select [1] Start Address Register (R/W) */
-#define VR4181_PCS1STPA         __preg16(KSEG1 + 0x0B000328)    /* Programmable Chip Select [1] Stop Address Register (R/W) */
-#define VR4181_PCS1HIA          __preg16(KSEG1 + 0x0B00032A)    /* Programmable Chip Select [1] High Address Register (R/W) */
-#define VR4181_PCSMODE          __preg16(KSEG1 + 0x0B00032C)    /* Programmable Chip Select Mode Register (R/W) */
-#define VR4181_LCDGPMODE        __preg16(KSEG1 + 0x0B00032E)    /* LCD General Purpose Mode Register (R/W) */
-#define VR4181_MISCREG0         __preg16(KSEG1 + 0x0B000330)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG1         __preg16(KSEG1 + 0x0B000332)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG2         __preg16(KSEG1 + 0x0B000334)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG3         __preg16(KSEG1 + 0x0B000336)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG4         __preg16(KSEG1 + 0x0B000338)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG5         __preg16(KSEG1 + 0x0B00033A)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG6         __preg16(KSEG1 + 0x0B00033C)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG7         __preg16(KSEG1 + 0x0B00033D)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG8         __preg16(KSEG1 + 0x0B000340)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG9         __preg16(KSEG1 + 0x0B000342)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG10        __preg16(KSEG1 + 0x0B000344)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG11        __preg16(KSEG1 + 0x0B000346)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG12        __preg16(KSEG1 + 0x0B000348)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG13        __preg16(KSEG1 + 0x0B00034A)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG14        __preg16(KSEG1 + 0x0B00034C)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_MISCREG15        __preg16(KSEG1 + 0x0B00034E)    /* Misc. R/W Battery Backed Registers for Non-Volatile Storage (R/W) */
-#define VR4181_SECIRQMASKL      VR4181_GPINTEN
-// No SECIRQMASKH for VR4181
-
-// Touch Panel Interface Unit (PIU)
-#define VR4181_PIUCNTREG        __preg16(KSEG1 + 0x0B000122)    /* PIU Control register (R/W) */
-#define VR4181_PIUCNTREG_PIUSEQEN       0x0004
-#define VR4181_PIUCNTREG_PIUPWR         0x0002
-#define VR4181_PIUCNTREG_PADRST         0x0001
-
-#define VR4181_PIUINTREG        __preg16(KSEG1 + 0x0B000124)    /* PIU Interrupt cause register (R/W) */
-#define VR4181_PIUINTREG_OVP            0x8000
-#define VR4181_PIUINTREG_PADCMD         0x0040
-#define VR4181_PIUINTREG_PADADP         0x0020
-#define VR4181_PIUINTREG_PADPAGE1       0x0010
-#define VR4181_PIUINTREG_PADPAGE0       0x0008
-#define VR4181_PIUINTREG_PADDLOST       0x0004
-#define VR4181_PIUINTREG_PENCHG         0x0001
-
-#define VR4181_PIUSIVLREG       __preg16(KSEG1 + 0x0B000126)    /* PIU Data sampling interval register (R/W) */
-#define VR4181_PIUSTBLREG       __preg16(KSEG1 + 0x0B000128)    /* PIU A/D converter start delay register (R/W) */
-#define VR4181_PIUCMDREG        __preg16(KSEG1 + 0x0B00012A)    /* PIU A/D command register (R/W) */
-#define VR4181_PIUASCNREG       __preg16(KSEG1 + 0x0B000130)    /* PIU A/D port scan register (R/W) */
-#define VR4181_PIUAMSKREG       __preg16(KSEG1 + 0x0B000132)    /* PIU A/D scan mask register (R/W) */
-#define VR4181_PIUCIVLREG       __preg16(KSEG1 + 0x0B00013E)    /* PIU Check interval register (R) */
-#define VR4181_PIUPB00REG       __preg16(KSEG1 + 0x0B0002A0)    /* PIU Page 0 Buffer 0 register (R/W) */
-#define VR4181_PIUPB01REG       __preg16(KSEG1 + 0x0B0002A2)    /* PIU Page 0 Buffer 1 register (R/W) */
-#define VR4181_PIUPB02REG       __preg16(KSEG1 + 0x0B0002A4)    /* PIU Page 0 Buffer 2 register (R/W) */
-#define VR4181_PIUPB03REG       __preg16(KSEG1 + 0x0B0002A6)    /* PIU Page 0 Buffer 3 register (R/W) */
-#define VR4181_PIUPB10REG       __preg16(KSEG1 + 0x0B0002A8)    /* PIU Page 1 Buffer 0 register (R/W) */
-#define VR4181_PIUPB11REG       __preg16(KSEG1 + 0x0B0002AA)    /* PIU Page 1 Buffer 1 register (R/W) */
-#define VR4181_PIUPB12REG       __preg16(KSEG1 + 0x0B0002AC)    /* PIU Page 1 Buffer 2 register (R/W) */
-#define VR4181_PIUPB13REG       __preg16(KSEG1 + 0x0B0002AE)    /* PIU Page 1 Buffer 3 register (R/W) */
-#define VR4181_PIUAB0REG        __preg16(KSEG1 + 0x0B0002B0)    /* PIU A/D scan Buffer 0 register (R/W) */
-#define VR4181_PIUAB1REG        __preg16(KSEG1 + 0x0B0002B2)    /* PIU A/D scan Buffer 1 register (R/W) */
-#define VR4181_PIUAB2REG        __preg16(KSEG1 + 0x0B0002B4)    /* PIU A/D scan Buffer 2 register (R/W) */
-#define VR4181_PIUAB3REG        __preg16(KSEG1 + 0x0B0002B6)    /* PIU A/D scan Buffer 3 register (R/W) */
-#define VR4181_PIUPB04REG       __preg16(KSEG1 + 0x0B0002BC)    /* PIU Page 0 Buffer 4 register (R/W) */
-#define VR4181_PIUPB14REG       __preg16(KSEG1 + 0x0B0002BE)    /* PIU Page 1 Buffer 4 register (R/W) */
-
-// Audio Interface Unit (AIU)
-#define VR4181_SODATREG         __preg16(KSEG1 + 0x0B000166)    /* Speaker Output Data Register (R/W) */
-#define VR4181_SCNTREG          __preg16(KSEG1 + 0x0B000168)    /* Speaker Output Control Register (R/W) */
-#define VR4181_MIDATREG         __preg16(KSEG1 + 0x0B000170)    /* Mike Input Data Register (R/W) */
-#define VR4181_MCNTREG          __preg16(KSEG1 + 0x0B000172)    /* Mike Input Control Register (R/W) */
-#define VR4181_DVALIDREG        __preg16(KSEG1 + 0x0B000178)    /* Data Valid Register (R/W) */
-#define VR4181_SEQREG           __preg16(KSEG1 + 0x0B00017A)    /* Sequential Register (R/W) */
-#define VR4181_INTREG           __preg16(KSEG1 + 0x0B00017C)    /* Interrupt Register (R/W) */
-#define VR4181_SDMADATREG       __preg16(KSEG1 + 0x0B000160)    /* Speaker DMA Data Register (R/W) */
-#define VR4181_MDMADATREG       __preg16(KSEG1 + 0x0B000162)    /* Microphone DMA Data Register (R/W) */
-#define VR4181_DAVREF_SETUP     __preg16(KSEG1 + 0x0B000164)    /* DAC Vref setup register (R/W) */
-#define VR4181_SCNVC_END        __preg16(KSEG1 + 0x0B00016E)    /* Speaker sample rate control (R/W) */
-#define VR4181_MIDATREG         __preg16(KSEG1 + 0x0B000170)    /* Microphone Input Data Register (R/W) */
-#define VR4181_MCNTREG          __preg16(KSEG1 + 0x0B000172)    /* Microphone Input Control Register (R/W) */
-#define VR4181_MCNVC_END        __preg16(KSEG1 + 0x0B00017E)    /* Microphone sample rate control (R/W) */
-
-// Keyboard Interface Unit (KIU)
-#define VR4181_KIUDAT0          __preg16(KSEG1 + 0x0B000180)    /* KIU Data0 Register (R/W) */
-#define VR4181_KIUDAT1          __preg16(KSEG1 + 0x0B000182)    /* KIU Data1 Register (R/W) */
-#define VR4181_KIUDAT2          __preg16(KSEG1 + 0x0B000184)    /* KIU Data2 Register (R/W) */
-#define VR4181_KIUDAT3          __preg16(KSEG1 + 0x0B000186)    /* KIU Data3 Register (R/W) */
-#define VR4181_KIUDAT4          __preg16(KSEG1 + 0x0B000188)    /* KIU Data4 Register (R/W) */
-#define VR4181_KIUDAT5          __preg16(KSEG1 + 0x0B00018A)    /* KIU Data5 Register (R/W) */
-#define VR4181_KIUSCANREP       __preg16(KSEG1 + 0x0B000190)    /* KIU Scan/Repeat Register (R/W) */
-#define VR4181_KIUSCANREP_KEYEN      0x8000
-#define VR4181_KIUSCANREP_SCANSTP    0x0008
-#define VR4181_KIUSCANREP_SCANSTART  0x0004
-#define VR4181_KIUSCANREP_ATSTP      0x0002
-#define VR4181_KIUSCANREP_ATSCAN     0x0001
-#define VR4181_KIUSCANS         __preg16(KSEG1 + 0x0B000192)    /* KIU Scan Status Register (R) */
-#define VR4181_KIUWKS           __preg16(KSEG1 + 0x0B000194)    /* KIU Wait Keyscan Stable Register (R/W) */
-#define VR4181_KIUWKI           __preg16(KSEG1 + 0x0B000196)    /* KIU Wait Keyscan Interval Register (R/W) */
-#define VR4181_KIUINT           __preg16(KSEG1 + 0x0B000198)    /* KIU Interrupt Register (R/W) */
-#define VR4181_KIUINT_KDATLOST       0x0004
-#define VR4181_KIUINT_KDATRDY        0x0002
-#define VR4181_KIUINT_SCANINT        0x0001
-#define VR4181_KIUDAT6          __preg16(KSEG1 + 0x0B00018C)    /* Scan Line 6 Key Data Register (R) */
-#define VR4181_KIUDAT7          __preg16(KSEG1 + 0x0B00018E)    /* Scan Line 7 Key Data Register (R) */
-
-// CompactFlash Controller
-#define VR4181_PCCARDINDEX      __preg8(KSEG1 + 0x0B0008E0)     /* PC Card Controller Index Register */
-#define VR4181_PCCARDDATA       __preg8(KSEG1 + 0x0B0008E1)     /* PC Card Controller Data Register */
-#define VR4181_INTSTATREG       __preg16(KSEG1 + 0x0B0008F8)    /* Interrupt Status Register (R/W) */
-#define VR4181_INTMSKREG        __preg16(KSEG1 + 0x0B0008FA)    /* Interrupt Mask Register (R/W) */
-#define VR4181_CFG_REG_1        __preg16(KSEG1 + 0x0B0008FE)    /* Configuration Register 1 */
-
-// LED Control Unit (LED)
-#define VR4181_LEDHTSREG        __preg16(KSEG1 + 0x0B000240)    /* LED H Time Set register (R/W) */
-#define VR4181_LEDLTSREG        __preg16(KSEG1 + 0x0B000242)    /* LED L Time Set register (R/W) */
-#define VR4181_LEDCNTREG        __preg16(KSEG1 + 0x0B000248)    /* LED Control register (R/W) */
-#define VR4181_LEDASTCREG       __preg16(KSEG1 + 0x0B00024A)    /* LED Auto Stop Time Count register (R/W) */
-#define VR4181_LEDINTREG        __preg16(KSEG1 + 0x0B00024C)    /* LED Interrupt register (R/W) */
-
-// Serial Interface Unit (SIU / SIU1 and SIU2)
-#define VR4181_SIURB            __preg8(KSEG1 + 0x0C000010)     /* Receiver Buffer Register (Read) DLAB = 0 (R) */
-#define VR4181_SIUTH            __preg8(KSEG1 + 0x0C000010)     /* Transmitter Holding Register (Write) DLAB = 0 (W) */
-#define VR4181_SIUDLL           __preg8(KSEG1 + 0x0C000010)     /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */
-#define VR4181_SIUIE            __preg8(KSEG1 + 0x0C000011)     /* Interrupt Enable DLAB = 0 (R/W) */
-#define VR4181_SIUDLM           __preg8(KSEG1 + 0x0C000011)     /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */
-#define VR4181_SIUIID           __preg8(KSEG1 + 0x0C000012)     /* Interrupt Identification Register (Read) (R) */
-#define VR4181_SIUFC            __preg8(KSEG1 + 0x0C000012)     /* FIFO Control Register (Write) (W) */
-#define VR4181_SIULC            __preg8(KSEG1 + 0x0C000013)     /* Line Control Register (R/W) */
-#define VR4181_SIUMC            __preg8(KSEG1 + 0x0C000014)     /* MODEM Control Register (R/W) */
-#define VR4181_SIULS            __preg8(KSEG1 + 0x0C000015)     /* Line Status Register (R/W) */
-#define VR4181_SIUMS            __preg8(KSEG1 + 0x0C000016)     /* MODEM Status Register (R/W) */
-#define VR4181_SIUSC            __preg8(KSEG1 + 0x0C000017)     /* Scratch Register (R/W) */
-#define VR4181_SIURESET         __preg8(KSEG1 + 0x0C000019)     /* SIU Reset Register (R/W) */
-#define VR4181_SIUACTMSK        __preg8(KSEG1 + 0x0C00001C)     /* SIU Activity Mask (R/W) */
-#define VR4181_SIUACTTMR        __preg8(KSEG1 + 0x0C00001E)     /* SIU Activity Timer (R/W) */
-#define VR4181_SIURB_2          __preg8(KSEG1 + 0x0C000000)     /* Receive Buffer Register (Read) (R) */
-#define VR4181_SIUTH_2          __preg8(KSEG1 + 0x0C000000)     /* Transmitter Holding Register (Write) (W) */
-#define VR4181_SIUDLL_2         __preg8(KSEG1 + 0x0C000000)     /* Divisor Latch (Least Significant Byte) (R/W) */
-#define VR4181_SIUIE_2          __preg8(KSEG1 + 0x0C000001)     /* Interrupt Enable (DLAB = 0) (R/W) */
-#define VR4181_SIUDLM_2         __preg8(KSEG1 + 0x0C000001)     /* Divisor Latch (Most Significant Byte) (DLAB = 1) (R/W) */
-#define VR4181_SIUIID_2         __preg8(KSEG1 + 0x0C000002)     /* Interrupt Identification Register (Read) (R) */
-#define VR4181_SIUFC_2          __preg8(KSEG1 + 0x0C000002)     /* FIFO Control Register (Write) (W) */
-#define VR4181_SIULC_2          __preg8(KSEG1 + 0x0C000003)     /* Line Control Register (R/W) */
-#define VR4181_SIUMC_2          __preg8(KSEG1 + 0x0C000004)     /* Modem Control Register (R/W) */
-#define VR4181_SIULS_2          __preg8(KSEG1 + 0x0C000005)     /* Line Status Register (R/W) */
-#define VR4181_SIUMS_2          __preg8(KSEG1 + 0x0C000006)     /* Modem Status Register (R/W) */
-#define VR4181_SIUSC_2          __preg8(KSEG1 + 0x0C000007)     /* Scratch Register (R/W) */
-#define VR4181_SIUIRSEL_2       __preg8(KSEG1 + 0x0C000008)     /* SIU IrDA Selectot (R/W) */
-#define VR4181_SIURESET_2       __preg8(KSEG1 + 0x0C000009)     /* SIU Reset Register (R/W) */
-#define VR4181_SIUCSEL_2        __preg8(KSEG1 + 0x0C00000A)     /* IrDA Echo-back Control (R/W) */
-#define VR4181_SIUACTMSK_2      __preg8(KSEG1 + 0x0C00000C)     /* SIU Activity Mask Register (R/W) */
-#define VR4181_SIUACTTMR_2      __preg8(KSEG1 + 0x0C00000E)     /* SIU Activity Timer Register (R/W) */
-
-
-// USB Module
-#define VR4181_USBINFIFO        __preg16(KSEG1 + 0x0B000780)    /* USB Bulk Input FIFO (Bulk In End Point) (W) */
-#define VR4181_USBOUTFIFO       __preg16(KSEG1 + 0x0B000782)    /* USB Bulk Output FIFO (Bulk Out End Point) (R) */
-#define VR4181_USBCTLFIFO       __preg16(KSEG1 + 0x0B000784)    /* USB Control FIFO (Control End Point) (W) */
-#define VR4181_USBSTAT          __preg16(KSEG1 + 0x0B000786)    /* Interrupt Status Register (R/W) */
-#define VR4181_USBINTMSK        __preg16(KSEG1 + 0x0B000788)    /* Interrupt Mask Register (R/W) */
-#define VR4181_USBCTLREG        __preg16(KSEG1 + 0x0B00078A)    /* Control Register (R/W) */
-#define VR4181_USBSTPREG        __preg16(KSEG1 + 0x0B00078C)    /* USB Transfer Stop Register (R/W) */
-
-// LCD Controller
-#define VR4181_HRTOTALREG       __preg16(KSEG1 + 0x0A000400)    /* Horizontal total Register (R/W) */
-#define VR4181_HRVISIBREG       __preg16(KSEG1 + 0x0A000402)    /* Horizontal Visible Register (R/W) */
-#define VR4181_LDCLKSTREG       __preg16(KSEG1 + 0x0A000404)    /* Load clock start Register (R/W) */
-#define VR4181_LDCLKNDREG       __preg16(KSEG1 + 0x0A000406)    /* Load clock end Register (R/W) */
-#define VR4181_VRTOTALREG       __preg16(KSEG1 + 0x0A000408)    /* Vertical Total Register (R/W) */
-#define VR4181_VRVISIBREG       __preg16(KSEG1 + 0x0A00040A)    /* Vertical Visible Register (R/W) */
-#define VR4181_FVSTARTREG       __preg16(KSEG1 + 0x0A00040C)    /* FLM vertical start Register (R/W) */
-#define VR4181_FVENDREG         __preg16(KSEG1 + 0x0A00040E)    /* FLM vertical end Register (R/W) */
-#define VR4181_LCDCTRLREG       __preg16(KSEG1 + 0x0A000410)    /* LCD control Register (R/W) */
-#define VR4181_LCDINRQREG       __preg16(KSEG1 + 0x0A000412)    /* LCD Interrupt request Register (R/W) */
-#define VR4181_LCDCFGREG0       __preg16(KSEG1 + 0x0A000414)    /* LCD Configuration Register 0 (R/W) */
-#define VR4181_LCDCFGREG1       __preg16(KSEG1 + 0x0A000416)    /* LCD Configuration Register 1 (R/W) */
-#define VR4181_FBSTAD1REG       __preg16(KSEG1 + 0x0A000418)    /* Frame Buffer Start Address 1 Register (R/W) */
-#define VR4181_FBSTAD2REG       __preg16(KSEG1 + 0x0A00041A)    /* Frame Buffer Start Address 2 Register (R/W) */
-#define VR4181_FBNDAD1REG       __preg16(KSEG1 + 0x0A000420)    /* Frame Buffer End Address 1 Register (R/W) */
-#define VR4181_FBNDAD2REG       __preg16(KSEG1 + 0x0A000422)    /* Frame Buffer End Address 2 register (R/W) */
-#define VR4181_FHSTARTREG       __preg16(KSEG1 + 0x0A000424)    /* FLM horizontal Start Register (R/W) */
-#define VR4181_FHENDREG         __preg16(KSEG1 + 0x0A000426)    /* FLM horizontal End Register (R/W) */
-#define VR4181_PWRCONREG1       __preg16(KSEG1 + 0x0A000430)    /* Power Control register 1 (R/W) */
-#define VR4181_PWRCONREG2       __preg16(KSEG1 + 0x0A000432)    /* Power Control register 2 (R/W) */
-#define VR4181_LCDIMSKREG       __preg16(KSEG1 + 0x0A000434)    /* LCD Interrupt Mask register (R/W) */
-#define VR4181_CPINDCTREG       __preg16(KSEG1 + 0x0A00047E)    /* Color palette Index and control Register (R/W) */
-#define VR4181_CPALDATREG       __preg32(KSEG1 + 0x0A000480)    /* Color palette data register (32bits Register) (R/W) */
-
-// physical address spaces
-#define VR4181_LCD             0x0a000000
-#define VR4181_INTERNAL_IO_2   0x0b000000
-#define VR4181_INTERNAL_IO_1   0x0c000000
-#define VR4181_ISA_MEM         0x10000000
-#define VR4181_ISA_IO          0x14000000
-#define VR4181_ROM             0x18000000
-
-// This is the base address for IO port decoding to which the 16 bit IO port address
-// is added.  Defining it to 0 will usually cause a kernel oops any time port IO is
-// attempted, which can be handy for turning up parts of the kernel that make
-// incorrect architecture assumptions (by assuming that everything acts like a PC),
-// but we need it correctly defined to use the PCMCIA/CF controller:
-#define VR4181_PORT_BASE        (KSEG1 + VR4181_ISA_IO)
-#define VR4181_ISAMEM_BASE      (KSEG1 + VR4181_ISA_MEM)
-
-#endif /* __ASM_VR4181_VR4181_H */
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
index 7d41e44463f9..bd2723c30901 100644
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ b/include/asm-mips/vr41xx/vr41xx.h
@@ -7,7 +7,7 @@
  * Copyright (C) 2001, 2002 Paul Mundt
  * Copyright (C) 2002 MontaVista Software, Inc.
  * Copyright (C) 2002 TimeSys Corp.
- * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
+ * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -79,11 +79,11 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
 #define MIPS_CPU_IRQ(x)         (MIPS_CPU_IRQ_BASE + (x))
 #define MIPS_SOFTINT0_IRQ       MIPS_CPU_IRQ(0)
 #define MIPS_SOFTINT1_IRQ       MIPS_CPU_IRQ(1)
-#define INT0_CASCADE_IRQ        MIPS_CPU_IRQ(2)
-#define INT1_CASCADE_IRQ        MIPS_CPU_IRQ(3)
-#define INT2_CASCADE_IRQ        MIPS_CPU_IRQ(4)
-#define INT3_CASCADE_IRQ        MIPS_CPU_IRQ(5)
-#define INT4_CASCADE_IRQ        MIPS_CPU_IRQ(6)
+#define INT0_IRQ                MIPS_CPU_IRQ(2)
+#define INT1_IRQ                MIPS_CPU_IRQ(3)
+#define INT2_IRQ                MIPS_CPU_IRQ(4)
+#define INT3_IRQ                MIPS_CPU_IRQ(5)
+#define INT4_IRQ                MIPS_CPU_IRQ(6)
 #define TIMER_IRQ               MIPS_CPU_IRQ(7)
 
 /* SYINT1 Interrupt Numbers */
@@ -97,7 +97,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
 #define PIU_IRQ                 SYSINT1_IRQ(5)
 #define AIU_IRQ                 SYSINT1_IRQ(6)
 #define KIU_IRQ                 SYSINT1_IRQ(7)
-#define GIUINT_CASCADE_IRQ      SYSINT1_IRQ(8)
+#define GIUINT_IRQ              SYSINT1_IRQ(8)
 #define SIU_IRQ                 SYSINT1_IRQ(9)
 #define BUSERR_IRQ              SYSINT1_IRQ(10)
 #define SOFTINT_IRQ             SYSINT1_IRQ(11)
@@ -128,7 +128,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
 #define GIU_IRQ_LAST            GIU_IRQ(31)
 
 extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
-extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq));
+extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *));
 
 #define PIUINT_COMMAND          0x0040
 #define PIUINT_DATA             0x0020
diff --git a/include/asm-mips/vr41xx/vrc4173.h b/include/asm-mips/vr41xx/vrc4173.h
index 58e193c51b45..bb7a85c186e4 100644
--- a/include/asm-mips/vr41xx/vrc4173.h
+++ b/include/asm-mips/vr41xx/vrc4173.h
@@ -21,8 +21,8 @@
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#ifndef __NEC_VRC4173_H 
-#define __NEC_VRC4173_H 
+#ifndef __NEC_VRC4173_H
+#define __NEC_VRC4173_H
 
 #include <linux/config.h>
 #include <asm/io.h>
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index c4a704121343..04ee53b34c2e 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -113,7 +113,7 @@
  */
 #define BCM1250_M3_WAR 1
 
-/* 
+/*
  * This is a DUART workaround related to glitches around register accesses
  */
 #define SIBYTE_1956_WAR 1
@@ -122,7 +122,7 @@
 
 /*
  * Fill buffers not flushed on CACHE instructions
- * 
+ *
  * Hit_Invalidate_I cacheops invalidate an icache line but the refill
  * for that line can get stale data from the fill buffer instead of
  * accessing memory if the previous icache miss was also to that line.
diff --git a/include/asm-mips/xxs1500.h b/include/asm-mips/xxs1500.h
index 75c0ddfeca13..4d84a90b0f20 100644
--- a/include/asm-mips/xxs1500.h
+++ b/include/asm-mips/xxs1500.h
@@ -22,7 +22,7 @@
  *
  * ########################################################################
  *
- * 
+ *
  */
 #ifndef __ASM_XXS1500_H
 #define __ASM_XXS1500_H