diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2007-02-20 14:13:30 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-20 14:13:30 -0500 |
commit | 5a84d159061d914c8dd4aa372ac6e9529c2be453 (patch) | |
tree | 9b08af78085334af44414adafe0096276f8fe0ff /include/asm-mips | |
parent | e80a0e6e7ccdf64575d4384cb4172860422f5b81 (diff) | |
parent | 7d477a04a619e90ee08724e8f2d8803c6bdfcef8 (diff) |
Merge ARM fixes
Diffstat (limited to 'include/asm-mips')
56 files changed, 813 insertions, 395 deletions
diff --git a/include/asm-mips/abi.h b/include/asm-mips/abi.h index 1ce0518ace2e..1dd74fbdc09b 100644 --- a/include/asm-mips/abi.h +++ b/include/asm-mips/abi.h | |||
@@ -13,13 +13,13 @@ | |||
13 | #include <asm/siginfo.h> | 13 | #include <asm/siginfo.h> |
14 | 14 | ||
15 | struct mips_abi { | 15 | struct mips_abi { |
16 | void (* const do_signal)(struct pt_regs *regs); | ||
17 | int (* const setup_frame)(struct k_sigaction * ka, | 16 | int (* const setup_frame)(struct k_sigaction * ka, |
18 | struct pt_regs *regs, int signr, | 17 | struct pt_regs *regs, int signr, |
19 | sigset_t *set); | 18 | sigset_t *set); |
20 | int (* const setup_rt_frame)(struct k_sigaction * ka, | 19 | int (* const setup_rt_frame)(struct k_sigaction * ka, |
21 | struct pt_regs *regs, int signr, | 20 | struct pt_regs *regs, int signr, |
22 | sigset_t *set, siginfo_t *info); | 21 | sigset_t *set, siginfo_t *info); |
22 | const unsigned long restart; | ||
23 | }; | 23 | }; |
24 | 24 | ||
25 | #endif /* _ASM_ABI_H */ | 25 | #endif /* _ASM_ABI_H */ |
diff --git a/include/asm-mips/apm.h b/include/asm-mips/apm.h deleted file mode 100644 index 4b99ffc11529..000000000000 --- a/include/asm-mips/apm.h +++ /dev/null | |||
@@ -1,64 +0,0 @@ | |||
1 | /* -*- linux-c -*- | ||
2 | * | ||
3 | * (C) 2003 zecke@handhelds.org | ||
4 | * | ||
5 | * GPL version 2 | ||
6 | * | ||
7 | * based on arch/arm/kernel/apm.c | ||
8 | * factor out the information needed by architectures to provide | ||
9 | * apm status | ||
10 | * | ||
11 | * | ||
12 | */ | ||
13 | #ifndef MIPS_ASM_SA1100_APM_H | ||
14 | #define MIPS_ASM_SA1100_APM_H | ||
15 | |||
16 | #include <linux/apm_bios.h> | ||
17 | |||
18 | /* | ||
19 | * This structure gets filled in by the machine specific 'get_power_status' | ||
20 | * implementation. Any fields which are not set default to a safe value. | ||
21 | */ | ||
22 | struct apm_power_info { | ||
23 | unsigned char ac_line_status; | ||
24 | #define APM_AC_OFFLINE 0 | ||
25 | #define APM_AC_ONLINE 1 | ||
26 | #define APM_AC_BACKUP 2 | ||
27 | #define APM_AC_UNKNOWN 0xff | ||
28 | |||
29 | unsigned char battery_status; | ||
30 | #define APM_BATTERY_STATUS_HIGH 0 | ||
31 | #define APM_BATTERY_STATUS_LOW 1 | ||
32 | #define APM_BATTERY_STATUS_CRITICAL 2 | ||
33 | #define APM_BATTERY_STATUS_CHARGING 3 | ||
34 | #define APM_BATTERY_STATUS_NOT_PRESENT 4 | ||
35 | #define APM_BATTERY_STATUS_UNKNOWN 0xff | ||
36 | |||
37 | unsigned char battery_flag; | ||
38 | #define APM_BATTERY_FLAG_HIGH (1 << 0) | ||
39 | #define APM_BATTERY_FLAG_LOW (1 << 1) | ||
40 | #define APM_BATTERY_FLAG_CRITICAL (1 << 2) | ||
41 | #define APM_BATTERY_FLAG_CHARGING (1 << 3) | ||
42 | #define APM_BATTERY_FLAG_NOT_PRESENT (1 << 7) | ||
43 | #define APM_BATTERY_FLAG_UNKNOWN 0xff | ||
44 | |||
45 | int battery_life; | ||
46 | int time; | ||
47 | int units; | ||
48 | #define APM_UNITS_MINS 0 | ||
49 | #define APM_UNITS_SECS 1 | ||
50 | #define APM_UNITS_UNKNOWN -1 | ||
51 | |||
52 | }; | ||
53 | |||
54 | /* | ||
55 | * This allows machines to provide their own "apm get power status" function. | ||
56 | */ | ||
57 | extern void (*apm_get_power_status)(struct apm_power_info *); | ||
58 | |||
59 | /* | ||
60 | * Queue an event (APM_SYS_SUSPEND or APM_CRITICAL_SUSPEND) | ||
61 | */ | ||
62 | void apm_queue_event(apm_event_t event); | ||
63 | |||
64 | #endif | ||
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h index c1a2409bb52a..8578869a8bcf 100644 --- a/include/asm-mips/atomic.h +++ b/include/asm-mips/atomic.h | |||
@@ -69,7 +69,10 @@ static __inline__ void atomic_add(int i, atomic_t * v) | |||
69 | "1: ll %0, %1 # atomic_add \n" | 69 | "1: ll %0, %1 # atomic_add \n" |
70 | " addu %0, %2 \n" | 70 | " addu %0, %2 \n" |
71 | " sc %0, %1 \n" | 71 | " sc %0, %1 \n" |
72 | " beqz %0, 1b \n" | 72 | " beqz %0, 2f \n" |
73 | " .subsection 2 \n" | ||
74 | "2: b 1b \n" | ||
75 | " .previous \n" | ||
73 | " .set mips0 \n" | 76 | " .set mips0 \n" |
74 | : "=&r" (temp), "=m" (v->counter) | 77 | : "=&r" (temp), "=m" (v->counter) |
75 | : "Ir" (i), "m" (v->counter)); | 78 | : "Ir" (i), "m" (v->counter)); |
@@ -111,7 +114,10 @@ static __inline__ void atomic_sub(int i, atomic_t * v) | |||
111 | "1: ll %0, %1 # atomic_sub \n" | 114 | "1: ll %0, %1 # atomic_sub \n" |
112 | " subu %0, %2 \n" | 115 | " subu %0, %2 \n" |
113 | " sc %0, %1 \n" | 116 | " sc %0, %1 \n" |
114 | " beqz %0, 1b \n" | 117 | " beqz %0, 2f \n" |
118 | " .subsection 2 \n" | ||
119 | "2: b 1b \n" | ||
120 | " .previous \n" | ||
115 | " .set mips0 \n" | 121 | " .set mips0 \n" |
116 | : "=&r" (temp), "=m" (v->counter) | 122 | : "=&r" (temp), "=m" (v->counter) |
117 | : "Ir" (i), "m" (v->counter)); | 123 | : "Ir" (i), "m" (v->counter)); |
@@ -155,8 +161,11 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) | |||
155 | "1: ll %1, %2 # atomic_add_return \n" | 161 | "1: ll %1, %2 # atomic_add_return \n" |
156 | " addu %0, %1, %3 \n" | 162 | " addu %0, %1, %3 \n" |
157 | " sc %0, %2 \n" | 163 | " sc %0, %2 \n" |
158 | " beqz %0, 1b \n" | 164 | " beqz %0, 2f \n" |
159 | " addu %0, %1, %3 \n" | 165 | " addu %0, %1, %3 \n" |
166 | " .subsection 2 \n" | ||
167 | "2: b 1b \n" | ||
168 | " .previous \n" | ||
160 | " .set mips0 \n" | 169 | " .set mips0 \n" |
161 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) | 170 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) |
162 | : "Ir" (i), "m" (v->counter) | 171 | : "Ir" (i), "m" (v->counter) |
@@ -204,8 +213,11 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) | |||
204 | "1: ll %1, %2 # atomic_sub_return \n" | 213 | "1: ll %1, %2 # atomic_sub_return \n" |
205 | " subu %0, %1, %3 \n" | 214 | " subu %0, %1, %3 \n" |
206 | " sc %0, %2 \n" | 215 | " sc %0, %2 \n" |
207 | " beqz %0, 1b \n" | 216 | " beqz %0, 2f \n" |
208 | " subu %0, %1, %3 \n" | 217 | " subu %0, %1, %3 \n" |
218 | " .subsection 2 \n" | ||
219 | "2: b 1b \n" | ||
220 | " .previous \n" | ||
209 | " .set mips0 \n" | 221 | " .set mips0 \n" |
210 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) | 222 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) |
211 | : "Ir" (i), "m" (v->counter) | 223 | : "Ir" (i), "m" (v->counter) |
@@ -267,10 +279,13 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) | |||
267 | " bltz %0, 1f \n" | 279 | " bltz %0, 1f \n" |
268 | " sc %0, %2 \n" | 280 | " sc %0, %2 \n" |
269 | " .set noreorder \n" | 281 | " .set noreorder \n" |
270 | " beqz %0, 1b \n" | 282 | " beqz %0, 2f \n" |
271 | " subu %0, %1, %3 \n" | 283 | " subu %0, %1, %3 \n" |
272 | " .set reorder \n" | 284 | " .set reorder \n" |
273 | "1: \n" | 285 | "1: \n" |
286 | " .subsection 2 \n" | ||
287 | "2: b 1b \n" | ||
288 | " .previous \n" | ||
274 | " .set mips0 \n" | 289 | " .set mips0 \n" |
275 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) | 290 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) |
276 | : "Ir" (i), "m" (v->counter) | 291 | : "Ir" (i), "m" (v->counter) |
@@ -429,7 +444,10 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) | |||
429 | "1: lld %0, %1 # atomic64_add \n" | 444 | "1: lld %0, %1 # atomic64_add \n" |
430 | " addu %0, %2 \n" | 445 | " addu %0, %2 \n" |
431 | " scd %0, %1 \n" | 446 | " scd %0, %1 \n" |
432 | " beqz %0, 1b \n" | 447 | " beqz %0, 2f \n" |
448 | " .subsection 2 \n" | ||
449 | "2: b 1b \n" | ||
450 | " .previous \n" | ||
433 | " .set mips0 \n" | 451 | " .set mips0 \n" |
434 | : "=&r" (temp), "=m" (v->counter) | 452 | : "=&r" (temp), "=m" (v->counter) |
435 | : "Ir" (i), "m" (v->counter)); | 453 | : "Ir" (i), "m" (v->counter)); |
@@ -471,7 +489,10 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) | |||
471 | "1: lld %0, %1 # atomic64_sub \n" | 489 | "1: lld %0, %1 # atomic64_sub \n" |
472 | " subu %0, %2 \n" | 490 | " subu %0, %2 \n" |
473 | " scd %0, %1 \n" | 491 | " scd %0, %1 \n" |
474 | " beqz %0, 1b \n" | 492 | " beqz %0, 2f \n" |
493 | " .subsection 2 \n" | ||
494 | "2: b 1b \n" | ||
495 | " .previous \n" | ||
475 | " .set mips0 \n" | 496 | " .set mips0 \n" |
476 | : "=&r" (temp), "=m" (v->counter) | 497 | : "=&r" (temp), "=m" (v->counter) |
477 | : "Ir" (i), "m" (v->counter)); | 498 | : "Ir" (i), "m" (v->counter)); |
@@ -515,8 +536,11 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) | |||
515 | "1: lld %1, %2 # atomic64_add_return \n" | 536 | "1: lld %1, %2 # atomic64_add_return \n" |
516 | " addu %0, %1, %3 \n" | 537 | " addu %0, %1, %3 \n" |
517 | " scd %0, %2 \n" | 538 | " scd %0, %2 \n" |
518 | " beqz %0, 1b \n" | 539 | " beqz %0, 2f \n" |
519 | " addu %0, %1, %3 \n" | 540 | " addu %0, %1, %3 \n" |
541 | " .subsection 2 \n" | ||
542 | "2: b 1b \n" | ||
543 | " .previous \n" | ||
520 | " .set mips0 \n" | 544 | " .set mips0 \n" |
521 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) | 545 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) |
522 | : "Ir" (i), "m" (v->counter) | 546 | : "Ir" (i), "m" (v->counter) |
@@ -564,8 +588,11 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) | |||
564 | "1: lld %1, %2 # atomic64_sub_return \n" | 588 | "1: lld %1, %2 # atomic64_sub_return \n" |
565 | " subu %0, %1, %3 \n" | 589 | " subu %0, %1, %3 \n" |
566 | " scd %0, %2 \n" | 590 | " scd %0, %2 \n" |
567 | " beqz %0, 1b \n" | 591 | " beqz %0, 2f \n" |
568 | " subu %0, %1, %3 \n" | 592 | " subu %0, %1, %3 \n" |
593 | " .subsection 2 \n" | ||
594 | "2: b 1b \n" | ||
595 | " .previous \n" | ||
569 | " .set mips0 \n" | 596 | " .set mips0 \n" |
570 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) | 597 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) |
571 | : "Ir" (i), "m" (v->counter) | 598 | : "Ir" (i), "m" (v->counter) |
@@ -627,10 +654,13 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) | |||
627 | " bltz %0, 1f \n" | 654 | " bltz %0, 1f \n" |
628 | " scd %0, %2 \n" | 655 | " scd %0, %2 \n" |
629 | " .set noreorder \n" | 656 | " .set noreorder \n" |
630 | " beqz %0, 1b \n" | 657 | " beqz %0, 2f \n" |
631 | " dsubu %0, %1, %3 \n" | 658 | " dsubu %0, %1, %3 \n" |
632 | " .set reorder \n" | 659 | " .set reorder \n" |
633 | "1: \n" | 660 | "1: \n" |
661 | " .subsection 2 \n" | ||
662 | "2: b 1b \n" | ||
663 | " .previous \n" | ||
634 | " .set mips0 \n" | 664 | " .set mips0 \n" |
635 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) | 665 | : "=&r" (result), "=&r" (temp), "=m" (v->counter) |
636 | : "Ir" (i), "m" (v->counter) | 666 | : "Ir" (i), "m" (v->counter) |
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 06445de1324b..89436b96ad66 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (c) 1994 - 1997, 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org) | 6 | * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org) |
7 | * Copyright (c) 1999, 2000 Silicon Graphics, Inc. | 7 | * Copyright (c) 1999, 2000 Silicon Graphics, Inc. |
8 | */ | 8 | */ |
9 | #ifndef _ASM_BITOPS_H | 9 | #ifndef _ASM_BITOPS_H |
@@ -24,11 +24,15 @@ | |||
24 | #define SZLONG_MASK 31UL | 24 | #define SZLONG_MASK 31UL |
25 | #define __LL "ll " | 25 | #define __LL "ll " |
26 | #define __SC "sc " | 26 | #define __SC "sc " |
27 | #define __INS "ins " | ||
28 | #define __EXT "ext " | ||
27 | #elif (_MIPS_SZLONG == 64) | 29 | #elif (_MIPS_SZLONG == 64) |
28 | #define SZLONG_LOG 6 | 30 | #define SZLONG_LOG 6 |
29 | #define SZLONG_MASK 63UL | 31 | #define SZLONG_MASK 63UL |
30 | #define __LL "lld " | 32 | #define __LL "lld " |
31 | #define __SC "scd " | 33 | #define __SC "scd " |
34 | #define __INS "dins " | ||
35 | #define __EXT "dext " | ||
32 | #endif | 36 | #endif |
33 | 37 | ||
34 | /* | 38 | /* |
@@ -62,13 +66,29 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) | |||
62 | " .set mips0 \n" | 66 | " .set mips0 \n" |
63 | : "=&r" (temp), "=m" (*m) | 67 | : "=&r" (temp), "=m" (*m) |
64 | : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); | 68 | : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); |
69 | #ifdef CONFIG_CPU_MIPSR2 | ||
70 | } else if (__builtin_constant_p(nr)) { | ||
71 | __asm__ __volatile__( | ||
72 | "1: " __LL "%0, %1 # set_bit \n" | ||
73 | " " __INS "%0, %4, %2, 1 \n" | ||
74 | " " __SC "%0, %1 \n" | ||
75 | " beqz %0, 2f \n" | ||
76 | " .subsection 2 \n" | ||
77 | "2: b 1b \n" | ||
78 | " .previous \n" | ||
79 | : "=&r" (temp), "=m" (*m) | ||
80 | : "ir" (nr & SZLONG_MASK), "m" (*m), "r" (~0)); | ||
81 | #endif /* CONFIG_CPU_MIPSR2 */ | ||
65 | } else if (cpu_has_llsc) { | 82 | } else if (cpu_has_llsc) { |
66 | __asm__ __volatile__( | 83 | __asm__ __volatile__( |
67 | " .set mips3 \n" | 84 | " .set mips3 \n" |
68 | "1: " __LL "%0, %1 # set_bit \n" | 85 | "1: " __LL "%0, %1 # set_bit \n" |
69 | " or %0, %2 \n" | 86 | " or %0, %2 \n" |
70 | " " __SC "%0, %1 \n" | 87 | " " __SC "%0, %1 \n" |
71 | " beqz %0, 1b \n" | 88 | " beqz %0, 2f \n" |
89 | " .subsection 2 \n" | ||
90 | "2: b 1b \n" | ||
91 | " .previous \n" | ||
72 | " .set mips0 \n" | 92 | " .set mips0 \n" |
73 | : "=&r" (temp), "=m" (*m) | 93 | : "=&r" (temp), "=m" (*m) |
74 | : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); | 94 | : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); |
@@ -110,13 +130,29 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) | |||
110 | " .set mips0 \n" | 130 | " .set mips0 \n" |
111 | : "=&r" (temp), "=m" (*m) | 131 | : "=&r" (temp), "=m" (*m) |
112 | : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); | 132 | : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); |
133 | #ifdef CONFIG_CPU_MIPSR2 | ||
134 | } else if (__builtin_constant_p(nr)) { | ||
135 | __asm__ __volatile__( | ||
136 | "1: " __LL "%0, %1 # clear_bit \n" | ||
137 | " " __INS "%0, $0, %2, 1 \n" | ||
138 | " " __SC "%0, %1 \n" | ||
139 | " beqz %0, 2f \n" | ||
140 | " .subsection 2 \n" | ||
141 | "2: b 1b \n" | ||
142 | " .previous \n" | ||
143 | : "=&r" (temp), "=m" (*m) | ||
144 | : "ir" (nr & SZLONG_MASK), "m" (*m)); | ||
145 | #endif /* CONFIG_CPU_MIPSR2 */ | ||
113 | } else if (cpu_has_llsc) { | 146 | } else if (cpu_has_llsc) { |
114 | __asm__ __volatile__( | 147 | __asm__ __volatile__( |
115 | " .set mips3 \n" | 148 | " .set mips3 \n" |
116 | "1: " __LL "%0, %1 # clear_bit \n" | 149 | "1: " __LL "%0, %1 # clear_bit \n" |
117 | " and %0, %2 \n" | 150 | " and %0, %2 \n" |
118 | " " __SC "%0, %1 \n" | 151 | " " __SC "%0, %1 \n" |
119 | " beqz %0, 1b \n" | 152 | " beqz %0, 2f \n" |
153 | " .subsection 2 \n" | ||
154 | "2: b 1b \n" | ||
155 | " .previous \n" | ||
120 | " .set mips0 \n" | 156 | " .set mips0 \n" |
121 | : "=&r" (temp), "=m" (*m) | 157 | : "=&r" (temp), "=m" (*m) |
122 | : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); | 158 | : "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m)); |
@@ -166,7 +202,10 @@ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) | |||
166 | "1: " __LL "%0, %1 # change_bit \n" | 202 | "1: " __LL "%0, %1 # change_bit \n" |
167 | " xor %0, %2 \n" | 203 | " xor %0, %2 \n" |
168 | " " __SC "%0, %1 \n" | 204 | " " __SC "%0, %1 \n" |
169 | " beqz %0, 1b \n" | 205 | " beqz %0, 2f \n" |
206 | " .subsection 2 \n" | ||
207 | "2: b 1b \n" | ||
208 | " .previous \n" | ||
170 | " .set mips0 \n" | 209 | " .set mips0 \n" |
171 | : "=&r" (temp), "=m" (*m) | 210 | : "=&r" (temp), "=m" (*m) |
172 | : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); | 211 | : "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m)); |
@@ -222,8 +261,12 @@ static inline int test_and_set_bit(unsigned long nr, | |||
222 | "1: " __LL "%0, %1 # test_and_set_bit \n" | 261 | "1: " __LL "%0, %1 # test_and_set_bit \n" |
223 | " or %2, %0, %3 \n" | 262 | " or %2, %0, %3 \n" |
224 | " " __SC "%2, %1 \n" | 263 | " " __SC "%2, %1 \n" |
225 | " beqz %2, 1b \n" | 264 | " beqz %2, 2f \n" |
226 | " and %2, %0, %3 \n" | 265 | " and %2, %0, %3 \n" |
266 | " .subsection 2 \n" | ||
267 | "2: b 1b \n" | ||
268 | " nop \n" | ||
269 | " .previous \n" | ||
227 | " .set pop \n" | 270 | " .set pop \n" |
228 | : "=&r" (temp), "=m" (*m), "=&r" (res) | 271 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
229 | : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) | 272 | : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) |
@@ -278,6 +321,26 @@ static inline int test_and_clear_bit(unsigned long nr, | |||
278 | : "memory"); | 321 | : "memory"); |
279 | 322 | ||
280 | return res != 0; | 323 | return res != 0; |
324 | #ifdef CONFIG_CPU_MIPSR2 | ||
325 | } else if (__builtin_constant_p(nr)) { | ||
326 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | ||
327 | unsigned long temp, res; | ||
328 | |||
329 | __asm__ __volatile__( | ||
330 | "1: " __LL "%0, %1 # test_and_clear_bit \n" | ||
331 | " " __EXT "%2, %0, %3, 1 \n" | ||
332 | " " __INS "%0, $0, %3, 1 \n" | ||
333 | " " __SC "%0, %1 \n" | ||
334 | " beqz %0, 2f \n" | ||
335 | " .subsection 2 \n" | ||
336 | "2: b 1b \n" | ||
337 | " .previous \n" | ||
338 | : "=&r" (temp), "=m" (*m), "=&r" (res) | ||
339 | : "ri" (nr & SZLONG_MASK), "m" (*m) | ||
340 | : "memory"); | ||
341 | |||
342 | return res; | ||
343 | #endif | ||
281 | } else if (cpu_has_llsc) { | 344 | } else if (cpu_has_llsc) { |
282 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); | 345 | unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); |
283 | unsigned long temp, res; | 346 | unsigned long temp, res; |
@@ -290,8 +353,12 @@ static inline int test_and_clear_bit(unsigned long nr, | |||
290 | " or %2, %0, %3 \n" | 353 | " or %2, %0, %3 \n" |
291 | " xor %2, %3 \n" | 354 | " xor %2, %3 \n" |
292 | " " __SC "%2, %1 \n" | 355 | " " __SC "%2, %1 \n" |
293 | " beqz %2, 1b \n" | 356 | " beqz %2, 2f \n" |
294 | " and %2, %0, %3 \n" | 357 | " and %2, %0, %3 \n" |
358 | " .subsection 2 \n" | ||
359 | "2: b 1b \n" | ||
360 | " nop \n" | ||
361 | " .previous \n" | ||
295 | " .set pop \n" | 362 | " .set pop \n" |
296 | : "=&r" (temp), "=m" (*m), "=&r" (res) | 363 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
297 | : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) | 364 | : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) |
@@ -356,8 +423,12 @@ static inline int test_and_change_bit(unsigned long nr, | |||
356 | "1: " __LL "%0, %1 # test_and_change_bit \n" | 423 | "1: " __LL "%0, %1 # test_and_change_bit \n" |
357 | " xor %2, %0, %3 \n" | 424 | " xor %2, %0, %3 \n" |
358 | " " __SC "\t%2, %1 \n" | 425 | " " __SC "\t%2, %1 \n" |
359 | " beqz %2, 1b \n" | 426 | " beqz %2, 2f \n" |
360 | " and %2, %0, %3 \n" | 427 | " and %2, %0, %3 \n" |
428 | " .subsection 2 \n" | ||
429 | "2: b 1b \n" | ||
430 | " nop \n" | ||
431 | " .previous \n" | ||
361 | " .set pop \n" | 432 | " .set pop \n" |
362 | : "=&r" (temp), "=m" (*m), "=&r" (res) | 433 | : "=&r" (temp), "=m" (*m), "=&r" (res) |
363 | : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) | 434 | : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m) |
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h index 8e321f53a382..c7c945baf1ee 100644 --- a/include/asm-mips/bootinfo.h +++ b/include/asm-mips/bootinfo.h | |||
@@ -243,6 +243,10 @@ extern struct boot_mem_map boot_mem_map; | |||
243 | extern void add_memory_region(phys_t start, phys_t size, long type); | 243 | extern void add_memory_region(phys_t start, phys_t size, long type); |
244 | 244 | ||
245 | extern void prom_init(void); | 245 | extern void prom_init(void); |
246 | extern void prom_free_prom_memory(void); | ||
247 | |||
248 | extern void free_init_pages(const char *what, | ||
249 | unsigned long begin, unsigned long end); | ||
246 | 250 | ||
247 | /* | 251 | /* |
248 | * Initial kernel command line, usually setup by prom_init() | 252 | * Initial kernel command line, usually setup by prom_init() |
diff --git a/include/asm-mips/compat-signal.h b/include/asm-mips/compat-signal.h new file mode 100644 index 000000000000..6599a901b63e --- /dev/null +++ b/include/asm-mips/compat-signal.h | |||
@@ -0,0 +1,57 @@ | |||
1 | #ifndef __ASM_COMPAT_SIGNAL_H | ||
2 | #define __ASM_COMPAT_SIGNAL_H | ||
3 | |||
4 | #include <linux/bug.h> | ||
5 | #include <linux/compat.h> | ||
6 | #include <linux/compiler.h> | ||
7 | |||
8 | #include <asm/signal.h> | ||
9 | #include <asm/siginfo.h> | ||
10 | |||
11 | #include <asm/uaccess.h> | ||
12 | |||
13 | static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d, | ||
14 | const sigset_t *s) | ||
15 | { | ||
16 | int err; | ||
17 | |||
18 | BUG_ON(sizeof(*d) != sizeof(*s)); | ||
19 | BUG_ON(_NSIG_WORDS != 2); | ||
20 | |||
21 | err = __put_user(s->sig[0], &d->sig[0]); | ||
22 | err |= __put_user(s->sig[0] >> 32, &d->sig[1]); | ||
23 | err |= __put_user(s->sig[1], &d->sig[2]); | ||
24 | err |= __put_user(s->sig[1] >> 32, &d->sig[3]); | ||
25 | |||
26 | return err; | ||
27 | } | ||
28 | |||
29 | static inline int __copy_conv_sigset_from_user(sigset_t *d, | ||
30 | const compat_sigset_t __user *s) | ||
31 | { | ||
32 | int err; | ||
33 | union sigset_u { | ||
34 | sigset_t s; | ||
35 | compat_sigset_t c; | ||
36 | } *u = (union sigset_u *) d; | ||
37 | |||
38 | BUG_ON(sizeof(*d) != sizeof(*s)); | ||
39 | BUG_ON(_NSIG_WORDS != 2); | ||
40 | |||
41 | #ifdef CONFIG_CPU_BIG_ENDIAN | ||
42 | err = __get_user(u->c.sig[1], &s->sig[0]); | ||
43 | err |= __get_user(u->c.sig[0], &s->sig[1]); | ||
44 | err |= __get_user(u->c.sig[3], &s->sig[2]); | ||
45 | err |= __get_user(u->c.sig[2], &s->sig[3]); | ||
46 | #endif | ||
47 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | ||
48 | err = __get_user(u->c.sig[0], &s->sig[0]); | ||
49 | err |= __get_user(u->c.sig[1], &s->sig[1]); | ||
50 | err |= __get_user(u->c.sig[2], &s->sig[2]); | ||
51 | err |= __get_user(u->c.sig[3], &s->sig[3]); | ||
52 | #endif | ||
53 | |||
54 | return err; | ||
55 | } | ||
56 | |||
57 | #endif /* __ASM_COMPAT_SIGNAL_H */ | ||
diff --git a/include/asm-mips/ddb5xxx/ddb5477.h b/include/asm-mips/ddb5xxx/ddb5477.h index c5af4b73fdd7..6cf177caf6d5 100644 --- a/include/asm-mips/ddb5xxx/ddb5477.h +++ b/include/asm-mips/ddb5xxx/ddb5477.h | |||
@@ -17,6 +17,7 @@ | |||
17 | #ifndef __ASM_DDB5XXX_DDB5477_H | 17 | #ifndef __ASM_DDB5XXX_DDB5477_H |
18 | #define __ASM_DDB5XXX_DDB5477_H | 18 | #define __ASM_DDB5XXX_DDB5477_H |
19 | 19 | ||
20 | #include <irq.h> | ||
20 | 21 | ||
21 | /* | 22 | /* |
22 | * This contains macros that are specific to DDB5477 or renamed from | 23 | * This contains macros that are specific to DDB5477 or renamed from |
@@ -251,14 +252,10 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); | |||
251 | */ | 252 | */ |
252 | 253 | ||
253 | #define NUM_CPU_IRQ 8 | 254 | #define NUM_CPU_IRQ 8 |
254 | #define NUM_I8259_IRQ 16 | ||
255 | #define NUM_VRC5477_IRQ 32 | 255 | #define NUM_VRC5477_IRQ 32 |
256 | 256 | ||
257 | #define DDB_IRQ_BASE 0 | 257 | #define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE |
258 | 258 | #define VRC5477_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) | |
259 | #define I8259_IRQ_BASE DDB_IRQ_BASE | ||
260 | #define VRC5477_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ) | ||
261 | #define CPU_IRQ_BASE (VRC5477_IRQ_BASE + NUM_VRC5477_IRQ) | ||
262 | 259 | ||
263 | /* | 260 | /* |
264 | * vrc5477 irq defs | 261 | * vrc5477 irq defs |
@@ -300,22 +297,22 @@ extern void ll_vrc5477_irq_disable(int vrc5477_irq); | |||
300 | /* | 297 | /* |
301 | * i2859 irq assignment | 298 | * i2859 irq assignment |
302 | */ | 299 | */ |
303 | #define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE) | 300 | #define I8259_IRQ_RESERVED_0 (0 + I8259A_IRQ_BASE) |
304 | #define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */ | 301 | #define I8259_IRQ_KEYBOARD (1 + I8259A_IRQ_BASE) /* M1543 default */ |
305 | #define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE) | 302 | #define I8259_IRQ_CASCADE (2 + I8259A_IRQ_BASE) |
306 | #define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ | 303 | #define I8259_IRQ_UART_B (3 + I8259A_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */ |
307 | #define I8259_IRQ_UART_A (4 + I8259_IRQ_BASE) /* M1543 default */ | 304 | #define I8259_IRQ_UART_A (4 + I8259A_IRQ_BASE) /* M1543 default */ |
308 | #define I8259_IRQ_PARALLEL (5 + I8259_IRQ_BASE) /* M1543 default */ | 305 | #define I8259_IRQ_PARALLEL (5 + I8259A_IRQ_BASE) /* M1543 default */ |
309 | #define I8259_IRQ_RESERVED_6 (6 + I8259_IRQ_BASE) | 306 | #define I8259_IRQ_RESERVED_6 (6 + I8259A_IRQ_BASE) |
310 | #define I8259_IRQ_RESERVED_7 (7 + I8259_IRQ_BASE) | 307 | #define I8259_IRQ_RESERVED_7 (7 + I8259A_IRQ_BASE) |
311 | #define I8259_IRQ_RTC (8 + I8259_IRQ_BASE) /* who set this? */ | 308 | #define I8259_IRQ_RTC (8 + I8259A_IRQ_BASE) /* who set this? */ |
312 | #define I8259_IRQ_USB (9 + I8259_IRQ_BASE) /* ddb_setup */ | 309 | #define I8259_IRQ_USB (9 + I8259A_IRQ_BASE) /* ddb_setup */ |
313 | #define I8259_IRQ_PMU (10 + I8259_IRQ_BASE) /* ddb_setup */ | 310 | #define I8259_IRQ_PMU (10 + I8259A_IRQ_BASE) /* ddb_setup */ |
314 | #define I8259_IRQ_RESERVED_11 (11 + I8259_IRQ_BASE) | 311 | #define I8259_IRQ_RESERVED_11 (11 + I8259A_IRQ_BASE) |
315 | #define I8259_IRQ_RESERVED_12 (12 + I8259_IRQ_BASE) /* m1543_irq_setup */ | 312 | #define I8259_IRQ_RESERVED_12 (12 + I8259A_IRQ_BASE) /* m1543_irq_setup */ |
316 | #define I8259_IRQ_RESERVED_13 (13 + I8259_IRQ_BASE) | 313 | #define I8259_IRQ_RESERVED_13 (13 + I8259A_IRQ_BASE) |
317 | #define I8259_IRQ_HDC1 (14 + I8259_IRQ_BASE) /* default and ddb_setup */ | 314 | #define I8259_IRQ_HDC1 (14 + I8259A_IRQ_BASE) /* default and ddb_setup */ |
318 | #define I8259_IRQ_HDC2 (15 + I8259_IRQ_BASE) /* default */ | 315 | #define I8259_IRQ_HDC2 (15 + I8259A_IRQ_BASE) /* default */ |
319 | 316 | ||
320 | 317 | ||
321 | /* | 318 | /* |
diff --git a/include/asm-mips/dec/interrupts.h b/include/asm-mips/dec/interrupts.h index 273e4d65bfe6..e10d341067c8 100644 --- a/include/asm-mips/dec/interrupts.h +++ b/include/asm-mips/dec/interrupts.h | |||
@@ -14,6 +14,7 @@ | |||
14 | #ifndef __ASM_DEC_INTERRUPTS_H | 14 | #ifndef __ASM_DEC_INTERRUPTS_H |
15 | #define __ASM_DEC_INTERRUPTS_H | 15 | #define __ASM_DEC_INTERRUPTS_H |
16 | 16 | ||
17 | #include <irq.h> | ||
17 | #include <asm/mipsregs.h> | 18 | #include <asm/mipsregs.h> |
18 | 19 | ||
19 | 20 | ||
@@ -87,7 +88,7 @@ | |||
87 | #define DEC_CPU_INR_SW1 1 /* software #1 */ | 88 | #define DEC_CPU_INR_SW1 1 /* software #1 */ |
88 | #define DEC_CPU_INR_SW0 0 /* software #0 */ | 89 | #define DEC_CPU_INR_SW0 0 /* software #0 */ |
89 | 90 | ||
90 | #define DEC_CPU_IRQ_BASE 0 /* first IRQ assigned to CPU */ | 91 | #define DEC_CPU_IRQ_BASE MIPS_CPU_IRQ_BASE /* first IRQ assigned to CPU */ |
91 | 92 | ||
92 | #define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE) | 93 | #define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE) |
93 | #define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP)) | 94 | #define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP)) |
diff --git a/include/asm-mips/dec/system.h b/include/asm-mips/dec/system.h index 78af51fbc797..b2afaccd6831 100644 --- a/include/asm-mips/dec/system.h +++ b/include/asm-mips/dec/system.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * Generic DECstation/DECsystem bits. | 4 | * Generic DECstation/DECsystem bits. |
5 | * | 5 | * |
6 | * Copyright (C) 2005 Maciej W. Rozycki | 6 | * Copyright (C) 2005, 2006 Maciej W. Rozycki |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or | 8 | * This program is free software; you can redistribute it and/or |
9 | * modify it under the terms of the GNU General Public License | 9 | * modify it under the terms of the GNU General Public License |
@@ -14,5 +14,6 @@ | |||
14 | #define __ASM_DEC_SYSTEM_H | 14 | #define __ASM_DEC_SYSTEM_H |
15 | 15 | ||
16 | extern unsigned long dec_kn_slot_base, dec_kn_slot_size; | 16 | extern unsigned long dec_kn_slot_base, dec_kn_slot_size; |
17 | extern int dec_tc_bus; | ||
17 | 18 | ||
18 | #endif /* __ASM_DEC_SYSTEM_H */ | 19 | #endif /* __ASM_DEC_SYSTEM_H */ |
diff --git a/include/asm-mips/dec/tc.h b/include/asm-mips/dec/tc.h deleted file mode 100644 index 9cb51f24d42c..000000000000 --- a/include/asm-mips/dec/tc.h +++ /dev/null | |||
@@ -1,41 +0,0 @@ | |||
1 | /* | ||
2 | * Interface to the TURBOchannel related routines | ||
3 | * | ||
4 | * This file is subject to the terms and conditions of the GNU General Public | ||
5 | * License. See the file "COPYING" in the main directory of this archive | ||
6 | * for more details. | ||
7 | * | ||
8 | * Copyright (c) 1998 Harald Koerfgen | ||
9 | */ | ||
10 | #ifndef __ASM_DEC_TC_H | ||
11 | #define __ASM_DEC_TC_H | ||
12 | |||
13 | /* | ||
14 | * Search for a TURBOchannel Option Module | ||
15 | * with a certain name. Returns slot number | ||
16 | * of the first card not in use or -ENODEV | ||
17 | * if none found. | ||
18 | */ | ||
19 | extern int search_tc_card(const char *); | ||
20 | /* | ||
21 | * Marks the card in slot as used | ||
22 | */ | ||
23 | extern void claim_tc_card(int); | ||
24 | /* | ||
25 | * Marks the card in slot as free | ||
26 | */ | ||
27 | extern void release_tc_card(int); | ||
28 | /* | ||
29 | * Return base address of card in slot | ||
30 | */ | ||
31 | extern unsigned long get_tc_base_addr(int); | ||
32 | /* | ||
33 | * Return interrupt number of slot | ||
34 | */ | ||
35 | extern unsigned long get_tc_irq_nr(int); | ||
36 | /* | ||
37 | * Return TURBOchannel clock frequency in Hz | ||
38 | */ | ||
39 | extern unsigned long get_tc_speed(void); | ||
40 | |||
41 | #endif /* __ASM_DEC_TC_H */ | ||
diff --git a/include/asm-mips/dec/tcinfo.h b/include/asm-mips/dec/tcinfo.h deleted file mode 100644 index cc23509ee77a..000000000000 --- a/include/asm-mips/dec/tcinfo.h +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | /* | ||
2 | * Various TURBOchannel related stuff | ||
3 | * | ||
4 | * This file is subject to the terms and conditions of the GNU General Public | ||
5 | * License. See the file "COPYING" in the main directory of this archive | ||
6 | * for more details. | ||
7 | * | ||
8 | * Information obtained through the get_tcinfo prom call | ||
9 | * created from: | ||
10 | * | ||
11 | * TURBOchannel Firmware Specification | ||
12 | * | ||
13 | * EK-TCAAD-FS-004 | ||
14 | * from Digital Equipment Corporation | ||
15 | * | ||
16 | * Copyright (c) 1998 Harald Koerfgen | ||
17 | */ | ||
18 | |||
19 | typedef struct { | ||
20 | int revision; | ||
21 | int clk_period; | ||
22 | int slot_size; | ||
23 | int io_timeout; | ||
24 | int dma_range; | ||
25 | int max_dma_burst; | ||
26 | int parity; | ||
27 | int reserved[4]; | ||
28 | } tcinfo; | ||
29 | |||
30 | #define MAX_SLOT 7 | ||
31 | |||
32 | typedef struct { | ||
33 | unsigned long base_addr; | ||
34 | unsigned char name[9]; | ||
35 | unsigned char vendor[9]; | ||
36 | unsigned char firmware[9]; | ||
37 | int interrupt; | ||
38 | int flags; | ||
39 | } slot_info; | ||
40 | |||
41 | /* | ||
42 | * Values for flags | ||
43 | */ | ||
44 | #define FREE 1<<0 | ||
45 | #define IN_USE 1<<1 | ||
46 | |||
47 | |||
diff --git a/include/asm-mips/dec/tcmodule.h b/include/asm-mips/dec/tcmodule.h deleted file mode 100644 index 6268e8915d87..000000000000 --- a/include/asm-mips/dec/tcmodule.h +++ /dev/null | |||
@@ -1,39 +0,0 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Offsets for the ROM header locations for | ||
7 | * TURBOchannel cards | ||
8 | * | ||
9 | * created from: | ||
10 | * | ||
11 | * TURBOchannel Firmware Specification | ||
12 | * | ||
13 | * EK-TCAAD-FS-004 | ||
14 | * from Digital Equipment Corporation | ||
15 | * | ||
16 | * Jan.1998 Harald Koerfgen | ||
17 | */ | ||
18 | #ifndef __ASM_DEC_TCMODULE_H | ||
19 | #define __ASM_DEC_TCMODULE_H | ||
20 | |||
21 | #define OLDCARD 0x3c0000 | ||
22 | #define NEWCARD 0x000000 | ||
23 | |||
24 | #define TC_ROM_WIDTH 0x3e0 | ||
25 | #define TC_ROM_STRIDE 0x3e4 | ||
26 | #define TC_ROM_SIZE 0x3e8 | ||
27 | #define TC_SLOT_SIZE 0x3ec | ||
28 | #define TC_PATTERN0 0x3f0 | ||
29 | #define TC_PATTERN1 0x3f4 | ||
30 | #define TC_PATTERN2 0x3f8 | ||
31 | #define TC_PATTERN3 0x3fc | ||
32 | #define TC_FIRM_VER 0x400 | ||
33 | #define TC_VENDOR 0x420 | ||
34 | #define TC_MODULE 0x440 | ||
35 | #define TC_FIRM_TYPE 0x460 | ||
36 | #define TC_FLAGS 0x470 | ||
37 | #define TC_ROM_OBJECTS 0x480 | ||
38 | |||
39 | #endif /* __ASM_DEC_TCMODULE_H */ | ||
diff --git a/include/asm-mips/dma-mapping.h b/include/asm-mips/dma-mapping.h index 236d1a467cc7..230b3f1b69b1 100644 --- a/include/asm-mips/dma-mapping.h +++ b/include/asm-mips/dma-mapping.h | |||
@@ -68,6 +68,7 @@ extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr); | |||
68 | extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, | 68 | extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, |
69 | enum dma_data_direction direction); | 69 | enum dma_data_direction direction); |
70 | 70 | ||
71 | #if 0 | ||
71 | #define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY | 72 | #define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY |
72 | 73 | ||
73 | extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, | 74 | extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, |
@@ -75,5 +76,6 @@ extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, | |||
75 | extern void dma_release_declared_memory(struct device *dev); | 76 | extern void dma_release_declared_memory(struct device *dev); |
76 | extern void * dma_mark_declared_memory_occupied(struct device *dev, | 77 | extern void * dma_mark_declared_memory_occupied(struct device *dev, |
77 | dma_addr_t device_addr, size_t size); | 78 | dma_addr_t device_addr, size_t size); |
79 | #endif | ||
78 | 80 | ||
79 | #endif /* _ASM_DMA_MAPPING_H */ | 81 | #endif /* _ASM_DMA_MAPPING_H */ |
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h index 23f789c80845..e06ef0776d48 100644 --- a/include/asm-mips/dma.h +++ b/include/asm-mips/dma.h | |||
@@ -91,6 +91,7 @@ | |||
91 | #else | 91 | #else |
92 | #define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) | 92 | #define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000) |
93 | #endif | 93 | #endif |
94 | #define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS)) | ||
94 | 95 | ||
95 | /* 8237 DMA controllers */ | 96 | /* 8237 DMA controllers */ |
96 | #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ | 97 | #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ |
diff --git a/include/asm-mips/ds1216.h b/include/asm-mips/ds1216.h new file mode 100644 index 000000000000..1ff8b73f7a6a --- /dev/null +++ b/include/asm-mips/ds1216.h | |||
@@ -0,0 +1,31 @@ | |||
1 | #ifndef _DS1216_H | ||
2 | #define _DS1216_H | ||
3 | |||
4 | extern volatile unsigned char *ds1216_base; | ||
5 | unsigned long ds1216_get_cmos_time(void); | ||
6 | int ds1216_set_rtc_mmss(unsigned long nowtime); | ||
7 | |||
8 | #define DS1216_SEC_BYTE 1 | ||
9 | #define DS1216_MIN_BYTE 2 | ||
10 | #define DS1216_HOUR_BYTE 3 | ||
11 | #define DS1216_HOUR_MASK (0x1f) | ||
12 | #define DS1216_AMPM_MASK (1<<5) | ||
13 | #define DS1216_1224_MASK (1<<7) | ||
14 | #define DS1216_DAY_BYTE 4 | ||
15 | #define DS1216_DAY_MASK (0x7) | ||
16 | #define DS1216_DATE_BYTE 5 | ||
17 | #define DS1216_DATE_MASK (0x3f) | ||
18 | #define DS1216_MONTH_BYTE 6 | ||
19 | #define DS1216_MONTH_MASK (0x1f) | ||
20 | #define DS1216_YEAR_BYTE 7 | ||
21 | |||
22 | #define DS1216_SEC(buf) (buf[DS1216_SEC_BYTE]) | ||
23 | #define DS1216_MIN(buf) (buf[DS1216_MIN_BYTE]) | ||
24 | #define DS1216_HOUR(buf) (buf[DS1216_HOUR_BYTE] & DS1216_HOUR_MASK) | ||
25 | #define DS1216_AMPM(buf) (buf[DS1216_HOUR_BYTE] & DS1216_AMPM_MASK) | ||
26 | #define DS1216_1224(buf) (buf[DS1216_HOUR_BYTE] & DS1216_1224_MASK) | ||
27 | #define DS1216_DATE(buf) (buf[DS1216_DATE_BYTE] & DS1216_DATE_MASK) | ||
28 | #define DS1216_MONTH(buf) (buf[DS1216_MONTH_BYTE] & DS1216_MONTH_MASK) | ||
29 | #define DS1216_YEAR(buf) (buf[DS1216_YEAR_BYTE]) | ||
30 | |||
31 | #endif | ||
diff --git a/include/asm-mips/emma2rh/emma2rh.h b/include/asm-mips/emma2rh/emma2rh.h index 4fb8df71caa9..6a1af0af51e3 100644 --- a/include/asm-mips/emma2rh/emma2rh.h +++ b/include/asm-mips/emma2rh/emma2rh.h | |||
@@ -24,6 +24,8 @@ | |||
24 | #ifndef __ASM_EMMA2RH_EMMA2RH_H | 24 | #ifndef __ASM_EMMA2RH_EMMA2RH_H |
25 | #define __ASM_EMMA2RH_EMMA2RH_H | 25 | #define __ASM_EMMA2RH_EMMA2RH_H |
26 | 26 | ||
27 | #include <irq.h> | ||
28 | |||
27 | /* | 29 | /* |
28 | * EMMA2RH registers | 30 | * EMMA2RH registers |
29 | */ | 31 | */ |
@@ -104,7 +106,8 @@ | |||
104 | #define NUM_EMMA2RH_IRQ 96 | 106 | #define NUM_EMMA2RH_IRQ 96 |
105 | 107 | ||
106 | #define CPU_EMMA2RH_CASCADE 2 | 108 | #define CPU_EMMA2RH_CASCADE 2 |
107 | #define EMMA2RH_IRQ_BASE 0 | 109 | #define CPU_IRQ_BASE MIPS_CPU_IRQ_BASE |
110 | #define EMMA2RH_IRQ_BASE (CPU_IRQ_BASE + NUM_CPU_IRQ) | ||
108 | 111 | ||
109 | /* | 112 | /* |
110 | * emma2rh irq defs | 113 | * emma2rh irq defs |
diff --git a/include/asm-mips/emma2rh/markeins.h b/include/asm-mips/emma2rh/markeins.h index 8fa766795078..973b0628490d 100644 --- a/include/asm-mips/emma2rh/markeins.h +++ b/include/asm-mips/emma2rh/markeins.h | |||
@@ -33,7 +33,6 @@ | |||
33 | 33 | ||
34 | #define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) | 34 | #define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ) |
35 | #define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) | 35 | #define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW) |
36 | #define CPU_IRQ_BASE (EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO) | ||
37 | 36 | ||
38 | #define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE) | 37 | #define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE) |
39 | #define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE) | 38 | #define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE) |
diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h index 4df8d8b118c0..e88a01607fea 100644 --- a/include/asm-mips/i8259.h +++ b/include/asm-mips/i8259.h | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/spinlock.h> | 18 | #include <linux/spinlock.h> |
19 | 19 | ||
20 | #include <asm/io.h> | 20 | #include <asm/io.h> |
21 | #include <irq.h> | ||
21 | 22 | ||
22 | /* i8259A PIC registers */ | 23 | /* i8259A PIC registers */ |
23 | #define PIC_MASTER_CMD 0x20 | 24 | #define PIC_MASTER_CMD 0x20 |
@@ -42,8 +43,6 @@ extern void disable_8259A_irq(unsigned int irq); | |||
42 | 43 | ||
43 | extern void init_i8259_irqs(void); | 44 | extern void init_i8259_irqs(void); |
44 | 45 | ||
45 | #define I8259A_IRQ_BASE 0 | ||
46 | |||
47 | /* | 46 | /* |
48 | * Do the traditional i8259 interrupt polling thing. This is for the few | 47 | * Do the traditional i8259 interrupt polling thing. This is for the few |
49 | * cases where no better interrupt acknowledge method is available and we | 48 | * cases where no better interrupt acknowledge method is available and we |
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index d77b657c09c7..92ec2618560c 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <asm/byteorder.h> | 20 | #include <asm/byteorder.h> |
21 | #include <asm/cpu.h> | 21 | #include <asm/cpu.h> |
22 | #include <asm/cpu-features.h> | 22 | #include <asm/cpu-features.h> |
23 | #include <asm-generic/iomap.h> | ||
23 | #include <asm/page.h> | 24 | #include <asm/page.h> |
24 | #include <asm/pgtable-bits.h> | 25 | #include <asm/pgtable-bits.h> |
25 | #include <asm/processor.h> | 26 | #include <asm/processor.h> |
@@ -115,7 +116,7 @@ static inline void set_io_port_base(unsigned long base) | |||
115 | */ | 116 | */ |
116 | static inline unsigned long virt_to_phys(volatile const void *address) | 117 | static inline unsigned long virt_to_phys(volatile const void *address) |
117 | { | 118 | { |
118 | return (unsigned long)address - PAGE_OFFSET; | 119 | return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET; |
119 | } | 120 | } |
120 | 121 | ||
121 | /* | 122 | /* |
@@ -132,7 +133,7 @@ static inline unsigned long virt_to_phys(volatile const void *address) | |||
132 | */ | 133 | */ |
133 | static inline void * phys_to_virt(unsigned long address) | 134 | static inline void * phys_to_virt(unsigned long address) |
134 | { | 135 | { |
135 | return (void *)(address + PAGE_OFFSET); | 136 | return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); |
136 | } | 137 | } |
137 | 138 | ||
138 | /* | 139 | /* |
@@ -518,34 +519,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int | |||
518 | } | 519 | } |
519 | 520 | ||
520 | /* | 521 | /* |
521 | * Memory Mapped I/O | ||
522 | */ | ||
523 | #define ioread8(addr) readb(addr) | ||
524 | #define ioread16(addr) readw(addr) | ||
525 | #define ioread32(addr) readl(addr) | ||
526 | |||
527 | #define iowrite8(b,addr) writeb(b,addr) | ||
528 | #define iowrite16(w,addr) writew(w,addr) | ||
529 | #define iowrite32(l,addr) writel(l,addr) | ||
530 | |||
531 | #define ioread8_rep(a,b,c) readsb(a,b,c) | ||
532 | #define ioread16_rep(a,b,c) readsw(a,b,c) | ||
533 | #define ioread32_rep(a,b,c) readsl(a,b,c) | ||
534 | |||
535 | #define iowrite8_rep(a,b,c) writesb(a,b,c) | ||
536 | #define iowrite16_rep(a,b,c) writesw(a,b,c) | ||
537 | #define iowrite32_rep(a,b,c) writesl(a,b,c) | ||
538 | |||
539 | /* Create a virtual mapping cookie for an IO port range */ | ||
540 | extern void __iomem *ioport_map(unsigned long port, unsigned int nr); | ||
541 | extern void ioport_unmap(void __iomem *); | ||
542 | |||
543 | /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ | ||
544 | struct pci_dev; | ||
545 | extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max); | ||
546 | extern void pci_iounmap(struct pci_dev *dev, void __iomem *); | ||
547 | |||
548 | /* | ||
549 | * ISA space is 'always mapped' on currently supported MIPS systems, no need | 522 | * ISA space is 'always mapped' on currently supported MIPS systems, no need |
550 | * to explicitly ioremap() it. The fact that the ISA IO space is mapped | 523 | * to explicitly ioremap() it. The fact that the ISA IO space is mapped |
551 | * to PAGE_OFFSET is pure coincidence - it does not mean ISA values | 524 | * to PAGE_OFFSET is pure coincidence - it does not mean ISA values |
@@ -556,12 +529,6 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *); | |||
556 | #define __ISA_IO_base ((char *)(isa_slot_offset)) | 529 | #define __ISA_IO_base ((char *)(isa_slot_offset)) |
557 | 530 | ||
558 | /* | 531 | /* |
559 | * We don't have csum_partial_copy_fromio() yet, so we cheat here and | ||
560 | * just copy it. The net code will then do the checksum later. | ||
561 | */ | ||
562 | #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len)) | ||
563 | |||
564 | /* | ||
565 | * The caches on some architectures aren't dma-coherent and have need to | 532 | * The caches on some architectures aren't dma-coherent and have need to |
566 | * handle this in software. There are three types of operations that | 533 | * handle this in software. There are three types of operations that |
567 | * can be applied to dma buffers. | 534 | * can be applied to dma buffers. |
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h index 386da82e5774..91803ba30ff2 100644 --- a/include/asm-mips/irq.h +++ b/include/asm-mips/irq.h | |||
@@ -18,7 +18,7 @@ | |||
18 | #ifdef CONFIG_I8259 | 18 | #ifdef CONFIG_I8259 |
19 | static inline int irq_canonicalize(int irq) | 19 | static inline int irq_canonicalize(int irq) |
20 | { | 20 | { |
21 | return ((irq == 2) ? 9 : irq); | 21 | return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq); |
22 | } | 22 | } |
23 | #else | 23 | #else |
24 | #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ | 24 | #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */ |
diff --git a/include/asm-mips/irq_cpu.h b/include/asm-mips/irq_cpu.h index ed3d1e3d09ec..ef6a07cddb23 100644 --- a/include/asm-mips/irq_cpu.h +++ b/include/asm-mips/irq_cpu.h | |||
@@ -13,8 +13,8 @@ | |||
13 | #ifndef _ASM_IRQ_CPU_H | 13 | #ifndef _ASM_IRQ_CPU_H |
14 | #define _ASM_IRQ_CPU_H | 14 | #define _ASM_IRQ_CPU_H |
15 | 15 | ||
16 | extern void mips_cpu_irq_init(int irq_base); | 16 | extern void mips_cpu_irq_init(void); |
17 | extern void rm7k_cpu_irq_init(int irq_base); | 17 | extern void rm7k_cpu_irq_init(void); |
18 | extern void rm9k_cpu_irq_init(int irq_base); | 18 | extern void rm9k_cpu_irq_init(void); |
19 | 19 | ||
20 | #endif /* _ASM_IRQ_CPU_H */ | 20 | #endif /* _ASM_IRQ_CPU_H */ |
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 582acd8adb81..58fca8a5a9a6 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h | |||
@@ -39,6 +39,7 @@ | |||
39 | #ifndef _LANGUAGE_ASSEMBLY | 39 | #ifndef _LANGUAGE_ASSEMBLY |
40 | 40 | ||
41 | #include <linux/delay.h> | 41 | #include <linux/delay.h> |
42 | #include <linux/types.h> | ||
42 | #include <asm/io.h> | 43 | #include <asm/io.h> |
43 | 44 | ||
44 | /* cpu pipeline flush */ | 45 | /* cpu pipeline flush */ |
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h index 00b0fc68d5cb..24a8d51a55a3 100644 --- a/include/asm-mips/mach-cobalt/cobalt.h +++ b/include/asm-mips/mach-cobalt/cobalt.h | |||
@@ -12,6 +12,8 @@ | |||
12 | #ifndef __ASM_COBALT_H | 12 | #ifndef __ASM_COBALT_H |
13 | #define __ASM_COBALT_H | 13 | #define __ASM_COBALT_H |
14 | 14 | ||
15 | #include <irq.h> | ||
16 | |||
15 | /* | 17 | /* |
16 | * i8259 legacy interrupts used on Cobalt: | 18 | * i8259 legacy interrupts used on Cobalt: |
17 | * | 19 | * |
@@ -25,7 +27,7 @@ | |||
25 | /* | 27 | /* |
26 | * CPU IRQs are 16 ... 23 | 28 | * CPU IRQs are 16 ... 23 |
27 | */ | 29 | */ |
28 | #define COBALT_CPU_IRQ 16 | 30 | #define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE |
29 | 31 | ||
30 | #define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) | 32 | #define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2) |
31 | #define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */ | 33 | #define COBALT_SCC_IRQ (COBALT_CPU_IRQ + 3) /* pre-production has 85C30 */ |
diff --git a/include/asm-mips/mach-emma2rh/irq.h b/include/asm-mips/mach-emma2rh/irq.h index bce64244b800..5439eb856461 100644 --- a/include/asm-mips/mach-emma2rh/irq.h +++ b/include/asm-mips/mach-emma2rh/irq.h | |||
@@ -10,4 +10,6 @@ | |||
10 | 10 | ||
11 | #define NR_IRQS 256 | 11 | #define NR_IRQS 256 |
12 | 12 | ||
13 | #include_next <irq.h> | ||
14 | |||
13 | #endif /* __ASM_MACH_EMMA2RH_IRQ_H */ | 15 | #endif /* __ASM_MACH_EMMA2RH_IRQ_H */ |
diff --git a/include/asm-mips/mach-generic/dma-coherence.h b/include/asm-mips/mach-generic/dma-coherence.h new file mode 100644 index 000000000000..df71822fd27b --- /dev/null +++ b/include/asm-mips/mach-generic/dma-coherence.h | |||
@@ -0,0 +1,43 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> | ||
7 | * | ||
8 | */ | ||
9 | #ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H | ||
10 | #define __ASM_MACH_GENERIC_DMA_COHERENCE_H | ||
11 | |||
12 | struct device; | ||
13 | |||
14 | static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) | ||
15 | { | ||
16 | return virt_to_phys(addr); | ||
17 | } | ||
18 | |||
19 | static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) | ||
20 | { | ||
21 | return page_to_phys(page); | ||
22 | } | ||
23 | |||
24 | static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) | ||
25 | { | ||
26 | return dma_addr; | ||
27 | } | ||
28 | |||
29 | static void plat_unmap_dma_mem(dma_addr_t dma_addr) | ||
30 | { | ||
31 | } | ||
32 | |||
33 | static inline int plat_device_is_coherent(struct device *dev) | ||
34 | { | ||
35 | #ifdef CONFIG_DMA_COHERENT | ||
36 | return 1; | ||
37 | #endif | ||
38 | #ifdef CONFIG_DMA_NONCOHERENT | ||
39 | return 0; | ||
40 | #endif | ||
41 | } | ||
42 | |||
43 | #endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ | ||
diff --git a/include/asm-mips/mach-generic/irq.h b/include/asm-mips/mach-generic/irq.h index 500e10ff24de..70d9a25132c5 100644 --- a/include/asm-mips/mach-generic/irq.h +++ b/include/asm-mips/mach-generic/irq.h | |||
@@ -8,6 +8,38 @@ | |||
8 | #ifndef __ASM_MACH_GENERIC_IRQ_H | 8 | #ifndef __ASM_MACH_GENERIC_IRQ_H |
9 | #define __ASM_MACH_GENERIC_IRQ_H | 9 | #define __ASM_MACH_GENERIC_IRQ_H |
10 | 10 | ||
11 | #ifndef NR_IRQS | ||
11 | #define NR_IRQS 128 | 12 | #define NR_IRQS 128 |
13 | #endif | ||
14 | |||
15 | #ifdef CONFIG_I8259 | ||
16 | #ifndef I8259A_IRQ_BASE | ||
17 | #define I8259A_IRQ_BASE 0 | ||
18 | #endif | ||
19 | #endif | ||
20 | |||
21 | #ifdef CONFIG_IRQ_CPU | ||
22 | |||
23 | #ifndef MIPS_CPU_IRQ_BASE | ||
24 | #ifdef CONFIG_I8259 | ||
25 | #define MIPS_CPU_IRQ_BASE 16 | ||
26 | #else | ||
27 | #define MIPS_CPU_IRQ_BASE 0 | ||
28 | #endif /* CONFIG_I8259 */ | ||
29 | #endif | ||
30 | |||
31 | #ifdef CONFIG_IRQ_CPU_RM7K | ||
32 | #ifndef RM7K_CPU_IRQ_BASE | ||
33 | #define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8) | ||
34 | #endif | ||
35 | #endif | ||
36 | |||
37 | #ifdef CONFIG_IRQ_CPU_RM9K | ||
38 | #ifndef RM9K_CPU_IRQ_BASE | ||
39 | #define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12) | ||
40 | #endif | ||
41 | #endif | ||
42 | |||
43 | #endif /* CONFIG_IRQ_CPU */ | ||
12 | 44 | ||
13 | #endif /* __ASM_MACH_GENERIC_IRQ_H */ | 45 | #endif /* __ASM_MACH_GENERIC_IRQ_H */ |
diff --git a/include/asm-mips/mach-generic/kmalloc.h b/include/asm-mips/mach-generic/kmalloc.h index 410ab5f6c563..b8e6deba352f 100644 --- a/include/asm-mips/mach-generic/kmalloc.h +++ b/include/asm-mips/mach-generic/kmalloc.h | |||
@@ -5,6 +5,7 @@ | |||
5 | #ifndef CONFIG_DMA_COHERENT | 5 | #ifndef CONFIG_DMA_COHERENT |
6 | /* | 6 | /* |
7 | * Total overkill for most systems but need as a safe default. | 7 | * Total overkill for most systems but need as a safe default. |
8 | * Set this one if any device in the system might do non-coherent DMA. | ||
8 | */ | 9 | */ |
9 | #define ARCH_KMALLOC_MINALIGN 128 | 10 | #define ARCH_KMALLOC_MINALIGN 128 |
10 | #endif | 11 | #endif |
diff --git a/include/asm-mips/mach-ip27/dma-coherence.h b/include/asm-mips/mach-ip27/dma-coherence.h new file mode 100644 index 000000000000..659816e200d4 --- /dev/null +++ b/include/asm-mips/mach-ip27/dma-coherence.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> | ||
7 | * | ||
8 | */ | ||
9 | #ifndef __ASM_MACH_IP27_DMA_COHERENCE_H | ||
10 | #define __ASM_MACH_IP27_DMA_COHERENCE_H | ||
11 | |||
12 | #include <asm/pci/bridge.h> | ||
13 | |||
14 | #define pdev_to_baddr(pdev, addr) \ | ||
15 | (BRIDGE_CONTROLLER(pdev->bus)->baddr + (addr)) | ||
16 | #define dev_to_baddr(dev, addr) \ | ||
17 | pdev_to_baddr(to_pci_dev(dev), (addr)) | ||
18 | |||
19 | struct device; | ||
20 | |||
21 | static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) | ||
22 | { | ||
23 | dma_addr_t pa = dev_to_baddr(dev, virt_to_phys(addr)); | ||
24 | |||
25 | return pa; | ||
26 | } | ||
27 | |||
28 | static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) | ||
29 | { | ||
30 | dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page)); | ||
31 | |||
32 | return pa; | ||
33 | } | ||
34 | |||
35 | static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) | ||
36 | { | ||
37 | return dma_addr & (0xffUL << 56); | ||
38 | } | ||
39 | |||
40 | static void plat_unmap_dma_mem(dma_addr_t dma_addr) | ||
41 | { | ||
42 | } | ||
43 | |||
44 | static inline int plat_device_is_coherent(struct device *dev) | ||
45 | { | ||
46 | return 1; /* IP27 non-cohernet mode is unsupported */ | ||
47 | } | ||
48 | |||
49 | #endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */ | ||
diff --git a/include/asm-mips/mach-ip32/dma-coherence.h b/include/asm-mips/mach-ip32/dma-coherence.h new file mode 100644 index 000000000000..950be17bbb86 --- /dev/null +++ b/include/asm-mips/mach-ip32/dma-coherence.h | |||
@@ -0,0 +1,71 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> | ||
7 | * | ||
8 | */ | ||
9 | #ifndef __ASM_MACH_IP35_DMA_COHERENCE_H | ||
10 | #define __ASM_MACH_IP35_DMA_COHERENCE_H | ||
11 | |||
12 | #include <asm/ip32/crime.h> | ||
13 | |||
14 | struct device; | ||
15 | |||
16 | /* | ||
17 | * Few notes. | ||
18 | * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M | ||
19 | * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for | ||
20 | * native-endian) | ||
21 | * 3. All other devices see memory as one big chunk at 0x40000000 | ||
22 | * 4. Non-PCI devices will pass NULL as struct device* | ||
23 | * | ||
24 | * Thus we translate differently, depending on device. | ||
25 | */ | ||
26 | |||
27 | #define RAM_OFFSET_MASK 0x3fffffffUL | ||
28 | |||
29 | static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) | ||
30 | { | ||
31 | dma_addr_t pa = virt_to_phys(addr) & RAM_OFFSET_MASK; | ||
32 | |||
33 | if (dev == NULL) | ||
34 | pa += CRIME_HI_MEM_BASE; | ||
35 | |||
36 | return pa; | ||
37 | } | ||
38 | |||
39 | static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) | ||
40 | { | ||
41 | dma_addr_t pa; | ||
42 | |||
43 | pa = page_to_phys(page) & RAM_OFFSET_MASK; | ||
44 | |||
45 | if (dev == NULL) | ||
46 | pa += CRIME_HI_MEM_BASE; | ||
47 | |||
48 | return pa; | ||
49 | } | ||
50 | |||
51 | /* This is almost certainly wrong but it's what dma-ip32.c used to use */ | ||
52 | static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) | ||
53 | { | ||
54 | unsigned long addr = dma_addr & RAM_OFFSET_MASK; | ||
55 | |||
56 | if (dma_addr >= 256*1024*1024) | ||
57 | addr += CRIME_HI_MEM_BASE; | ||
58 | |||
59 | return addr; | ||
60 | } | ||
61 | |||
62 | static void plat_unmap_dma_mem(dma_addr_t dma_addr) | ||
63 | { | ||
64 | } | ||
65 | |||
66 | static inline int plat_device_is_coherent(struct device *dev) | ||
67 | { | ||
68 | return 0; /* IP32 is non-cohernet */ | ||
69 | } | ||
70 | |||
71 | #endif /* __ASM_MACH_IP35_DMA_COHERENCE_H */ | ||
diff --git a/include/asm-mips/mach-jazz/dma-coherence.h b/include/asm-mips/mach-jazz/dma-coherence.h new file mode 100644 index 000000000000..d66979a124a8 --- /dev/null +++ b/include/asm-mips/mach-jazz/dma-coherence.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MACH_JAZZ_DMA_COHERENCE_H | ||
9 | #define __ASM_MACH_JAZZ_DMA_COHERENCE_H | ||
10 | |||
11 | #include <asm/jazzdma.h> | ||
12 | |||
13 | struct device; | ||
14 | |||
15 | static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size) | ||
16 | { | ||
17 | return vdma_alloc(virt_to_phys(addr), size); | ||
18 | } | ||
19 | |||
20 | static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page) | ||
21 | { | ||
22 | return vdma_alloc(page_to_phys(page), PAGE_SIZE); | ||
23 | } | ||
24 | |||
25 | static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) | ||
26 | { | ||
27 | return vdma_log2phys(dma_addr); | ||
28 | } | ||
29 | |||
30 | static void plat_unmap_dma_mem(dma_addr_t dma_addr) | ||
31 | { | ||
32 | vdma_free(dma_addr); | ||
33 | } | ||
34 | |||
35 | static inline int plat_device_is_coherent(struct device *dev) | ||
36 | { | ||
37 | return 0; | ||
38 | } | ||
39 | |||
40 | #endif /* __ASM_MACH_JAZZ_DMA_COHERENCE_H */ | ||
diff --git a/include/asm-mips/mach-mips/irq.h b/include/asm-mips/mach-mips/irq.h index e994b0c01227..9b9da26683c2 100644 --- a/include/asm-mips/mach-mips/irq.h +++ b/include/asm-mips/mach-mips/irq.h | |||
@@ -4,4 +4,6 @@ | |||
4 | 4 | ||
5 | #define NR_IRQS 256 | 5 | #define NR_IRQS 256 |
6 | 6 | ||
7 | #include_next <irq.h> | ||
8 | |||
7 | #endif /* __ASM_MACH_MIPS_IRQ_H */ | 9 | #endif /* __ASM_MACH_MIPS_IRQ_H */ |
diff --git a/include/asm-mips/mach-rm/cpu-feature-overrides.h b/include/asm-mips/mach-rm/cpu-feature-overrides.h index 11410ae10d36..7e07283140a3 100644 --- a/include/asm-mips/mach-rm/cpu-feature-overrides.h +++ b/include/asm-mips/mach-rm/cpu-feature-overrides.h | |||
@@ -21,9 +21,7 @@ | |||
21 | #define cpu_has_watch 0 | 21 | #define cpu_has_watch 0 |
22 | #define cpu_has_mips16 0 | 22 | #define cpu_has_mips16 0 |
23 | #define cpu_has_divec 0 | 23 | #define cpu_has_divec 0 |
24 | #define cpu_has_vce 0 | ||
25 | #define cpu_has_cache_cdex_p 1 | 24 | #define cpu_has_cache_cdex_p 1 |
26 | #define cpu_has_cache_cdex_s 0 | ||
27 | #define cpu_has_prefetch 0 | 25 | #define cpu_has_prefetch 0 |
28 | #define cpu_has_mcheck 0 | 26 | #define cpu_has_mcheck 0 |
29 | #define cpu_has_ejtag 0 | 27 | #define cpu_has_ejtag 0 |
@@ -35,9 +33,6 @@ | |||
35 | #define cpu_has_nofpuex 0 | 33 | #define cpu_has_nofpuex 0 |
36 | #define cpu_has_64bits 1 | 34 | #define cpu_has_64bits 1 |
37 | 35 | ||
38 | #define cpu_dcache_line_size() 32 | ||
39 | #define cpu_icache_line_size() 32 | ||
40 | |||
41 | #define cpu_has_mips32r1 0 | 36 | #define cpu_has_mips32r1 0 |
42 | #define cpu_has_mips32r2 0 | 37 | #define cpu_has_mips32r2 0 |
43 | #define cpu_has_mips64r1 0 | 38 | #define cpu_has_mips64r1 0 |
diff --git a/include/asm-mips/mach-vr41xx/irq.h b/include/asm-mips/mach-vr41xx/irq.h new file mode 100644 index 000000000000..848812296052 --- /dev/null +++ b/include/asm-mips/mach-vr41xx/irq.h | |||
@@ -0,0 +1,11 @@ | |||
1 | #ifndef __ASM_MACH_VR41XX_IRQ_H | ||
2 | #define __ASM_MACH_VR41XX_IRQ_H | ||
3 | |||
4 | #include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */ | ||
5 | #ifdef CONFIG_NEC_CMBVR4133 | ||
6 | #include <asm/vr41xx/cmbvr4133.h> /* for I8259A_IRQ_BASE */ | ||
7 | #endif | ||
8 | |||
9 | #include_next <irq.h> | ||
10 | |||
11 | #endif /* __ASM_MACH_VR41XX_IRQ_H */ | ||
diff --git a/include/asm-mips/mips-boards/atlasint.h b/include/asm-mips/mips-boards/atlasint.h index b15e4ea0b091..76add42e486e 100644 --- a/include/asm-mips/mips-boards/atlasint.h +++ b/include/asm-mips/mips-boards/atlasint.h | |||
@@ -26,10 +26,12 @@ | |||
26 | #ifndef _MIPS_ATLASINT_H | 26 | #ifndef _MIPS_ATLASINT_H |
27 | #define _MIPS_ATLASINT_H | 27 | #define _MIPS_ATLASINT_H |
28 | 28 | ||
29 | #include <irq.h> | ||
30 | |||
29 | /* | 31 | /* |
30 | * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode) | 32 | * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode) |
31 | */ | 33 | */ |
32 | #define MIPSCPU_INT_BASE 0 | 34 | #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE |
33 | 35 | ||
34 | /* CPU interrupt offsets */ | 36 | /* CPU interrupt offsets */ |
35 | #define MIPSCPU_INT_SW0 0 | 37 | #define MIPSCPU_INT_SW0 0 |
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h index da6cc2fbbc78..9180d6466113 100644 --- a/include/asm-mips/mips-boards/maltaint.h +++ b/include/asm-mips/mips-boards/maltaint.h | |||
@@ -25,6 +25,8 @@ | |||
25 | #ifndef _MIPS_MALTAINT_H | 25 | #ifndef _MIPS_MALTAINT_H |
26 | #define _MIPS_MALTAINT_H | 26 | #define _MIPS_MALTAINT_H |
27 | 27 | ||
28 | #include <irq.h> | ||
29 | |||
28 | /* | 30 | /* |
29 | * Interrupts 0..15 are used for Malta ISA compatible interrupts | 31 | * Interrupts 0..15 are used for Malta ISA compatible interrupts |
30 | */ | 32 | */ |
@@ -33,7 +35,7 @@ | |||
33 | /* | 35 | /* |
34 | * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode) | 36 | * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode) |
35 | */ | 37 | */ |
36 | #define MIPSCPU_INT_BASE 16 | 38 | #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE |
37 | 39 | ||
38 | /* CPU interrupt offsets */ | 40 | /* CPU interrupt offsets */ |
39 | #define MIPSCPU_INT_SW0 0 | 41 | #define MIPSCPU_INT_SW0 0 |
diff --git a/include/asm-mips/mips-boards/prom.h b/include/asm-mips/mips-boards/prom.h index 4168c7fcd43e..7bf6f5f6ab9c 100644 --- a/include/asm-mips/mips-boards/prom.h +++ b/include/asm-mips/mips-boards/prom.h | |||
@@ -33,7 +33,6 @@ extern void prom_printf(char *fmt, ...); | |||
33 | extern void prom_init_cmdline(void); | 33 | extern void prom_init_cmdline(void); |
34 | extern void prom_meminit(void); | 34 | extern void prom_meminit(void); |
35 | extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); | 35 | extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); |
36 | extern unsigned long prom_free_prom_memory (void); | ||
37 | extern void mips_display_message(const char *str); | 36 | extern void mips_display_message(const char *str); |
38 | extern void mips_display_word(unsigned int num); | 37 | extern void mips_display_word(unsigned int num); |
39 | extern int get_ethernet_addr(char *ethernet_addr); | 38 | extern int get_ethernet_addr(char *ethernet_addr); |
diff --git a/include/asm-mips/mips-boards/seadint.h b/include/asm-mips/mips-boards/seadint.h index 365c2a3c64f5..4f6a3933699d 100644 --- a/include/asm-mips/mips-boards/seadint.h +++ b/include/asm-mips/mips-boards/seadint.h | |||
@@ -20,10 +20,12 @@ | |||
20 | #ifndef _MIPS_SEADINT_H | 20 | #ifndef _MIPS_SEADINT_H |
21 | #define _MIPS_SEADINT_H | 21 | #define _MIPS_SEADINT_H |
22 | 22 | ||
23 | #include <irq.h> | ||
24 | |||
23 | /* | 25 | /* |
24 | * Interrupts 0..7 are used for SEAD CPU interrupts | 26 | * Interrupts 0..7 are used for SEAD CPU interrupts |
25 | */ | 27 | */ |
26 | #define MIPSCPU_INT_BASE 0 | 28 | #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE |
27 | 29 | ||
28 | #define MIPSCPU_INT_UART0 2 | 30 | #define MIPSCPU_INT_UART0 2 |
29 | #define MIPSCPU_INT_UART1 3 | 31 | #define MIPSCPU_INT_UART1 3 |
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h index 4952e0b3bf11..54f2fe621d69 100644 --- a/include/asm-mips/mips-boards/simint.h +++ b/include/asm-mips/mips-boards/simint.h | |||
@@ -17,10 +17,11 @@ | |||
17 | #ifndef _MIPS_SIMINT_H | 17 | #ifndef _MIPS_SIMINT_H |
18 | #define _MIPS_SIMINT_H | 18 | #define _MIPS_SIMINT_H |
19 | 19 | ||
20 | #include <irq.h> | ||
20 | 21 | ||
21 | #define SIM_INT_BASE 0 | 22 | #define SIM_INT_BASE 0 |
22 | #define MIPSCPU_INT_MB0 2 | 23 | #define MIPSCPU_INT_MB0 2 |
23 | #define MIPSCPU_INT_BASE 16 | 24 | #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE |
24 | #define MIPS_CPU_TIMER_IRQ 7 | 25 | #define MIPS_CPU_TIMER_IRQ 7 |
25 | 26 | ||
26 | 27 | ||
diff --git a/include/asm-mips/mips_mt.h b/include/asm-mips/mips_mt.h index c31a312b9783..fdfff0b8ce42 100644 --- a/include/asm-mips/mips_mt.h +++ b/include/asm-mips/mips_mt.h | |||
@@ -12,4 +12,7 @@ extern unsigned long mt_fpemul_threshold; | |||
12 | extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value); | 12 | extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value); |
13 | extern void mips_mt_set_cpuoptions(void); | 13 | extern void mips_mt_set_cpuoptions(void); |
14 | 14 | ||
15 | struct class; | ||
16 | extern struct class *mt_class; | ||
17 | |||
15 | #endif /* __ASM_MIPS_MT_H */ | 18 | #endif /* __ASM_MIPS_MT_H */ |
diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h index 3e9468f424f4..294bca12cd3f 100644 --- a/include/asm-mips/mipsmtregs.h +++ b/include/asm-mips/mipsmtregs.h | |||
@@ -165,8 +165,6 @@ | |||
165 | 165 | ||
166 | #ifndef __ASSEMBLY__ | 166 | #ifndef __ASSEMBLY__ |
167 | 167 | ||
168 | extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value); | ||
169 | |||
170 | static inline unsigned int dvpe(void) | 168 | static inline unsigned int dvpe(void) |
171 | { | 169 | { |
172 | int res = 0; | 170 | int res = 0; |
diff --git a/include/asm-mips/mman.h b/include/asm-mips/mman.h index 046cf686bee7..e4d6f1fb1cf7 100644 --- a/include/asm-mips/mman.h +++ b/include/asm-mips/mman.h | |||
@@ -72,7 +72,6 @@ | |||
72 | #define MADV_DOFORK 11 /* do inherit across fork */ | 72 | #define MADV_DOFORK 11 /* do inherit across fork */ |
73 | 73 | ||
74 | /* compatibility flags */ | 74 | /* compatibility flags */ |
75 | #define MAP_ANON MAP_ANONYMOUS | ||
76 | #define MAP_FILE 0 | 75 | #define MAP_FILE 0 |
77 | 76 | ||
78 | #endif /* _ASM_MMAN_H */ | 77 | #endif /* _ASM_MMAN_H */ |
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h index 2f9e1a9ec51f..d3fbd83ff545 100644 --- a/include/asm-mips/page.h +++ b/include/asm-mips/page.h | |||
@@ -34,6 +34,20 @@ | |||
34 | 34 | ||
35 | #ifndef __ASSEMBLY__ | 35 | #ifndef __ASSEMBLY__ |
36 | 36 | ||
37 | /* | ||
38 | * This gives the physical RAM offset. | ||
39 | */ | ||
40 | #ifndef PHYS_OFFSET | ||
41 | #define PHYS_OFFSET 0UL | ||
42 | #endif | ||
43 | |||
44 | /* | ||
45 | * It's normally defined only for FLATMEM config but it's | ||
46 | * used in our early mem init code for all memory models. | ||
47 | * So always define it. | ||
48 | */ | ||
49 | #define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET) | ||
50 | |||
37 | #include <linux/pfn.h> | 51 | #include <linux/pfn.h> |
38 | #include <asm/io.h> | 52 | #include <asm/io.h> |
39 | 53 | ||
@@ -132,20 +146,23 @@ typedef struct { unsigned long pgprot; } pgprot_t; | |||
132 | /* to align the pointer to the (next) page boundary */ | 146 | /* to align the pointer to the (next) page boundary */ |
133 | #define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) | 147 | #define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK) |
134 | 148 | ||
149 | /* | ||
150 | * __pa()/__va() should be used only during mem init. | ||
151 | */ | ||
135 | #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) | 152 | #if defined(CONFIG_64BIT) && !defined(CONFIG_BUILD_ELF64) |
136 | #define __pa_page_offset(x) ((unsigned long)(x) < CKSEG0 ? PAGE_OFFSET : CKSEG0) | 153 | #define __pa_page_offset(x) ((unsigned long)(x) < CKSEG0 ? PAGE_OFFSET : CKSEG0) |
137 | #else | 154 | #else |
138 | #define __pa_page_offset(x) PAGE_OFFSET | 155 | #define __pa_page_offset(x) PAGE_OFFSET |
139 | #endif | 156 | #endif |
140 | #define __pa(x) ((unsigned long)(x) - __pa_page_offset(x)) | 157 | #define __pa(x) ((unsigned long)(x) - __pa_page_offset(x) + PHYS_OFFSET) |
141 | #define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) | 158 | #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) |
142 | #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET)) | 159 | #define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x),0)) |
143 | 160 | ||
144 | #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) | 161 | #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) |
145 | 162 | ||
146 | #ifdef CONFIG_FLATMEM | 163 | #ifdef CONFIG_FLATMEM |
147 | 164 | ||
148 | #define pfn_valid(pfn) ((pfn) < max_mapnr) | 165 | #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) |
149 | 166 | ||
150 | #elif defined(CONFIG_SPARSEMEM) | 167 | #elif defined(CONFIG_SPARSEMEM) |
151 | 168 | ||
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h index 7f0f120ca07c..3eea3ba0fca5 100644 --- a/include/asm-mips/pci.h +++ b/include/asm-mips/pci.h | |||
@@ -32,6 +32,7 @@ struct pci_controller { | |||
32 | unsigned long mem_offset; | 32 | unsigned long mem_offset; |
33 | struct resource *io_resource; | 33 | struct resource *io_resource; |
34 | unsigned long io_offset; | 34 | unsigned long io_offset; |
35 | unsigned long io_map_base; | ||
35 | 36 | ||
36 | unsigned int index; | 37 | unsigned int index; |
37 | /* For compatibility with current (as of July 2003) pciutils | 38 | /* For compatibility with current (as of July 2003) pciutils |
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h index af121c67dc71..5685d4fc7881 100644 --- a/include/asm-mips/pgalloc.h +++ b/include/asm-mips/pgalloc.h | |||
@@ -130,4 +130,6 @@ static inline void pmd_free(pmd_t *pmd) | |||
130 | 130 | ||
131 | #define check_pgt_cache() do { } while (0) | 131 | #define check_pgt_cache() do { } while (0) |
132 | 132 | ||
133 | extern void pagetable_init(void); | ||
134 | |||
133 | #endif /* _ASM_PGALLOC_H */ | 135 | #endif /* _ASM_PGALLOC_H */ |
diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h index 76cd51c6be39..59162f74a798 100644 --- a/include/asm-mips/rtlx.h +++ b/include/asm-mips/rtlx.h | |||
@@ -6,9 +6,10 @@ | |||
6 | #ifndef __ASM_RTLX_H | 6 | #ifndef __ASM_RTLX_H |
7 | #define __ASM_RTLX_H_ | 7 | #define __ASM_RTLX_H_ |
8 | 8 | ||
9 | #include <irq.h> | ||
10 | |||
9 | #define LX_NODE_BASE 10 | 11 | #define LX_NODE_BASE 10 |
10 | 12 | ||
11 | #define MIPSCPU_INT_BASE 16 | ||
12 | #define MIPS_CPU_RTLX_IRQ 0 | 13 | #define MIPS_CPU_RTLX_IRQ 0 |
13 | 14 | ||
14 | #define RTLX_VERSION 2 | 15 | #define RTLX_VERSION 2 |
diff --git a/include/asm-mips/sections.h b/include/asm-mips/sections.h index f7016278b266..b7e37262c246 100644 --- a/include/asm-mips/sections.h +++ b/include/asm-mips/sections.h | |||
@@ -3,6 +3,4 @@ | |||
3 | 3 | ||
4 | #include <asm-generic/sections.h> | 4 | #include <asm-generic/sections.h> |
5 | 5 | ||
6 | extern char _fdata; | ||
7 | |||
8 | #endif /* _ASM_SECTIONS_H */ | 6 | #endif /* _ASM_SECTIONS_H */ |
diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h index bbfc05c3cab9..6592f3bd1999 100644 --- a/include/asm-mips/sgi/ip22.h +++ b/include/asm-mips/sgi/ip22.h | |||
@@ -21,15 +21,16 @@ | |||
21 | * HAL2 driver). This will prevent many complications, trust me ;-) | 21 | * HAL2 driver). This will prevent many complications, trust me ;-) |
22 | */ | 22 | */ |
23 | 23 | ||
24 | #include <irq.h> | ||
24 | #include <asm/sgi/ioc.h> | 25 | #include <asm/sgi/ioc.h> |
25 | 26 | ||
26 | #define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */ | 27 | #define SGINT_EISA 0 /* 16 EISA irq levels (Indigo2) */ |
27 | #define SGINT_CPU 16 /* MIPS CPU define 8 interrupt sources */ | 28 | #define SGINT_CPU MIPS_CPU_IRQ_BASE /* MIPS CPU define 8 interrupt sources */ |
28 | #define SGINT_LOCAL0 24 /* 8 local0 irq levels */ | 29 | #define SGINT_LOCAL0 (SGINT_CPU+8) /* 8 local0 irq levels */ |
29 | #define SGINT_LOCAL1 32 /* 8 local1 irq levels */ | 30 | #define SGINT_LOCAL1 (SGINT_CPU+16) /* 8 local1 irq levels */ |
30 | #define SGINT_LOCAL2 40 /* 8 local2 vectored irq levels */ | 31 | #define SGINT_LOCAL2 (SGINT_CPU+24) /* 8 local2 vectored irq levels */ |
31 | #define SGINT_LOCAL3 48 /* 8 local3 vectored irq levels */ | 32 | #define SGINT_LOCAL3 (SGINT_CPU+32) /* 8 local3 vectored irq levels */ |
32 | #define SGINT_END 56 /* End of 'spaces' */ | 33 | #define SGINT_END (SGINT_CPU+40) /* End of 'spaces' */ |
33 | 34 | ||
34 | /* | 35 | /* |
35 | * Individual interrupt definitions for the Indy and Indigo2 | 36 | * Individual interrupt definitions for the Indy and Indigo2 |
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h index cefa657dd04a..972947474eb7 100644 --- a/include/asm-mips/sigcontext.h +++ b/include/asm-mips/sigcontext.h | |||
@@ -19,7 +19,7 @@ | |||
19 | */ | 19 | */ |
20 | struct sigcontext { | 20 | struct sigcontext { |
21 | unsigned int sc_regmask; /* Unused */ | 21 | unsigned int sc_regmask; /* Unused */ |
22 | unsigned int sc_status; | 22 | unsigned int sc_status; /* Unused */ |
23 | unsigned long long sc_pc; | 23 | unsigned long long sc_pc; |
24 | unsigned long long sc_regs[32]; | 24 | unsigned long long sc_regs[32]; |
25 | unsigned long long sc_fpregs[32]; | 25 | unsigned long long sc_fpregs[32]; |
@@ -42,6 +42,7 @@ struct sigcontext { | |||
42 | 42 | ||
43 | #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 | 43 | #if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 |
44 | 44 | ||
45 | #include <linux/posix_types.h> | ||
45 | /* | 46 | /* |
46 | * Keep this struct definition in sync with the sigcontext fragment | 47 | * Keep this struct definition in sync with the sigcontext fragment |
47 | * in arch/mips/tools/offset.c | 48 | * in arch/mips/tools/offset.c |
@@ -53,30 +54,28 @@ struct sigcontext { | |||
53 | * entries, add sc_dsp and sc_reserved for padding. No prisoners. | 54 | * entries, add sc_dsp and sc_reserved for padding. No prisoners. |
54 | */ | 55 | */ |
55 | struct sigcontext { | 56 | struct sigcontext { |
56 | unsigned long sc_regs[32]; | 57 | __u64 sc_regs[32]; |
57 | unsigned long sc_fpregs[32]; | 58 | __u64 sc_fpregs[32]; |
58 | unsigned long sc_mdhi; | 59 | __u64 sc_mdhi; |
59 | unsigned long sc_hi1; | 60 | __u64 sc_hi1; |
60 | unsigned long sc_hi2; | 61 | __u64 sc_hi2; |
61 | unsigned long sc_hi3; | 62 | __u64 sc_hi3; |
62 | unsigned long sc_mdlo; | 63 | __u64 sc_mdlo; |
63 | unsigned long sc_lo1; | 64 | __u64 sc_lo1; |
64 | unsigned long sc_lo2; | 65 | __u64 sc_lo2; |
65 | unsigned long sc_lo3; | 66 | __u64 sc_lo3; |
66 | unsigned long sc_pc; | 67 | __u64 sc_pc; |
67 | unsigned int sc_fpc_csr; | 68 | __u32 sc_fpc_csr; |
68 | unsigned int sc_used_math; | 69 | __u32 sc_used_math; |
69 | unsigned int sc_dsp; | 70 | __u32 sc_dsp; |
70 | unsigned int sc_reserved; | 71 | __u32 sc_reserved; |
71 | }; | 72 | }; |
72 | 73 | ||
73 | #ifdef __KERNEL__ | 74 | #ifdef __KERNEL__ |
74 | 75 | ||
75 | #include <linux/posix_types.h> | ||
76 | |||
77 | struct sigcontext32 { | 76 | struct sigcontext32 { |
78 | __u32 sc_regmask; /* Unused */ | 77 | __u32 sc_regmask; /* Unused */ |
79 | __u32 sc_status; | 78 | __u32 sc_status; /* Unused */ |
80 | __u64 sc_pc; | 79 | __u64 sc_pc; |
81 | __u64 sc_regs[32]; | 80 | __u64 sc_regs[32]; |
82 | __u64 sc_fpregs[32]; | 81 | __u64 sc_fpregs[32]; |
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h index 8b391a2f0814..7a28989f7ee3 100644 --- a/include/asm-mips/signal.h +++ b/include/asm-mips/signal.h | |||
@@ -137,23 +137,6 @@ typedef struct sigaltstack { | |||
137 | 137 | ||
138 | #define ptrace_signal_deliver(regs, cookie) do { } while (0) | 138 | #define ptrace_signal_deliver(regs, cookie) do { } while (0) |
139 | 139 | ||
140 | struct pt_regs; | ||
141 | extern void do_signal(struct pt_regs *regs); | ||
142 | extern void do_signal32(struct pt_regs *regs); | ||
143 | |||
144 | extern int setup_frame(struct k_sigaction * ka, struct pt_regs *regs, | ||
145 | int signr, sigset_t *set); | ||
146 | extern int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, | ||
147 | int signr, sigset_t *set, siginfo_t *info); | ||
148 | |||
149 | extern int setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs, | ||
150 | int signr, sigset_t *set); | ||
151 | extern int setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, | ||
152 | int signr, sigset_t *set, siginfo_t *info); | ||
153 | |||
154 | extern int setup_rt_frame_n32(struct k_sigaction * ka, struct pt_regs *regs, | ||
155 | int signr, sigset_t *set, siginfo_t *info); | ||
156 | |||
157 | #endif /* __KERNEL__ */ | 140 | #endif /* __KERNEL__ */ |
158 | 141 | ||
159 | #endif /* _ASM_SIGNAL_H */ | 142 | #endif /* _ASM_SIGNAL_H */ |
diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h index f22c3e2f993a..55f3419f6546 100644 --- a/include/asm-mips/smtc_ipi.h +++ b/include/asm-mips/smtc_ipi.h | |||
@@ -44,9 +44,6 @@ struct smtc_ipi_q { | |||
44 | int depth; | 44 | int depth; |
45 | }; | 45 | }; |
46 | 46 | ||
47 | extern struct smtc_ipi_q IPIQ[NR_CPUS]; | ||
48 | extern struct smtc_ipi_q freeIPIq; | ||
49 | |||
50 | static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) | 47 | static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) |
51 | { | 48 | { |
52 | long flags; | 49 | long flags; |
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h index b9ba54d0dd35..62f9be6f7320 100644 --- a/include/asm-mips/sni.h +++ b/include/asm-mips/sni.h | |||
@@ -6,12 +6,72 @@ | |||
6 | * for more details. | 6 | * for more details. |
7 | * | 7 | * |
8 | * Copyright (C) 1997, 1998 by Ralf Baechle | 8 | * Copyright (C) 1997, 1998 by Ralf Baechle |
9 | * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de) | ||
9 | */ | 10 | */ |
10 | #ifndef __ASM_SNI_H | 11 | #ifndef __ASM_SNI_H |
11 | #define __ASM_SNI_H | 12 | #define __ASM_SNI_H |
12 | 13 | ||
14 | extern unsigned int sni_brd_type; | ||
15 | |||
16 | #define SNI_BRD_10 2 | ||
17 | #define SNI_BRD_10NEW 3 | ||
18 | #define SNI_BRD_TOWER_OASIC 4 | ||
19 | #define SNI_BRD_MINITOWER 5 | ||
20 | #define SNI_BRD_PCI_TOWER 6 | ||
21 | #define SNI_BRD_RM200 7 | ||
22 | #define SNI_BRD_PCI_MTOWER 8 | ||
23 | #define SNI_BRD_PCI_DESKTOP 9 | ||
24 | #define SNI_BRD_PCI_TOWER_CPLUS 10 | ||
25 | #define SNI_BRD_PCI_MTOWER_CPLUS 11 | ||
26 | |||
27 | /* RM400 cpu types */ | ||
28 | #define SNI_CPU_M8021 0x01 | ||
29 | #define SNI_CPU_M8030 0x04 | ||
30 | #define SNI_CPU_M8031 0x06 | ||
31 | #define SNI_CPU_M8034 0x0f | ||
32 | #define SNI_CPU_M8037 0x07 | ||
33 | #define SNI_CPU_M8040 0x05 | ||
34 | #define SNI_CPU_M8043 0x09 | ||
35 | #define SNI_CPU_M8050 0x0b | ||
36 | #define SNI_CPU_M8053 0x0d | ||
37 | |||
13 | #define SNI_PORT_BASE 0xb4000000 | 38 | #define SNI_PORT_BASE 0xb4000000 |
14 | 39 | ||
40 | #ifndef __MIPSEL__ | ||
41 | /* | ||
42 | * ASIC PCI registers for big endian configuration. | ||
43 | */ | ||
44 | #define PCIMT_UCONF 0xbfff0004 | ||
45 | #define PCIMT_IOADTIMEOUT2 0xbfff000c | ||
46 | #define PCIMT_IOMEMCONF 0xbfff0014 | ||
47 | #define PCIMT_IOMMU 0xbfff001c | ||
48 | #define PCIMT_IOADTIMEOUT1 0xbfff0024 | ||
49 | #define PCIMT_DMAACCESS 0xbfff002c | ||
50 | #define PCIMT_DMAHIT 0xbfff0034 | ||
51 | #define PCIMT_ERRSTATUS 0xbfff003c | ||
52 | #define PCIMT_ERRADDR 0xbfff0044 | ||
53 | #define PCIMT_SYNDROME 0xbfff004c | ||
54 | #define PCIMT_ITPEND 0xbfff0054 | ||
55 | #define IT_INT2 0x01 | ||
56 | #define IT_INTD 0x02 | ||
57 | #define IT_INTC 0x04 | ||
58 | #define IT_INTB 0x08 | ||
59 | #define IT_INTA 0x10 | ||
60 | #define IT_EISA 0x20 | ||
61 | #define IT_SCSI 0x40 | ||
62 | #define IT_ETH 0x80 | ||
63 | #define PCIMT_IRQSEL 0xbfff005c | ||
64 | #define PCIMT_TESTMEM 0xbfff0064 | ||
65 | #define PCIMT_ECCREG 0xbfff006c | ||
66 | #define PCIMT_CONFIG_ADDRESS 0xbfff0074 | ||
67 | #define PCIMT_ASIC_ID 0xbfff007c /* read */ | ||
68 | #define PCIMT_SOFT_RESET 0xbfff007c /* write */ | ||
69 | #define PCIMT_PIA_OE 0xbfff0084 | ||
70 | #define PCIMT_PIA_DATAOUT 0xbfff008c | ||
71 | #define PCIMT_PIA_DATAIN 0xbfff0094 | ||
72 | #define PCIMT_CACHECONF 0xbfff009c | ||
73 | #define PCIMT_INVSPACE 0xbfff00a4 | ||
74 | #else | ||
15 | /* | 75 | /* |
16 | * ASIC PCI registers for little endian configuration. | 76 | * ASIC PCI registers for little endian configuration. |
17 | */ | 77 | */ |
@@ -45,6 +105,8 @@ | |||
45 | #define PCIMT_PIA_DATAIN 0xbfff0090 | 105 | #define PCIMT_PIA_DATAIN 0xbfff0090 |
46 | #define PCIMT_CACHECONF 0xbfff0098 | 106 | #define PCIMT_CACHECONF 0xbfff0098 |
47 | #define PCIMT_INVSPACE 0xbfff00a0 | 107 | #define PCIMT_INVSPACE 0xbfff00a0 |
108 | #endif | ||
109 | |||
48 | #define PCIMT_PCI_CONF 0xbfff0100 | 110 | #define PCIMT_PCI_CONF 0xbfff0100 |
49 | 111 | ||
50 | /* | 112 | /* |
@@ -73,6 +135,36 @@ | |||
73 | #define PCIMT_PWDN 0xbfdf0000 | 135 | #define PCIMT_PWDN 0xbfdf0000 |
74 | 136 | ||
75 | /* | 137 | /* |
138 | * A20R based boards | ||
139 | */ | ||
140 | #define A20R_PT_CLOCK_BASE 0xbc040000 | ||
141 | #define A20R_PT_TIM0_ACK 0xbc050000 | ||
142 | #define A20R_PT_TIM1_ACK 0xbc060000 | ||
143 | |||
144 | #define SNI_MIPS_IRQ_CPU_BASE 16 | ||
145 | #define SNI_MIPS_IRQ_CPU_TIMER (SNI_MIPS_IRQ_CPU_BASE+7) | ||
146 | |||
147 | #define SNI_A20R_IRQ_BASE SNI_MIPS_IRQ_CPU_BASE | ||
148 | #define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) | ||
149 | |||
150 | #define SNI_DS1216_A20R_BASE 0xbc081ffc | ||
151 | #define SNI_DS1216_RM200_BASE 0xbcd41ffc | ||
152 | |||
153 | #define SNI_PCIT_INT_REG 0xbfff000c | ||
154 | |||
155 | #define SNI_PCIT_INT_START 24 | ||
156 | #define SNI_PCIT_INT_END 30 | ||
157 | |||
158 | #define PCIT_IRQ_ETHERNET (SNI_MIPS_IRQ_CPU_BASE + 5) | ||
159 | #define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0) | ||
160 | #define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1) | ||
161 | #define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2) | ||
162 | #define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3) | ||
163 | #define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4) | ||
164 | #define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5) | ||
165 | |||
166 | |||
167 | /* | ||
76 | * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned | 168 | * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned |
77 | * to the other interrupts generated by ASIC PCI. | 169 | * to the other interrupts generated by ASIC PCI. |
78 | * | 170 | * |
@@ -80,18 +172,22 @@ | |||
80 | * ASIC PCI interrupt. | 172 | * ASIC PCI interrupt. |
81 | */ | 173 | */ |
82 | #define PCIMT_KEYBOARD_IRQ 1 | 174 | #define PCIMT_KEYBOARD_IRQ 1 |
83 | #define PCIMT_IRQ_INT2 16 | 175 | #define PCIMT_IRQ_INT2 24 |
84 | #define PCIMT_IRQ_INTD 17 | 176 | #define PCIMT_IRQ_INTD 25 |
85 | #define PCIMT_IRQ_INTC 18 | 177 | #define PCIMT_IRQ_INTC 26 |
86 | #define PCIMT_IRQ_INTB 19 | 178 | #define PCIMT_IRQ_INTB 27 |
87 | #define PCIMT_IRQ_INTA 20 | 179 | #define PCIMT_IRQ_INTA 28 |
88 | #define PCIMT_IRQ_EISA 21 | 180 | #define PCIMT_IRQ_EISA 29 |
89 | #define PCIMT_IRQ_SCSI 22 | 181 | #define PCIMT_IRQ_SCSI 30 |
90 | #define PCIMT_IRQ_ETHERNET 23 | 182 | |
183 | #define PCIMT_IRQ_ETHERNET (SNI_MIPS_IRQ_CPU_BASE+6) | ||
184 | |||
185 | #if 0 | ||
91 | #define PCIMT_IRQ_TEMPERATURE 24 | 186 | #define PCIMT_IRQ_TEMPERATURE 24 |
92 | #define PCIMT_IRQ_EISA_NMI 25 | 187 | #define PCIMT_IRQ_EISA_NMI 25 |
93 | #define PCIMT_IRQ_POWER_OFF 26 | 188 | #define PCIMT_IRQ_POWER_OFF 26 |
94 | #define PCIMT_IRQ_BUTTON 27 | 189 | #define PCIMT_IRQ_BUTTON 27 |
190 | #endif | ||
95 | 191 | ||
96 | /* | 192 | /* |
97 | * Base address for the mapped 16mb EISA bus segment. | 193 | * Base address for the mapped 16mb EISA bus segment. |
@@ -101,4 +197,24 @@ | |||
101 | /* PCI EISA Interrupt acknowledge */ | 197 | /* PCI EISA Interrupt acknowledge */ |
102 | #define PCIMT_INT_ACKNOWLEDGE 0xba000000 | 198 | #define PCIMT_INT_ACKNOWLEDGE 0xba000000 |
103 | 199 | ||
200 | /* board specific init functions */ | ||
201 | extern void sni_a20r_init (void); | ||
202 | extern void sni_pcit_init (void); | ||
203 | extern void sni_rm200_init (void); | ||
204 | extern void sni_pcimt_init (void); | ||
205 | |||
206 | /* board specific irq init functions */ | ||
207 | extern void sni_a20r_irq_init (void); | ||
208 | extern void sni_pcit_irq_init (void); | ||
209 | extern void sni_pcit_cplus_irq_init (void); | ||
210 | extern void sni_rm200_irq_init (void); | ||
211 | extern void sni_pcimt_irq_init (void); | ||
212 | |||
213 | /* timer inits */ | ||
214 | extern void sni_cpu_time_init(void); | ||
215 | |||
216 | /* common irq stuff */ | ||
217 | extern void (*sni_hwint)(void); | ||
218 | extern struct irqaction sni_isa_irq; | ||
219 | |||
104 | #endif /* __ASM_SNI_H */ | 220 | #endif /* __ASM_SNI_H */ |
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h index fc3217fc1118..f1755d28a36a 100644 --- a/include/asm-mips/spinlock.h +++ b/include/asm-mips/spinlock.h | |||
@@ -3,7 +3,7 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 1999, 2000, 06 by Ralf Baechle | 6 | * Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org) |
7 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. | 7 | * Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
8 | */ | 8 | */ |
9 | #ifndef _ASM_SPINLOCK_H | 9 | #ifndef _ASM_SPINLOCK_H |
@@ -49,11 +49,18 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock) | |||
49 | __asm__ __volatile__( | 49 | __asm__ __volatile__( |
50 | " .set noreorder # __raw_spin_lock \n" | 50 | " .set noreorder # __raw_spin_lock \n" |
51 | "1: ll %1, %2 \n" | 51 | "1: ll %1, %2 \n" |
52 | " bnez %1, 1b \n" | 52 | " bnez %1, 2f \n" |
53 | " li %1, 1 \n" | 53 | " li %1, 1 \n" |
54 | " sc %1, %0 \n" | 54 | " sc %1, %0 \n" |
55 | " beqz %1, 1b \n" | 55 | " beqz %1, 2f \n" |
56 | " nop \n" | 56 | " nop \n" |
57 | " .subsection 2 \n" | ||
58 | "2: ll %1, %2 \n" | ||
59 | " bnez %1, 2b \n" | ||
60 | " li %1, 1 \n" | ||
61 | " b 1b \n" | ||
62 | " nop \n" | ||
63 | " .previous \n" | ||
57 | " .set reorder \n" | 64 | " .set reorder \n" |
58 | : "=m" (lock->lock), "=&r" (tmp) | 65 | : "=m" (lock->lock), "=&r" (tmp) |
59 | : "m" (lock->lock) | 66 | : "m" (lock->lock) |
@@ -99,8 +106,12 @@ static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock) | |||
99 | "1: ll %0, %3 \n" | 106 | "1: ll %0, %3 \n" |
100 | " ori %2, %0, 1 \n" | 107 | " ori %2, %0, 1 \n" |
101 | " sc %2, %1 \n" | 108 | " sc %2, %1 \n" |
102 | " beqz %2, 1b \n" | 109 | " beqz %2, 2f \n" |
103 | " andi %2, %0, 1 \n" | 110 | " andi %2, %0, 1 \n" |
111 | " .subsection 2 \n" | ||
112 | "2: b 1b \n" | ||
113 | " nop \n" | ||
114 | " .previous \n" | ||
104 | " .set reorder" | 115 | " .set reorder" |
105 | : "=&r" (temp), "=m" (lock->lock), "=&r" (res) | 116 | : "=&r" (temp), "=m" (lock->lock), "=&r" (res) |
106 | : "m" (lock->lock) | 117 | : "m" (lock->lock) |
@@ -154,11 +165,18 @@ static inline void __raw_read_lock(raw_rwlock_t *rw) | |||
154 | __asm__ __volatile__( | 165 | __asm__ __volatile__( |
155 | " .set noreorder # __raw_read_lock \n" | 166 | " .set noreorder # __raw_read_lock \n" |
156 | "1: ll %1, %2 \n" | 167 | "1: ll %1, %2 \n" |
157 | " bltz %1, 1b \n" | 168 | " bltz %1, 2f \n" |
158 | " addu %1, 1 \n" | 169 | " addu %1, 1 \n" |
159 | " sc %1, %0 \n" | 170 | " sc %1, %0 \n" |
160 | " beqz %1, 1b \n" | 171 | " beqz %1, 1b \n" |
161 | " nop \n" | 172 | " nop \n" |
173 | " .subsection 2 \n" | ||
174 | "2: ll %1, %2 \n" | ||
175 | " bltz %1, 2b \n" | ||
176 | " addu %1, 1 \n" | ||
177 | " b 1b \n" | ||
178 | " nop \n" | ||
179 | " .previous \n" | ||
162 | " .set reorder \n" | 180 | " .set reorder \n" |
163 | : "=m" (rw->lock), "=&r" (tmp) | 181 | : "=m" (rw->lock), "=&r" (tmp) |
164 | : "m" (rw->lock) | 182 | : "m" (rw->lock) |
@@ -192,8 +210,12 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw) | |||
192 | "1: ll %1, %2 \n" | 210 | "1: ll %1, %2 \n" |
193 | " sub %1, 1 \n" | 211 | " sub %1, 1 \n" |
194 | " sc %1, %0 \n" | 212 | " sc %1, %0 \n" |
195 | " beqz %1, 1b \n" | 213 | " beqz %1, 2f \n" |
214 | " nop \n" | ||
215 | " .subsection 2 \n" | ||
216 | "2: b 1b \n" | ||
196 | " nop \n" | 217 | " nop \n" |
218 | " .previous \n" | ||
197 | " .set reorder \n" | 219 | " .set reorder \n" |
198 | : "=m" (rw->lock), "=&r" (tmp) | 220 | : "=m" (rw->lock), "=&r" (tmp) |
199 | : "m" (rw->lock) | 221 | : "m" (rw->lock) |
@@ -222,11 +244,18 @@ static inline void __raw_write_lock(raw_rwlock_t *rw) | |||
222 | __asm__ __volatile__( | 244 | __asm__ __volatile__( |
223 | " .set noreorder # __raw_write_lock \n" | 245 | " .set noreorder # __raw_write_lock \n" |
224 | "1: ll %1, %2 \n" | 246 | "1: ll %1, %2 \n" |
225 | " bnez %1, 1b \n" | 247 | " bnez %1, 2f \n" |
226 | " lui %1, 0x8000 \n" | 248 | " lui %1, 0x8000 \n" |
227 | " sc %1, %0 \n" | 249 | " sc %1, %0 \n" |
228 | " beqz %1, 1b \n" | 250 | " beqz %1, 2f \n" |
251 | " nop \n" | ||
252 | " .subsection 2 \n" | ||
253 | "2: ll %1, %2 \n" | ||
254 | " bnez %1, 2b \n" | ||
255 | " lui %1, 0x8000 \n" | ||
256 | " b 1b \n" | ||
229 | " nop \n" | 257 | " nop \n" |
258 | " .previous \n" | ||
230 | " .set reorder \n" | 259 | " .set reorder \n" |
231 | : "=m" (rw->lock), "=&r" (tmp) | 260 | : "=m" (rw->lock), "=&r" (tmp) |
232 | : "m" (rw->lock) | 261 | : "m" (rw->lock) |
@@ -322,12 +351,15 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw) | |||
322 | " bnez %1, 2f \n" | 351 | " bnez %1, 2f \n" |
323 | " lui %1, 0x8000 \n" | 352 | " lui %1, 0x8000 \n" |
324 | " sc %1, %0 \n" | 353 | " sc %1, %0 \n" |
325 | " beqz %1, 1b \n" | 354 | " beqz %1, 3f \n" |
326 | " nop \n" | 355 | " li %2, 1 \n" |
356 | "2: \n" | ||
327 | __WEAK_ORDERING_MB | 357 | __WEAK_ORDERING_MB |
328 | " li %2, 1 \n" | 358 | " .subsection 2 \n" |
359 | "3: b 1b \n" | ||
360 | " li %2, 0 \n" | ||
361 | " .previous \n" | ||
329 | " .set reorder \n" | 362 | " .set reorder \n" |
330 | "2: \n" | ||
331 | : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) | 363 | : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret) |
332 | : "m" (rw->lock) | 364 | : "m" (rw->lock) |
333 | : "memory"); | 365 | : "memory"); |
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h index 5e1289c85ed9..597a3743f6a1 100644 --- a/include/asm-mips/system.h +++ b/include/asm-mips/system.h | |||
@@ -110,7 +110,10 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val) | |||
110 | " move %2, %z4 \n" | 110 | " move %2, %z4 \n" |
111 | " .set mips3 \n" | 111 | " .set mips3 \n" |
112 | " sc %2, %1 \n" | 112 | " sc %2, %1 \n" |
113 | " beqz %2, 1b \n" | 113 | " beqz %2, 2f \n" |
114 | " .subsection 2 \n" | ||
115 | "2: b 1b \n" | ||
116 | " .previous \n" | ||
114 | " .set mips0 \n" | 117 | " .set mips0 \n" |
115 | : "=&r" (retval), "=m" (*m), "=&r" (dummy) | 118 | : "=&r" (retval), "=m" (*m), "=&r" (dummy) |
116 | : "R" (*m), "Jr" (val) | 119 | : "R" (*m), "Jr" (val) |
@@ -155,7 +158,10 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val) | |||
155 | "1: lld %0, %3 # xchg_u64 \n" | 158 | "1: lld %0, %3 # xchg_u64 \n" |
156 | " move %2, %z4 \n" | 159 | " move %2, %z4 \n" |
157 | " scd %2, %1 \n" | 160 | " scd %2, %1 \n" |
158 | " beqz %2, 1b \n" | 161 | " beqz %2, 2f \n" |
162 | " .subsection 2 \n" | ||
163 | "2: b 1b \n" | ||
164 | " .previous \n" | ||
159 | " .set mips0 \n" | 165 | " .set mips0 \n" |
160 | : "=&r" (retval), "=m" (*m), "=&r" (dummy) | 166 | : "=&r" (retval), "=m" (*m), "=&r" (dummy) |
161 | : "R" (*m), "Jr" (val) | 167 | : "R" (*m), "Jr" (val) |
@@ -232,8 +238,11 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, | |||
232 | " move $1, %z4 \n" | 238 | " move $1, %z4 \n" |
233 | " .set mips3 \n" | 239 | " .set mips3 \n" |
234 | " sc $1, %1 \n" | 240 | " sc $1, %1 \n" |
235 | " beqz $1, 1b \n" | 241 | " beqz $1, 3f \n" |
236 | "2: \n" | 242 | "2: \n" |
243 | " .subsection 2 \n" | ||
244 | "3: b 1b \n" | ||
245 | " .previous \n" | ||
237 | " .set pop \n" | 246 | " .set pop \n" |
238 | : "=&r" (retval), "=R" (*m) | 247 | : "=&r" (retval), "=R" (*m) |
239 | : "R" (*m), "Jr" (old), "Jr" (new) | 248 | : "R" (*m), "Jr" (old), "Jr" (new) |
@@ -283,8 +292,11 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old, | |||
283 | " bne %0, %z3, 2f \n" | 292 | " bne %0, %z3, 2f \n" |
284 | " move $1, %z4 \n" | 293 | " move $1, %z4 \n" |
285 | " scd $1, %1 \n" | 294 | " scd $1, %1 \n" |
286 | " beqz $1, 1b \n" | 295 | " beqz $1, 3f \n" |
287 | "2: \n" | 296 | "2: \n" |
297 | " .subsection 2 \n" | ||
298 | "3: b 1b \n" | ||
299 | " .previous \n" | ||
288 | " .set pop \n" | 300 | " .set pop \n" |
289 | : "=&r" (retval), "=R" (*m) | 301 | : "=&r" (retval), "=R" (*m) |
290 | : "R" (*m), "Jr" (old), "Jr" (new) | 302 | : "R" (*m), "Jr" (old), "Jr" (new) |
diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h index 4906204d34fe..2ce07f4be369 100644 --- a/include/asm-mips/termios.h +++ b/include/asm-mips/termios.h | |||
@@ -87,24 +87,6 @@ struct termio { | |||
87 | #define TIOCM_OUT2 0x4000 | 87 | #define TIOCM_OUT2 0x4000 |
88 | #define TIOCM_LOOP 0x8000 | 88 | #define TIOCM_LOOP 0x8000 |
89 | 89 | ||
90 | /* line disciplines */ | ||
91 | #define N_TTY 0 | ||
92 | #define N_SLIP 1 | ||
93 | #define N_MOUSE 2 | ||
94 | #define N_PPP 3 | ||
95 | #define N_STRIP 4 | ||
96 | #define N_AX25 5 | ||
97 | #define N_X25 6 /* X.25 async */ | ||
98 | #define N_6PACK 7 | ||
99 | #define N_MASC 8 /* Reserved fo Mobitex module <kaz@cafe.net> */ | ||
100 | #define N_R3964 9 /* Reserved for Simatic R3964 module */ | ||
101 | #define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */ | ||
102 | #define N_IRDA 11 /* Linux IrDa - http://irda.sourceforge.net/ */ | ||
103 | #define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */ | ||
104 | #define N_HDLC 13 /* synchronous HDLC */ | ||
105 | #define N_SYNC_PPP 14 /* synchronous PPP */ | ||
106 | #define N_HCI 15 /* Bluetooth HCI UART */ | ||
107 | |||
108 | #ifdef __KERNEL__ | 90 | #ifdef __KERNEL__ |
109 | 91 | ||
110 | #include <linux/string.h> | 92 | #include <linux/string.h> |
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h index 1cdd4eeb2f73..c62c20e7b5c6 100644 --- a/include/asm-mips/uaccess.h +++ b/include/asm-mips/uaccess.h | |||
@@ -265,12 +265,14 @@ do { \ | |||
265 | */ | 265 | */ |
266 | #define __get_user_asm_ll32(val, addr) \ | 266 | #define __get_user_asm_ll32(val, addr) \ |
267 | { \ | 267 | { \ |
268 | unsigned long long __gu_tmp; \ | 268 | union { \ |
269 | unsigned long long l; \ | ||
270 | __typeof__(*(addr)) t; \ | ||
271 | } __gu_tmp; \ | ||
269 | \ | 272 | \ |
270 | __asm__ __volatile__( \ | 273 | __asm__ __volatile__( \ |
271 | "1: lw %1, (%3) \n" \ | 274 | "1: lw %1, (%3) \n" \ |
272 | "2: lw %D1, 4(%3) \n" \ | 275 | "2: lw %D1, 4(%3) \n" \ |
273 | " move %0, $0 \n" \ | ||
274 | "3: .section .fixup,\"ax\" \n" \ | 276 | "3: .section .fixup,\"ax\" \n" \ |
275 | "4: li %0, %4 \n" \ | 277 | "4: li %0, %4 \n" \ |
276 | " move %1, $0 \n" \ | 278 | " move %1, $0 \n" \ |
@@ -281,9 +283,10 @@ do { \ | |||
281 | " " __UA_ADDR " 1b, 4b \n" \ | 283 | " " __UA_ADDR " 1b, 4b \n" \ |
282 | " " __UA_ADDR " 2b, 4b \n" \ | 284 | " " __UA_ADDR " 2b, 4b \n" \ |
283 | " .previous \n" \ | 285 | " .previous \n" \ |
284 | : "=r" (__gu_err), "=&r" (__gu_tmp) \ | 286 | : "=r" (__gu_err), "=&r" (__gu_tmp.l) \ |
285 | : "0" (0), "r" (addr), "i" (-EFAULT)); \ | 287 | : "0" (0), "r" (addr), "i" (-EFAULT)); \ |
286 | (val) = (__typeof__(*(addr))) __gu_tmp; \ | 288 | \ |
289 | (val) = __gu_tmp.t; \ | ||
287 | } | 290 | } |
288 | 291 | ||
289 | /* | 292 | /* |
@@ -432,8 +435,32 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); | |||
432 | __cu_len; \ | 435 | __cu_len; \ |
433 | }) | 436 | }) |
434 | 437 | ||
435 | #define __copy_to_user_inatomic __copy_to_user | 438 | #define __copy_to_user_inatomic(to,from,n) \ |
436 | #define __copy_from_user_inatomic __copy_from_user | 439 | ({ \ |
440 | void __user *__cu_to; \ | ||
441 | const void *__cu_from; \ | ||
442 | long __cu_len; \ | ||
443 | \ | ||
444 | __cu_to = (to); \ | ||
445 | __cu_from = (from); \ | ||
446 | __cu_len = (n); \ | ||
447 | __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \ | ||
448 | __cu_len; \ | ||
449 | }) | ||
450 | |||
451 | #define __copy_from_user_inatomic(to,from,n) \ | ||
452 | ({ \ | ||
453 | void *__cu_to; \ | ||
454 | const void __user *__cu_from; \ | ||
455 | long __cu_len; \ | ||
456 | \ | ||
457 | __cu_to = (to); \ | ||
458 | __cu_from = (from); \ | ||
459 | __cu_len = (n); \ | ||
460 | __cu_len = __invoke_copy_from_user_inatomic(__cu_to, __cu_from, \ | ||
461 | __cu_len); \ | ||
462 | __cu_len; \ | ||
463 | }) | ||
437 | 464 | ||
438 | /* | 465 | /* |
439 | * copy_to_user: - Copy a block of data into user space. | 466 | * copy_to_user: - Copy a block of data into user space. |
@@ -487,8 +514,32 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n); | |||
487 | __cu_len_r; \ | 514 | __cu_len_r; \ |
488 | }) | 515 | }) |
489 | 516 | ||
517 | #define __invoke_copy_from_user_inatomic(to,from,n) \ | ||
518 | ({ \ | ||
519 | register void *__cu_to_r __asm__ ("$4"); \ | ||
520 | register const void __user *__cu_from_r __asm__ ("$5"); \ | ||
521 | register long __cu_len_r __asm__ ("$6"); \ | ||
522 | \ | ||
523 | __cu_to_r = (to); \ | ||
524 | __cu_from_r = (from); \ | ||
525 | __cu_len_r = (n); \ | ||
526 | __asm__ __volatile__( \ | ||
527 | ".set\tnoreorder\n\t" \ | ||
528 | __MODULE_JAL(__copy_user_inatomic) \ | ||
529 | ".set\tnoat\n\t" \ | ||
530 | __UA_ADDU "\t$1, %1, %2\n\t" \ | ||
531 | ".set\tat\n\t" \ | ||
532 | ".set\treorder" \ | ||
533 | : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r) \ | ||
534 | : \ | ||
535 | : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31", \ | ||
536 | "memory"); \ | ||
537 | __cu_len_r; \ | ||
538 | }) | ||
539 | |||
490 | /* | 540 | /* |
491 | * __copy_from_user: - Copy a block of data from user space, with less checking. * @to: Destination address, in kernel space. | 541 | * __copy_from_user: - Copy a block of data from user space, with less checking. |
542 | * @to: Destination address, in kernel space. | ||
492 | * @from: Source address, in user space. | 543 | * @from: Source address, in user space. |
493 | * @n: Number of bytes to copy. | 544 | * @n: Number of bytes to copy. |
494 | * | 545 | * |
diff --git a/include/asm-mips/vr41xx/cmbvr4133.h b/include/asm-mips/vr41xx/cmbvr4133.h index 9490ade58b46..42300037d593 100644 --- a/include/asm-mips/vr41xx/cmbvr4133.h +++ b/include/asm-mips/vr41xx/cmbvr4133.h | |||
@@ -35,8 +35,8 @@ | |||
35 | #define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN) | 35 | #define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN) |
36 | #define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN) | 36 | #define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN) |
37 | 37 | ||
38 | #define I8259_IRQ_BASE 72 | 38 | #define I8259A_IRQ_BASE 72 |
39 | #define I8259_IRQ(x) (I8259_IRQ_BASE + (x)) | 39 | #define I8259_IRQ(x) (I8259A_IRQ_BASE + (x)) |
40 | #define TIMER_IRQ I8259_IRQ(0) | 40 | #define TIMER_IRQ I8259_IRQ(0) |
41 | #define KEYBOARD_IRQ I8259_IRQ(1) | 41 | #define KEYBOARD_IRQ I8259_IRQ(1) |
42 | #define I8259_SLAVE_IRQ I8259_IRQ(2) | 42 | #define I8259_SLAVE_IRQ I8259_IRQ(2) |
@@ -52,6 +52,5 @@ | |||
52 | #define AUX_IRQ I8259_IRQ(12) | 52 | #define AUX_IRQ I8259_IRQ(12) |
53 | #define IDE_PRIMARY_IRQ I8259_IRQ(14) | 53 | #define IDE_PRIMARY_IRQ I8259_IRQ(14) |
54 | #define IDE_SECONDARY_IRQ I8259_IRQ(15) | 54 | #define IDE_SECONDARY_IRQ I8259_IRQ(15) |
55 | #define I8259_IRQ_LAST IDE_SECONDARY_IRQ | ||
56 | 55 | ||
57 | #endif /* __NEC_CMBVR4133_H */ | 56 | #endif /* __NEC_CMBVR4133_H */ |