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authorIngo Molnar <mingo@elte.hu>2008-07-18 15:13:20 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-18 15:13:20 -0400
commitf6dc8ccaab6d8f63cbae1e6c73fe972b26f5376c (patch)
treec5643fcdc884a8d0bfc3f1bc28039cab7394e5bc /include/asm-mips
parent323ec001c6bb98eeabb5abbdbb8c8055d9496554 (diff)
parent5b664cb235e97afbf34db9c4d77f08ebd725335e (diff)
Merge branch 'linus' into core/generic-dma-coherent
Conflicts: kernel/Makefile Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-mips')
-rw-r--r--include/asm-mips/atomic.h4
-rw-r--r--include/asm-mips/barrier.h14
-rw-r--r--include/asm-mips/bitops.h6
-rw-r--r--include/asm-mips/bootinfo.h43
-rw-r--r--include/asm-mips/cpu.h4
-rw-r--r--include/asm-mips/dec/kn05.h9
-rw-r--r--include/asm-mips/inventory.h24
-rw-r--r--include/asm-mips/io.h17
-rw-r--r--include/asm-mips/lasat/lasat.h2
-rw-r--r--include/asm-mips/mach-atlas/mc146818rtc.h60
-rw-r--r--include/asm-mips/mach-au1x00/au1100_mmc.h18
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_psc.h8
-rw-r--r--include/asm-mips/mach-db1x00/db1x00.h45
-rw-r--r--include/asm-mips/mach-malta/cpu-feature-overrides.h (renamed from include/asm-mips/mach-mips/cpu-feature-overrides.h)0
-rw-r--r--include/asm-mips/mach-malta/irq.h (renamed from include/asm-mips/mach-mips/irq.h)0
-rw-r--r--include/asm-mips/mach-malta/kernel-entry-init.h (renamed from include/asm-mips/mach-mips/kernel-entry-init.h)0
-rw-r--r--include/asm-mips/mach-malta/mach-gt64120.h (renamed from include/asm-mips/mach-mips/mach-gt64120.h)0
-rw-r--r--include/asm-mips/mach-malta/mc146818rtc.h (renamed from include/asm-mips/mach-mips/mc146818rtc.h)0
-rw-r--r--include/asm-mips/mach-malta/war.h (renamed from include/asm-mips/mach-mips/war.h)0
-rw-r--r--include/asm-mips/mach-tx39xx/ioremap.h (renamed from include/asm-mips/mach-jmr3927/ioremap.h)8
-rw-r--r--include/asm-mips/mach-tx39xx/mangle-port.h (renamed from include/asm-mips/mach-jmr3927/mangle-port.h)13
-rw-r--r--include/asm-mips/mach-tx39xx/war.h (renamed from include/asm-mips/mach-jmr3927/war.h)6
-rw-r--r--include/asm-mips/mach-vr41xx/irq.h3
-rw-r--r--include/asm-mips/mips-boards/generic.h9
-rw-r--r--include/asm-mips/namei.h25
-rw-r--r--include/asm-mips/pci.h3
-rw-r--r--include/asm-mips/prctl.h41
-rw-r--r--include/asm-mips/setup.h2
-rw-r--r--include/asm-mips/signal.h3
-rw-r--r--include/asm-mips/smp.h13
-rw-r--r--include/asm-mips/traps.h1
-rw-r--r--include/asm-mips/tx4927/tx4927.h46
-rw-r--r--include/asm-mips/tx4927/tx4927_pci.h268
-rw-r--r--include/asm-mips/txx9/generic.h41
-rw-r--r--include/asm-mips/txx9/jmr3927.h (renamed from include/asm-mips/jmr3927/jmr3927.h)13
-rw-r--r--include/asm-mips/txx9/pci.h36
-rw-r--r--include/asm-mips/txx9/rbtx4927.h (renamed from include/asm-mips/tx4927/toshiba_rbtx4927.h)52
-rw-r--r--include/asm-mips/txx9/rbtx4938.h (renamed from include/asm-mips/tx4938/rbtx4938.h)45
-rw-r--r--include/asm-mips/txx9/smsc_fdc37m81x.h (renamed from include/asm-mips/tx4927/smsc_fdc37m81x.h)2
-rw-r--r--include/asm-mips/txx9/spi.h (renamed from include/asm-mips/tx4938/spi.h)7
-rw-r--r--include/asm-mips/txx9/tx3927.h (renamed from include/asm-mips/jmr3927/tx3927.h)12
-rw-r--r--include/asm-mips/txx9/tx4927.h219
-rw-r--r--include/asm-mips/txx9/tx4927pcic.h199
-rw-r--r--include/asm-mips/txx9/tx4938.h (renamed from include/asm-mips/tx4938/tx4938.h)239
-rw-r--r--include/asm-mips/txx9/txx927.h (renamed from include/asm-mips/jmr3927/txx927.h)6
-rw-r--r--include/asm-mips/vr41xx/cmbvr4133.h56
46 files changed, 682 insertions, 940 deletions
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index a798d6299a79..1232be3885b0 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -283,10 +283,10 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
283 " beqz %0, 2f \n" 283 " beqz %0, 2f \n"
284 " subu %0, %1, %3 \n" 284 " subu %0, %1, %3 \n"
285 " .set reorder \n" 285 " .set reorder \n"
286 "1: \n"
287 " .subsection 2 \n" 286 " .subsection 2 \n"
288 "2: b 1b \n" 287 "2: b 1b \n"
289 " .previous \n" 288 " .previous \n"
289 "1: \n"
290 " .set mips0 \n" 290 " .set mips0 \n"
291 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 291 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
292 : "Ir" (i), "m" (v->counter) 292 : "Ir" (i), "m" (v->counter)
@@ -664,10 +664,10 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
664 " beqz %0, 2f \n" 664 " beqz %0, 2f \n"
665 " dsubu %0, %1, %3 \n" 665 " dsubu %0, %1, %3 \n"
666 " .set reorder \n" 666 " .set reorder \n"
667 "1: \n"
668 " .subsection 2 \n" 667 " .subsection 2 \n"
669 "2: b 1b \n" 668 "2: b 1b \n"
670 " .previous \n" 669 " .previous \n"
670 "1: \n"
671 " .set mips0 \n" 671 " .set mips0 \n"
672 : "=&r" (result), "=&r" (temp), "=m" (v->counter) 672 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
673 : "Ir" (i), "m" (v->counter) 673 : "Ir" (i), "m" (v->counter)
diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h
index 9d8cfbb5e796..8e9ac313ca3b 100644
--- a/include/asm-mips/barrier.h
+++ b/include/asm-mips/barrier.h
@@ -92,11 +92,25 @@
92#define fast_wmb() __sync() 92#define fast_wmb() __sync()
93#define fast_rmb() __sync() 93#define fast_rmb() __sync()
94#define fast_mb() __sync() 94#define fast_mb() __sync()
95#ifdef CONFIG_SGI_IP28
96#define fast_iob() \
97 __asm__ __volatile__( \
98 ".set push\n\t" \
99 ".set noreorder\n\t" \
100 "lw $0,%0\n\t" \
101 "sync\n\t" \
102 "lw $0,%0\n\t" \
103 ".set pop" \
104 : /* no output */ \
105 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
106 : "memory")
107#else
95#define fast_iob() \ 108#define fast_iob() \
96 do { \ 109 do { \
97 __sync(); \ 110 __sync(); \
98 __fast_iob(); \ 111 __fast_iob(); \
99 } while (0) 112 } while (0)
113#endif
100 114
101#ifdef CONFIG_CPU_HAS_WB 115#ifdef CONFIG_CPU_HAS_WB
102 116
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 642724734eba..9a7274ba6a0b 100644
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -82,7 +82,7 @@ static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
82 "2: b 1b \n" 82 "2: b 1b \n"
83 " .previous \n" 83 " .previous \n"
84 : "=&r" (temp), "=m" (*m) 84 : "=&r" (temp), "=m" (*m)
85 : "ir" (bit), "m" (*m), "r" (~0)); 85 : "i" (bit), "m" (*m), "r" (~0));
86#endif /* CONFIG_CPU_MIPSR2 */ 86#endif /* CONFIG_CPU_MIPSR2 */
87 } else if (cpu_has_llsc) { 87 } else if (cpu_has_llsc) {
88 __asm__ __volatile__( 88 __asm__ __volatile__(
@@ -147,7 +147,7 @@ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
147 "2: b 1b \n" 147 "2: b 1b \n"
148 " .previous \n" 148 " .previous \n"
149 : "=&r" (temp), "=m" (*m) 149 : "=&r" (temp), "=m" (*m)
150 : "ir" (bit), "m" (*m)); 150 : "i" (bit), "m" (*m));
151#endif /* CONFIG_CPU_MIPSR2 */ 151#endif /* CONFIG_CPU_MIPSR2 */
152 } else if (cpu_has_llsc) { 152 } else if (cpu_has_llsc) {
153 __asm__ __volatile__( 153 __asm__ __volatile__(
@@ -428,7 +428,7 @@ static inline int test_and_clear_bit(unsigned long nr,
428 "2: b 1b \n" 428 "2: b 1b \n"
429 " .previous \n" 429 " .previous \n"
430 : "=&r" (temp), "=m" (*m), "=&r" (res) 430 : "=&r" (temp), "=m" (*m), "=&r" (res)
431 : "ri" (bit), "m" (*m) 431 : "i" (bit), "m" (*m)
432 : "memory"); 432 : "memory");
433#endif 433#endif
434 } else if (cpu_has_llsc) { 434 } else if (cpu_has_llsc) {
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index e031bdff9920..d39e143b4a3c 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -26,13 +26,6 @@
26#define MACH_UNKNOWN 0 /* whatever... */ 26#define MACH_UNKNOWN 0 /* whatever... */
27 27
28/* 28/*
29 * Valid machtype values for group JAZZ
30 */
31#define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */
32#define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */
33#define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */
34
35/*
36 * Valid machtype for group DEC 29 * Valid machtype for group DEC
37 */ 30 */
38#define MACH_DSUNKNOWN 0 31#define MACH_DSUNKNOWN 0
@@ -48,42 +41,6 @@
48#define MACH_DS5900 10 /* DECsystem 5900 */ 41#define MACH_DS5900 10 /* DECsystem 5900 */
49 42
50/* 43/*
51 * Valid machtype for group SNI_RM
52 */
53#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */
54
55/*
56 * Valid machtype for group SGI
57 */
58#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */
59#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */
60#define MACH_SGI_IP28 2 /* Indigo2 Impact */
61#define MACH_SGI_IP32 3 /* O2 */
62#define MACH_SGI_IP30 4 /* Octane, Octane2 */
63
64/*
65 * Valid machtypes for group Toshiba
66 */
67#define MACH_PALLAS 0
68#define MACH_TOPAS 1
69#define MACH_JMR 2
70#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */
71#define MACH_TOSHIBA_RBTX4927 4
72#define MACH_TOSHIBA_RBTX4937 5
73#define MACH_TOSHIBA_RBTX4938 6
74
75/*
76 * Valid machtype for group LASAT
77 */
78#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */
79#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */
80
81/*
82 * Valid machtype for group NEC EMMA2RH
83 */
84#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
85
86/*
87 * Valid machtype for group PMC-MSP 44 * Valid machtype for group PMC-MSP
88 */ 45 */
89#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */ 46#define MACH_MSP4200_EVAL 0 /* PMC-Sierra MSP4200 Evaluation */
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 1c35cac6f35b..229a786101d9 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -66,8 +66,10 @@
66#define PRID_IMP_RM7000 0x2700 66#define PRID_IMP_RM7000 0x2700
67#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ 67#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
68#define PRID_IMP_RM9000 0x3400 68#define PRID_IMP_RM9000 0x3400
69#define PRID_IMP_LOONGSON1 0x4200
69#define PRID_IMP_R5432 0x5400 70#define PRID_IMP_R5432 0x5400
70#define PRID_IMP_R5500 0x5500 71#define PRID_IMP_R5500 0x5500
72#define PRID_IMP_LOONGSON2 0x6300
71 73
72#define PRID_IMP_UNKNOWN 0xff00 74#define PRID_IMP_UNKNOWN 0xff00
73 75
@@ -90,8 +92,6 @@
90#define PRID_IMP_24KE 0x9600 92#define PRID_IMP_24KE 0x9600
91#define PRID_IMP_74K 0x9700 93#define PRID_IMP_74K 0x9700
92#define PRID_IMP_1004K 0x9900 94#define PRID_IMP_1004K 0x9900
93#define PRID_IMP_LOONGSON1 0x4200
94#define PRID_IMP_LOONGSON2 0x6300
95 95
96/* 96/*
97 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE 97 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h
index 15fe8f881e60..56d22dc8803a 100644
--- a/include/asm-mips/dec/kn05.h
+++ b/include/asm-mips/dec/kn05.h
@@ -6,7 +6,7 @@
6 * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC 6 * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
7 * definitions. 7 * definitions.
8 * 8 *
9 * Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki 9 * Copyright (C) 2002, 2003, 2005, 2008 Maciej W. Rozycki
10 * 10 *
11 * This program is free software; you can redistribute it and/or 11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License 12 * modify it under the terms of the GNU General Public License
@@ -54,11 +54,11 @@
54 */ 54 */
55#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */ 55#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */
56#define KN4K_MB_INT_RTC (1<<1) /* RTC? */ 56#define KN4K_MB_INT_RTC (1<<1) /* RTC? */
57#define KN4K_MB_INT_MT (1<<3) /* ??? */ 57#define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */
58 58
59/* 59/*
60 * Bits for the MB control & status register. 60 * Bits for the MB control & status register.
61 * Set to 0x00bf8001 on my system by the ROM. 61 * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
62 */ 62 */
63#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */ 63#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */
64#define KN4K_MB_CSR_F (1<<1) /* ??? */ 64#define KN4K_MB_CSR_F (1<<1) /* ??? */
@@ -69,7 +69,8 @@
69#define KN4K_MB_CSR_IM (1<<13) /* ??? */ 69#define KN4K_MB_CSR_IM (1<<13) /* ??? */
70#define KN4K_MB_CSR_NC (1<<14) /* ??? */ 70#define KN4K_MB_CSR_NC (1<<14) /* ??? */
71#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ 71#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
72#define KN4K_MB_CSR_MSK (0x1f<<16) /* ??? */ 72#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */
73#define KN4K_MB_CSR_FW (1<<21) /* ??? */ 73#define KN4K_MB_CSR_FW (1<<21) /* ??? */
74#define KN4K_MB_CSR_W (1<<31) /* ??? */
74 75
75#endif /* __ASM_MIPS_DEC_KN05_H */ 76#endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/include/asm-mips/inventory.h b/include/asm-mips/inventory.h
deleted file mode 100644
index cc88aed23f0f..000000000000
--- a/include/asm-mips/inventory.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Miguel de Icaza
3 */
4#ifndef __ASM_INVENTORY_H
5#define __ASM_INVENTORY_H
6
7#include <linux/compiler.h>
8
9typedef struct inventory_s {
10 struct inventory_s *inv_next;
11 int inv_class;
12 int inv_type;
13 int inv_controller;
14 int inv_unit;
15 int inv_state;
16} inventory_t;
17
18extern int inventory_items;
19
20extern void add_to_inventory(int class, int type, int controller, int unit, int state);
21extern int dump_inventory_to_user(void __user *userbuf, int size);
22extern int __init init_inventory(void);
23
24#endif /* __ASM_INVENTORY_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index f18d2816cbec..501a40b9f18d 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -161,13 +161,6 @@ static inline void * isa_bus_to_virt(unsigned long address)
161#define bus_to_virt phys_to_virt 161#define bus_to_virt phys_to_virt
162 162
163/* 163/*
164 * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
165 * for the processor. This implies the assumption that there is only
166 * one of these busses.
167 */
168extern unsigned long isa_slot_offset;
169
170/*
171 * Change "struct page" to physical address. 164 * Change "struct page" to physical address.
172 */ 165 */
173#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 166#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
@@ -528,16 +521,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
528} 521}
529 522
530/* 523/*
531 * ISA space is 'always mapped' on currently supported MIPS systems, no need
532 * to explicitly ioremap() it. The fact that the ISA IO space is mapped
533 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
534 * are physical addresses. The following constant pointer can be
535 * used as the IO-area pointer (it can be iounmapped as well, so the
536 * analogy with PCI is quite large):
537 */
538#define __ISA_IO_base ((char *)(isa_slot_offset))
539
540/*
541 * The caches on some architectures aren't dma-coherent and have need to 524 * The caches on some architectures aren't dma-coherent and have need to
542 * handle this in software. There are three types of operations that 525 * handle this in software. There are three types of operations that
543 * can be applied to dma buffers. 526 * can be applied to dma buffers.
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h
index ea04d9262edc..caeba1e302a2 100644
--- a/include/asm-mips/lasat/lasat.h
+++ b/include/asm-mips/lasat/lasat.h
@@ -240,6 +240,8 @@ static inline void lasat_ndelay(unsigned int ns)
240 __delay(ns / lasat_ndelay_divider); 240 __delay(ns / lasat_ndelay_divider);
241} 241}
242 242
243#define IS_LASAT_200() (current_cpu_data.cputype == CPU_R5000)
244
243#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 245#endif /* !defined (_LANGUAGE_ASSEMBLY) */
244 246
245#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef 247#define LASAT_SERVICEMODE_MAGIC_1 0xdeadbeef
diff --git a/include/asm-mips/mach-atlas/mc146818rtc.h b/include/asm-mips/mach-atlas/mc146818rtc.h
deleted file mode 100644
index 51d337e1bbd1..000000000000
--- a/include/asm-mips/mach-atlas/mc146818rtc.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * Copyright (C) 1999, 2000, 2005 MIPS Technologies, Inc.
3 * All rights reserved.
4 * Authors: Carsten Langgaard <carstenl@mips.com>
5 * Maciej W. Rozycki <macro@mips.com>
6 * Copyright (C) 2003, 05 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 */
21#ifndef __ASM_MACH_ATLAS_MC146818RTC_H
22#define __ASM_MACH_ATLAS_MC146818RTC_H
23
24#include <linux/types.h>
25
26#include <asm/addrspace.h>
27
28#include <asm/mips-boards/atlas.h>
29#include <asm/mips-boards/atlasint.h>
30
31#define ARCH_RTC_LOCATION
32
33#define RTC_PORT(x) (ATLAS_RTC_ADR_REG + (x) * 8)
34#define RTC_IO_EXTENT 0x100
35#define RTC_IOMAPPED 0
36#define RTC_IRQ ATLAS_INT_RTC
37
38static inline unsigned char CMOS_READ(unsigned long addr)
39{
40 volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0));
41 volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1));
42
43 *ireg = addr;
44 return *dreg;
45}
46
47static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
48{
49 volatile u32 *ireg = (void *)CKSEG1ADDR(RTC_PORT(0));
50 volatile u32 *dreg = (void *)CKSEG1ADDR(RTC_PORT(1));
51
52 *ireg = addr;
53 *dreg = data;
54}
55
56#define RTC_ALWAYS_BCD 0
57
58#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
59
60#endif /* __ASM_MACH_ATLAS_MC146818RTC_H */
diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h
index 9e0028f60a43..c35e20918490 100644
--- a/include/asm-mips/mach-au1x00/au1100_mmc.h
+++ b/include/asm-mips/mach-au1x00/au1100_mmc.h
@@ -38,15 +38,15 @@
38#ifndef __ASM_AU1100_MMC_H 38#ifndef __ASM_AU1100_MMC_H
39#define __ASM_AU1100_MMC_H 39#define __ASM_AU1100_MMC_H
40 40
41 41#include <linux/leds.h>
42#define NUM_AU1100_MMC_CONTROLLERS 2 42
43 43struct au1xmmc_platform_data {
44#if defined(CONFIG_SOC_AU1100) 44 int(*cd_setup)(void *mmc_host, int on);
45#define AU1100_SD_IRQ AU1100_SD_INT 45 int(*card_inserted)(void *mmc_host);
46#elif defined(CONFIG_SOC_AU1200) 46 int(*card_readonly)(void *mmc_host);
47#define AU1100_SD_IRQ AU1200_SD_INT 47 void(*set_power)(void *mmc_host, int state);
48#endif 48 struct led_classdev *led;
49 49};
50 50
51#define SD0_BASE 0xB0600000 51#define SD0_BASE 0xB0600000
52#define SD1_BASE 0xB0680000 52#define SD1_BASE 0xB0680000
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
index dae4eca2417e..892b7f168eb4 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h
@@ -204,6 +204,14 @@ typedef struct psc_i2s {
204 u32 psc_i2sudf; 204 u32 psc_i2sudf;
205} psc_i2s_t; 205} psc_i2s_t;
206 206
207#define PSC_I2SCFG_OFFSET 0x08
208#define PSC_I2SMASK_OFFSET 0x0C
209#define PSC_I2SPCR_OFFSET 0x10
210#define PSC_I2SSTAT_OFFSET 0x14
211#define PSC_I2SEVENT_OFFSET 0x18
212#define PSC_I2SRXTX_OFFSET 0x1C
213#define PSC_I2SUDF_OFFSET 0x20
214
207/* I2S Config Register. */ 215/* I2S Config Register. */
208#define PSC_I2SCFG_RT_MASK (3 << 30) 216#define PSC_I2SCFG_RT_MASK (3 << 30)
209#define PSC_I2SCFG_RT_FIFO1 (0 << 30) 217#define PSC_I2SCFG_RT_FIFO1 (0 << 30)
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
index 612ae90dbcb8..1a515b8c870f 100644
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ b/include/asm-mips/mach-db1x00/db1x00.h
@@ -146,51 +146,6 @@ typedef volatile struct
146 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) 146 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
147 147
148/* 148/*
149 * SD controller macros
150 */
151
152/* Detect card. */
153#define mmc_card_inserted(_n_, _res_) \
154 do { \
155 BCSR * const bcsr = (BCSR *)0xAE000000; \
156 unsigned long mmc_wp, board_specific; \
157 if ((_n_)) { \
158 mmc_wp = BCSR_BOARD_SD1_WP; \
159 } else { \
160 mmc_wp = BCSR_BOARD_SD0_WP; \
161 } \
162 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
163 if (!(board_specific & mmc_wp)) {/* low means card present */ \
164 *(int *)(_res_) = 1; \
165 } else { \
166 *(int *)(_res_) = 0; \
167 } \
168 } while (0)
169
170/*
171 * Apply power to card slot(s).
172 */
173#define mmc_power_on(_n_) \
174 do { \
175 BCSR * const bcsr = (BCSR *)0xAE000000; \
176 unsigned long mmc_pwr, mmc_wp, board_specific; \
177 if ((_n_)) { \
178 mmc_pwr = BCSR_BOARD_SD1_PWR; \
179 mmc_wp = BCSR_BOARD_SD1_WP; \
180 } else { \
181 mmc_pwr = BCSR_BOARD_SD0_PWR; \
182 mmc_wp = BCSR_BOARD_SD0_WP; \
183 } \
184 board_specific = au_readl((unsigned long)(&bcsr->specific)); \
185 if (!(board_specific & mmc_wp)) {/* low means card present */ \
186 board_specific |= mmc_pwr; \
187 au_writel(board_specific, (int)(&bcsr->specific)); \
188 au_sync(); \
189 } \
190 } while (0)
191
192
193/*
194 * NAND defines 149 * NAND defines
195 * 150 *
196 * Timing values as described in databook, * ns value stripped of the 151 * Timing values as described in databook, * ns value stripped of the
diff --git a/include/asm-mips/mach-mips/cpu-feature-overrides.h b/include/asm-mips/mach-malta/cpu-feature-overrides.h
index 7f3e3f9bd23a..7f3e3f9bd23a 100644
--- a/include/asm-mips/mach-mips/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-malta/cpu-feature-overrides.h
diff --git a/include/asm-mips/mach-mips/irq.h b/include/asm-mips/mach-malta/irq.h
index 9b9da26683c2..9b9da26683c2 100644
--- a/include/asm-mips/mach-mips/irq.h
+++ b/include/asm-mips/mach-malta/irq.h
diff --git a/include/asm-mips/mach-mips/kernel-entry-init.h b/include/asm-mips/mach-malta/kernel-entry-init.h
index 0b793e7bf67e..0b793e7bf67e 100644
--- a/include/asm-mips/mach-mips/kernel-entry-init.h
+++ b/include/asm-mips/mach-malta/kernel-entry-init.h
diff --git a/include/asm-mips/mach-mips/mach-gt64120.h b/include/asm-mips/mach-malta/mach-gt64120.h
index 0f863148f3b6..0f863148f3b6 100644
--- a/include/asm-mips/mach-mips/mach-gt64120.h
+++ b/include/asm-mips/mach-malta/mach-gt64120.h
diff --git a/include/asm-mips/mach-mips/mc146818rtc.h b/include/asm-mips/mach-malta/mc146818rtc.h
index ea612f37f614..ea612f37f614 100644
--- a/include/asm-mips/mach-mips/mc146818rtc.h
+++ b/include/asm-mips/mach-malta/mc146818rtc.h
diff --git a/include/asm-mips/mach-mips/war.h b/include/asm-mips/mach-malta/war.h
index 7c6931d5f45f..7c6931d5f45f 100644
--- a/include/asm-mips/mach-mips/war.h
+++ b/include/asm-mips/mach-malta/war.h
diff --git a/include/asm-mips/mach-jmr3927/ioremap.h b/include/asm-mips/mach-tx39xx/ioremap.h
index 29989ff10d66..93c6c04ffda3 100644
--- a/include/asm-mips/mach-jmr3927/ioremap.h
+++ b/include/asm-mips/mach-tx39xx/ioremap.h
@@ -1,13 +1,13 @@
1/* 1/*
2 * include/asm-mips/mach-jmr3927/ioremap.h 2 * include/asm-mips/mach-tx39xx/ioremap.h
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version. 7 * 2 of the License, or (at your option) any later version.
8 */ 8 */
9#ifndef __ASM_MACH_JMR3927_IOREMAP_H 9#ifndef __ASM_MACH_TX39XX_IOREMAP_H
10#define __ASM_MACH_JMR3927_IOREMAP_H 10#define __ASM_MACH_TX39XX_IOREMAP_H
11 11
12#include <linux/types.h> 12#include <linux/types.h>
13 13
@@ -35,4 +35,4 @@ static inline int plat_iounmap(const volatile void __iomem *addr)
35 return (unsigned long)addr >= TXX9_DIRECTMAP_BASE; 35 return (unsigned long)addr >= TXX9_DIRECTMAP_BASE;
36} 36}
37 37
38#endif /* __ASM_MACH_JMR3927_IOREMAP_H */ 38#endif /* __ASM_MACH_TX39XX_IOREMAP_H */
diff --git a/include/asm-mips/mach-jmr3927/mangle-port.h b/include/asm-mips/mach-tx39xx/mangle-port.h
index 11bffcd1043b..ef0b502fd8b7 100644
--- a/include/asm-mips/mach-jmr3927/mangle-port.h
+++ b/include/asm-mips/mach-tx39xx/mangle-port.h
@@ -1,7 +1,12 @@
1#ifndef __ASM_MACH_JMR3927_MANGLE_PORT_H 1#ifndef __ASM_MACH_TX39XX_MANGLE_PORT_H
2#define __ASM_MACH_JMR3927_MANGLE_PORT_H 2#define __ASM_MACH_TX39XX_MANGLE_PORT_H
3 3
4extern unsigned long __swizzle_addr_b(unsigned long port); 4#if defined(CONFIG_TOSHIBA_JMR3927)
5extern unsigned long (*__swizzle_addr_b)(unsigned long port);
6#define NEEDS_TXX9_SWIZZLE_ADDR_B
7#else
8#define __swizzle_addr_b(port) (port)
9#endif
5#define __swizzle_addr_w(port) (port) 10#define __swizzle_addr_w(port) (port)
6#define __swizzle_addr_l(port) (port) 11#define __swizzle_addr_l(port) (port)
7#define __swizzle_addr_q(port) (port) 12#define __swizzle_addr_q(port) (port)
@@ -15,4 +20,4 @@ extern unsigned long __swizzle_addr_b(unsigned long port);
15#define ioswabq(a, x) le64_to_cpu(x) 20#define ioswabq(a, x) le64_to_cpu(x)
16#define __mem_ioswabq(a, x) (x) 21#define __mem_ioswabq(a, x) (x)
17 22
18#endif /* __ASM_MACH_JMR3927_MANGLE_PORT_H */ 23#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-jmr3927/war.h b/include/asm-mips/mach-tx39xx/war.h
index 1ff55fb3fbcb..433814616359 100644
--- a/include/asm-mips/mach-jmr3927/war.h
+++ b/include/asm-mips/mach-tx39xx/war.h
@@ -5,8 +5,8 @@
5 * 5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> 6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */ 7 */
8#ifndef __ASM_MIPS_MACH_JMR3927_WAR_H 8#ifndef __ASM_MIPS_MACH_TX39XX_WAR_H
9#define __ASM_MIPS_MACH_JMR3927_WAR_H 9#define __ASM_MIPS_MACH_TX39XX_WAR_H
10 10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0 11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0 12#define R4600_V1_HIT_CACHEOP_WAR 0
@@ -22,4 +22,4 @@
22#define R10000_LLSC_WAR 0 22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0 23#define MIPS34K_MISSED_ITLB_WAR 0
24 24
25#endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */ 25#endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */
diff --git a/include/asm-mips/mach-vr41xx/irq.h b/include/asm-mips/mach-vr41xx/irq.h
index 848812296052..862058d3f81b 100644
--- a/include/asm-mips/mach-vr41xx/irq.h
+++ b/include/asm-mips/mach-vr41xx/irq.h
@@ -2,9 +2,6 @@
2#define __ASM_MACH_VR41XX_IRQ_H 2#define __ASM_MACH_VR41XX_IRQ_H
3 3
4#include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */ 4#include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */
5#ifdef CONFIG_NEC_CMBVR4133
6#include <asm/vr41xx/cmbvr4133.h> /* for I8259A_IRQ_BASE */
7#endif
8 5
9#include_next <irq.h> 6#include_next <irq.h>
10 7
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index 33407bee4e73..7f0b034dd9a5 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -27,12 +27,8 @@
27/* 27/*
28 * Display register base. 28 * Display register base.
29 */ 29 */
30#ifdef CONFIG_MIPS_SEAD
31#define ASCII_DISPLAY_POS_BASE 0x1f0005c0
32#else
33#define ASCII_DISPLAY_WORD_BASE 0x1f000410 30#define ASCII_DISPLAY_WORD_BASE 0x1f000410
34#define ASCII_DISPLAY_POS_BASE 0x1f000418 31#define ASCII_DISPLAY_POS_BASE 0x1f000418
35#endif
36 32
37 33
38/* 34/*
@@ -44,13 +40,8 @@
44/* 40/*
45 * Reset register. 41 * Reset register.
46 */ 42 */
47#ifdef CONFIG_MIPS_SEAD
48#define SOFTRES_REG 0x1e800050
49#define GORESET 0x4d
50#else
51#define SOFTRES_REG 0x1f000500 43#define SOFTRES_REG 0x1f000500
52#define GORESET 0x42 44#define GORESET 0x42
53#endif
54 45
55/* 46/*
56 * Revision register. 47 * Revision register.
diff --git a/include/asm-mips/namei.h b/include/asm-mips/namei.h
index c94d12d1f868..a6605a752469 100644
--- a/include/asm-mips/namei.h
+++ b/include/asm-mips/namei.h
@@ -1,26 +1,11 @@
1#ifndef _ASM_NAMEI_H 1#ifndef _ASM_NAMEI_H
2#define _ASM_NAMEI_H 2#define _ASM_NAMEI_H
3 3
4#include <linux/personality.h> 4/*
5#include <linux/stddef.h> 5 * This dummy routine maybe changed to something useful
6 * for /usr/gnemul/ emulation stuff.
7 */
6 8
7#define IRIX_EMUL "/usr/gnemul/irix/" 9#define __emul_prefix() NULL
8#define RISCOS_EMUL "/usr/gnemul/riscos/"
9
10static inline char *__emul_prefix(void)
11{
12 switch (current->personality) {
13 case PER_IRIX32:
14 case PER_IRIXN32:
15 case PER_IRIX64:
16 return IRIX_EMUL;
17
18 case PER_RISCOS:
19 return RISCOS_EMUL;
20
21 default:
22 return NULL;
23 }
24}
25 10
26#endif /* _ASM_NAMEI_H */ 11#endif /* _ASM_NAMEI_H */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
index 301ff2f28012..d3be83436070 100644
--- a/include/asm-mips/pci.h
+++ b/include/asm-mips/pci.h
@@ -172,4 +172,7 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
172 return channel ? 15 : 14; 172 return channel ? 15 : 14;
173} 173}
174 174
175extern int pci_probe_only;
176extern unsigned int pcibios_max_latency;
177
175#endif /* _ASM_PCI_H */ 178#endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/prctl.h b/include/asm-mips/prctl.h
deleted file mode 100644
index 8121a9a75bfd..000000000000
--- a/include/asm-mips/prctl.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * IRIX prctl interface
3 *
4 * The IRIX kernel maps a page at PRDA_ADDRESS with the
5 * contents of prda and fills it the bits on prda_sys.
6 */
7
8#ifndef __PRCTL_H__
9#define __PRCTL_H__
10
11#define PRDA_ADDRESS 0x200000L
12#define PRDA ((struct prda *) PRDA_ADDRESS)
13
14struct prda_sys {
15 pid_t t_pid;
16 u32 t_hint;
17 u32 t_dlactseq;
18 u32 t_fpflags;
19 u32 t_prid; /* processor type, $prid CP0 register */
20 u32 t_dlendseq;
21 u64 t_unused1[5];
22 pid_t t_rpid;
23 s32 t_resched;
24 u32 t_unused[8];
25 u32 t_cpu; /* current/last cpu */
26
27 /* FIXME: The signal information, not supported by Linux now */
28 u32 t_flags; /* if true, then the sigprocmask is in userspace */
29 u32 t_sigprocmask [1]; /* the sigprocmask */
30};
31
32struct prda {
33 char fill [0xe00];
34 struct prda_sys prda_sys;
35};
36
37#define t_sys prda_sys
38
39ptrdiff_t prctl(int op, int v1, int v2);
40
41#endif
diff --git a/include/asm-mips/setup.h b/include/asm-mips/setup.h
index 70009a902639..883f59bfa097 100644
--- a/include/asm-mips/setup.h
+++ b/include/asm-mips/setup.h
@@ -3,4 +3,6 @@
3 3
4#define COMMAND_LINE_SIZE 256 4#define COMMAND_LINE_SIZE 256
5 5
6extern void setup_early_printk(void);
7
6#endif /* __SETUP_H */ 8#endif /* __SETUP_H */
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
index 7a28989f7ee3..bee5153aca48 100644
--- a/include/asm-mips/signal.h
+++ b/include/asm-mips/signal.h
@@ -119,9 +119,6 @@ struct sigaction {
119 119
120struct k_sigaction { 120struct k_sigaction {
121 struct sigaction sa; 121 struct sigaction sa;
122#ifdef CONFIG_BINFMT_IRIX
123 void (*sa_restorer)(void);
124#endif
125}; 122};
126 123
127/* IRIX compatible stack_t */ 124/* IRIX compatible stack_t */
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index 84fef1aeec0c..0ff5b523ea77 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -35,16 +35,6 @@ extern int __cpu_logical_map[NR_CPUS];
35 35
36#define NO_PROC_ID (-1) 36#define NO_PROC_ID (-1)
37 37
38struct call_data_struct {
39 void (*func)(void *);
40 void *info;
41 atomic_t started;
42 atomic_t finished;
43 int wait;
44};
45
46extern struct call_data_struct *call_data;
47
48#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ 38#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
49#define SMP_CALL_FUNCTION 0x2 39#define SMP_CALL_FUNCTION 0x2
50 40
@@ -67,4 +57,7 @@ static inline void smp_send_reschedule(int cpu)
67 57
68extern asmlinkage void smp_call_function_interrupt(void); 58extern asmlinkage void smp_call_function_interrupt(void);
69 59
60extern void arch_send_call_function_single_ipi(int cpu);
61extern void arch_send_call_function_ipi(cpumask_t mask);
62
70#endif /* __ASM_SMP_H */ 63#endif /* __ASM_SMP_H */
diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h
index e5dbde625ec2..90ff2f497c50 100644
--- a/include/asm-mips/traps.h
+++ b/include/asm-mips/traps.h
@@ -24,6 +24,5 @@ extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
24extern void (*board_nmi_handler_setup)(void); 24extern void (*board_nmi_handler_setup)(void);
25extern void (*board_ejtag_handler_setup)(void); 25extern void (*board_ejtag_handler_setup)(void);
26extern void (*board_bind_eic_interrupt)(int irq, int regset); 26extern void (*board_bind_eic_interrupt)(int irq, int regset);
27extern void (*board_watchpoint_handler)(struct pt_regs *regs);
28 27
29#endif /* _ASM_TRAPS_H */ 28#endif /* _ASM_TRAPS_H */
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
deleted file mode 100644
index 193e80a17c12..000000000000
--- a/include/asm-mips/tx4927/tx4927.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2006 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_TX4927_TX4927_H
28#define __ASM_TX4927_TX4927_H
29
30#include <asm/txx9irq.h>
31
32#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
33#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
34
35#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE
36#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
37
38
39#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
40#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1)
41#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2)
42#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7)
43
44#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3)
45
46#endif /* __ASM_TX4927_TX4927_H */
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
deleted file mode 100644
index 0be77df70f2b..000000000000
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ /dev/null
@@ -1,268 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000-2001 Toshiba Corporation
7 */
8#ifndef __ASM_TX4927_TX4927_PCI_H
9#define __ASM_TX4927_TX4927_PCI_H
10
11#define TX4927_CCFG_TOE 0x00004000
12#define TX4927_CCFG_WR 0x00008000
13#define TX4927_CCFG_TINTDIS 0x01000000
14
15#define TX4927_PCIMEM 0x08000000
16#define TX4927_PCIMEM_SIZE 0x08000000
17#define TX4927_PCIIO 0x16000000
18#define TX4927_PCIIO_SIZE 0x01000000
19
20#define TX4927_SDRAMC_REG 0xff1f8000
21#define TX4927_EBUSC_REG 0xff1f9000
22#define TX4927_PCIC_REG 0xff1fd000
23#define TX4927_CCFG_REG 0xff1fe000
24#define TX4927_IRC_REG 0xff1ff600
25#define TX4927_NR_TMR 3
26#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
27#define TX4927_CE3 0x17f00000 /* 1M */
28#define TX4927_PCIRESET_ADDR 0xbc00f006
29#define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020)
30
31#define TX4927_IMSTAT_ADDR(n) (KSEG1 + TX4927_CE3 + 0x0004001a + (n))
32#define tx4927_imstat_ptr(n) \
33 ((volatile unsigned char *)TX4927_IMSTAT_ADDR(n))
34
35/* bits for ISTAT3/IMASK3/IMSTAT3 */
36#define TX4927_INT3B_PCID 0
37#define TX4927_INT3B_PCIC 1
38#define TX4927_INT3B_PCIB 2
39#define TX4927_INT3B_PCIA 3
40#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
41#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
42#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
43#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
44
45/* bits for PCI_CLK (S6) */
46#define TX4927_PCI_CLK_HOST 0x80
47#define TX4927_PCI_CLK_MASK (0x0f << 3)
48#define TX4927_PCI_CLK_33 (0x01 << 3)
49#define TX4927_PCI_CLK_25 (0x04 << 3)
50#define TX4927_PCI_CLK_66 (0x09 << 3)
51#define TX4927_PCI_CLK_50 (0x0c << 3)
52#define TX4927_PCI_CLK_ACK 0x04
53#define TX4927_PCI_CLK_ACE 0x02
54#define TX4927_PCI_CLK_ENDIAN 0x01
55#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
56#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
57
58#define TX4927_IR_PCIC 16
59#define TX4927_IR_PCIERR 22
60#define TX4927_IR_PCIPMA 23
61#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
62#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
63#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
64#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
65#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
66#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
67#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
68
69#ifdef _LANGUAGE_ASSEMBLY
70#define _CONST64(c) c
71#else
72#define _CONST64(c) c##ull
73
74#include <asm/byteorder.h>
75
76#define tx4927_pcireset_ptr \
77 ((volatile unsigned char *)TX4927_PCIRESET_ADDR)
78#define tx4927_pci_clk_ptr \
79 ((volatile unsigned char *)TX4927_PCI_CLK_ADDR)
80
81struct tx4927_sdramc_reg {
82 volatile unsigned long long cr[4];
83 volatile unsigned long long unused0[4];
84 volatile unsigned long long tr;
85 volatile unsigned long long unused1[2];
86 volatile unsigned long long cmd;
87};
88
89struct tx4927_ebusc_reg {
90 volatile unsigned long long cr[8];
91};
92
93struct tx4927_ccfg_reg {
94 volatile unsigned long long ccfg;
95 volatile unsigned long long crir;
96 volatile unsigned long long pcfg;
97 volatile unsigned long long tear;
98 volatile unsigned long long clkctr;
99 volatile unsigned long long unused0;
100 volatile unsigned long long garbc;
101 volatile unsigned long long unused1;
102 volatile unsigned long long unused2;
103 volatile unsigned long long ramp;
104};
105
106struct tx4927_pcic_reg {
107 volatile unsigned long pciid;
108 volatile unsigned long pcistatus;
109 volatile unsigned long pciccrev;
110 volatile unsigned long pcicfg1;
111 volatile unsigned long p2gm0plbase; /* +10 */
112 volatile unsigned long p2gm0pubase;
113 volatile unsigned long p2gm1plbase;
114 volatile unsigned long p2gm1pubase;
115 volatile unsigned long p2gm2pbase; /* +20 */
116 volatile unsigned long p2giopbase;
117 volatile unsigned long unused0;
118 volatile unsigned long pcisid;
119 volatile unsigned long unused1; /* +30 */
120 volatile unsigned long pcicapptr;
121 volatile unsigned long unused2;
122 volatile unsigned long pcicfg2;
123 volatile unsigned long g2ptocnt; /* +40 */
124 volatile unsigned long unused3[15];
125 volatile unsigned long g2pstatus; /* +80 */
126 volatile unsigned long g2pmask;
127 volatile unsigned long pcisstatus;
128 volatile unsigned long pcimask;
129 volatile unsigned long p2gcfg; /* +90 */
130 volatile unsigned long p2gstatus;
131 volatile unsigned long p2gmask;
132 volatile unsigned long p2gccmd;
133 volatile unsigned long unused4[24]; /* +a0 */
134 volatile unsigned long pbareqport; /* +100 */
135 volatile unsigned long pbacfg;
136 volatile unsigned long pbastatus;
137 volatile unsigned long pbamask;
138 volatile unsigned long pbabm; /* +110 */
139 volatile unsigned long pbacreq;
140 volatile unsigned long pbacgnt;
141 volatile unsigned long pbacstate;
142 volatile unsigned long long g2pmgbase[3]; /* +120 */
143 volatile unsigned long long g2piogbase;
144 volatile unsigned long g2pmmask[3]; /* +140 */
145 volatile unsigned long g2piomask;
146 volatile unsigned long long g2pmpbase[3]; /* +150 */
147 volatile unsigned long long g2piopbase;
148 volatile unsigned long pciccfg; /* +170 */
149 volatile unsigned long pcicstatus;
150 volatile unsigned long pcicmask;
151 volatile unsigned long unused5;
152 volatile unsigned long long p2gmgbase[3]; /* +180 */
153 volatile unsigned long long p2giogbase;
154 volatile unsigned long g2pcfgadrs; /* +1a0 */
155 volatile unsigned long g2pcfgdata;
156 volatile unsigned long unused6[8];
157 volatile unsigned long g2pintack;
158 volatile unsigned long g2pspc;
159 volatile unsigned long unused7[12]; /* +1d0 */
160 volatile unsigned long long pdmca; /* +200 */
161 volatile unsigned long long pdmga;
162 volatile unsigned long long pdmpa;
163 volatile unsigned long long pdmcut;
164 volatile unsigned long long pdmcnt; /* +220 */
165 volatile unsigned long long pdmsts;
166 volatile unsigned long long unused8[2];
167 volatile unsigned long long pdmdb[4]; /* +240 */
168 volatile unsigned long long pdmtdh; /* +260 */
169 volatile unsigned long long pdmdms;
170};
171
172#endif /* _LANGUAGE_ASSEMBLY */
173
174/*
175 * PCIC
176 */
177
178/* bits for G2PSTATUS/G2PMASK */
179#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
180#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
181#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
182
183/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
184#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
185
186/* bits for PBACFG */
187#define TX4927_PCIC_PBACFG_RPBA 0x00000004
188#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
189#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
190
191/* bits for G2PMnGBASE */
192#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
193#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
194
195/* bits for G2PIOGBASE */
196#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
197#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
198
199/* bits for PCICSTATUS/PCICMASK */
200#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
201
202/* bits for PCICCFG */
203#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
204#define TX4927_PCIC_PCICCFG_HRST 0x00000800
205#define TX4927_PCIC_PCICCFG_SRST 0x00000400
206#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
207#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
208#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
209#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
210#define TX4927_PCIC_PCICCFG_IISE 0x00000020
211#define TX4927_PCIC_PCICCFG_ATR 0x00000010
212#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
213
214/* bits for P2GMnGBASE */
215#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
216#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
217#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
218
219/* bits for P2GIOGBASE */
220#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
221#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
222#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
223
224#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
225#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
226
227/*
228 * CCFG
229 */
230/* CCFG : Chip Configuration */
231#define TX4927_CCFG_PCI66 0x00800000
232#define TX4927_CCFG_PCIMIDE 0x00400000
233#define TX4927_CCFG_PCIXARB 0x00002000
234#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
235#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
236#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
237#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
238#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
239
240#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
241#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
242#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
243#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
244#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
245#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
246#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
247#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
248#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
249
250/* PCFG : Pin Configuration */
251#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
252#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
253
254/* CLKCTR : Clock Control */
255#define TX4927_CLKCTR_PCICKD 0x00400000
256#define TX4927_CLKCTR_PCIRST 0x00000040
257
258
259#ifndef _LANGUAGE_ASSEMBLY
260
261#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
262#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
263#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
264#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
265
266#endif /* _LANGUAGE_ASSEMBLY */
267
268#endif /* __ASM_TX4927_TX4927_PCI_H */
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
new file mode 100644
index 000000000000..d8756660523d
--- /dev/null
+++ b/include/asm-mips/txx9/generic.h
@@ -0,0 +1,41 @@
1/*
2 * linux/include/asm-mips/txx9/generic.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 */
8#ifndef __ASM_TXX9_GENERIC_H
9#define __ASM_TXX9_GENERIC_H
10
11#include <linux/init.h>
12#include <linux/ioport.h> /* for struct resource */
13
14extern struct resource txx9_ce_res[];
15extern char txx9_pcode_str[8];
16void txx9_reg_res_init(unsigned int pcode, unsigned long base,
17 unsigned long size);
18
19extern unsigned int txx9_master_clock;
20extern unsigned int txx9_cpu_clock;
21extern unsigned int txx9_gbus_clock;
22
23struct pci_dev;
24struct txx9_board_vec {
25 const char *system;
26 void (*prom_init)(void);
27 void (*mem_setup)(void);
28 void (*irq_setup)(void);
29 void (*time_init)(void);
30 void (*arch_init)(void);
31 void (*device_init)(void);
32#ifdef CONFIG_PCI
33 int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
34#endif
35};
36extern struct txx9_board_vec *txx9_board_vec;
37extern int (*txx9_irq_dispatch)(int pending);
38void prom_init_cmdline(void);
39char *prom_getcmdline(void);
40
41#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/txx9/jmr3927.h
index a162268f17df..d6eb1b6a54eb 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/txx9/jmr3927.h
@@ -7,10 +7,10 @@
7 * 7 *
8 * Copyright (C) 2000-2001 Toshiba Corporation 8 * Copyright (C) 2000-2001 Toshiba Corporation
9 */ 9 */
10#ifndef __ASM_TX3927_JMR3927_H 10#ifndef __ASM_TXX9_JMR3927_H
11#define __ASM_TX3927_JMR3927_H 11#define __ASM_TXX9_JMR3927_H
12 12
13#include <asm/jmr3927/tx3927.h> 13#include <asm/txx9/tx3927.h>
14#include <asm/addrspace.h> 14#include <asm/addrspace.h>
15#include <asm/system.h> 15#include <asm/system.h>
16#include <asm/txx9irq.h> 16#include <asm/txx9irq.h>
@@ -174,4 +174,9 @@
174 * INT[3:0] 174 * INT[3:0]
175 */ 175 */
176 176
177#endif /* __ASM_TX3927_JMR3927_H */ 177void jmr3927_prom_init(void);
178void jmr3927_irq_setup(void);
179struct pci_dev;
180int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
181
182#endif /* __ASM_TXX9_JMR3927_H */
diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h
new file mode 100644
index 000000000000..d89a45091e24
--- /dev/null
+++ b/include/asm-mips/txx9/pci.h
@@ -0,0 +1,36 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 */
6#ifndef __ASM_TXX9_PCI_H
7#define __ASM_TXX9_PCI_H
8
9#include <linux/pci.h>
10
11extern struct pci_controller txx9_primary_pcic;
12struct pci_controller *
13txx9_alloc_pci_controller(struct pci_controller *pcic,
14 unsigned long mem_base, unsigned long mem_size,
15 unsigned long io_base, unsigned long io_size);
16
17int txx9_pci66_check(struct pci_controller *hose, int top_bus,
18 int current_bus);
19extern int txx9_pci_mem_high __initdata;
20
21extern int txx9_pci_option;
22#define TXX9_PCI_OPT_PICMG 0x0002
23#define TXX9_PCI_OPT_CLK_33 0x0008
24#define TXX9_PCI_OPT_CLK_66 0x0010
25#define TXX9_PCI_OPT_CLK_MASK \
26 (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
27#define TXX9_PCI_OPT_CLK_AUTO TXX9_PCI_OPT_CLK_MASK
28
29enum txx9_pci_err_action {
30 TXX9_PCI_ERR_REPORT,
31 TXX9_PCI_ERR_IGNORE,
32 TXX9_PCI_ERR_PANIC,
33};
34extern enum txx9_pci_err_action txx9_pci_err_action;
35
36#endif /* __ASM_TXX9_PCI_H */
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
index b188a659ce02..bf194589216f 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/txx9/rbtx4927.h
@@ -24,18 +24,42 @@
24 * with this program; if not, write to the Free Software Foundation, Inc., 24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */ 26 */
27#ifndef __ASM_TX4927_TOSHIBA_RBTX4927_H 27#ifndef __ASM_TXX9_RBTX4927_H
28#define __ASM_TX4927_TOSHIBA_RBTX4927_H 28#define __ASM_TXX9_RBTX4927_H
29 29
30#include <asm/tx4927/tx4927.h> 30#include <asm/txx9/tx4927.h>
31#ifdef CONFIG_PCI 31
32#include <asm/tx4927/tx4927_pci.h> 32#define RBTX4927_PCIMEM 0x08000000
33#endif 33#define RBTX4927_PCIMEM_SIZE 0x08000000
34#define RBTX4927_PCIIO 0x16000000
35#define RBTX4927_PCIIO_SIZE 0x01000000
36
37#define rbtx4927_pcireset_addr ((__u8 __iomem *)0xbc00f006UL)
38
39/* bits for ISTAT/IMASK/IMSTAT */
40#define RBTX4927_INTB_PCID 0
41#define RBTX4927_INTB_PCIC 1
42#define RBTX4927_INTB_PCIB 2
43#define RBTX4927_INTB_PCIA 3
44#define RBTX4927_INTF_PCID (1 << RBTX4927_INTB_PCID)
45#define RBTX4927_INTF_PCIC (1 << RBTX4927_INTB_PCIC)
46#define RBTX4927_INTF_PCIB (1 << RBTX4927_INTB_PCIB)
47#define RBTX4927_INTF_PCIA (1 << RBTX4927_INTB_PCIA)
48
49#define RBTX4927_NR_IRQ_IOC 8 /* IOC */
50
51#define RBTX4927_IRQ_IOC (TXX9_IRQ_BASE + TX4927_NUM_IR)
52#define RBTX4927_IRQ_IOC_PCID (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
53#define RBTX4927_IRQ_IOC_PCIC (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
54#define RBTX4927_IRQ_IOC_PCIB (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
55#define RBTX4927_IRQ_IOC_PCIA (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
56
57#define RBTX4927_IRQ_IOCINT (TXX9_IRQ_BASE + TX4927_IR_INT(1))
34 58
35#ifdef CONFIG_PCI 59#ifdef CONFIG_PCI
36#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO 60#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
37#else 61#else
38#define TBTX4927_ISA_IO_OFFSET 0 62#define RBTX4927_ISA_IO_OFFSET 0
39#endif 63#endif
40 64
41#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL 65#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL
@@ -44,10 +68,12 @@
44#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL 68#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
45#define RBTX4927_SW_RESET_ENABLE_SET 0x01 69#define RBTX4927_SW_RESET_ENABLE_SET 0x01
46 70
71#define RBTX4927_RTL_8019_BASE (0x1c020280 - RBTX4927_ISA_IO_OFFSET)
72#define RBTX4927_RTL_8019_IRQ (TXX9_IRQ_BASE + TX4927_IR_INT(3))
47 73
48#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) 74void rbtx4927_prom_init(void);
49#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5) 75void rbtx4927_irq_setup(void);
50 76struct pci_dev;
51int toshiba_rbtx4927_irq_nested(int sw_irq); 77int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
52 78
53#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */ 79#endif /* __ASM_TXX9_RBTX4927_H */
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h
index dfed7beb533f..2f5d5e705a41 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/txx9/rbtx4938.h
@@ -1,5 +1,4 @@
1/* 1/*
2 * linux/include/asm-mips/tx4938/rbtx4938.h
3 * Definitions for TX4937/TX4938 2 * Definitions for TX4937/TX4938
4 * 3 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the 4 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
@@ -9,12 +8,12 @@
9 * 8 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) 9 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */ 10 */
12#ifndef __ASM_TX_BOARDS_RBTX4938_H 11#ifndef __ASM_TXX9_RBTX4938_H
13#define __ASM_TX_BOARDS_RBTX4938_H 12#define __ASM_TXX9_RBTX4938_H
14 13
15#include <asm/addrspace.h> 14#include <asm/addrspace.h>
16#include <asm/tx4938/tx4938.h>
17#include <asm/txx9irq.h> 15#include <asm/txx9irq.h>
16#include <asm/txx9/tx4938.h>
18 17
19/* CS */ 18/* CS */
20#define RBTX4938_CE0 0x1c000000 /* 64M */ 19#define RBTX4938_CE0 0x1c000000 /* 64M */
@@ -102,35 +101,12 @@
102 * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new 101 * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
103 * IRQ hardware is supported. 102 * IRQ hardware is supported.
104 */ 103 */
105#define RBTX4938_NR_IRQ_LOCAL 8
106#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */
107#define RBTX4938_NR_IRQ_IOC 8 104#define RBTX4938_NR_IRQ_IOC 8
108 105
109#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE 106#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE
110#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) 107#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR)
111
112#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE
113#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
114#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2)
115#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2)
116#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0)
117#define TX4938_IRQ_USER1 (TX4938_IRQ_CP0_BEG+1)
118#define TX4938_IRQ_CPU_TIMER (TX4938_IRQ_CP0_BEG+7)
119
120#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG 0
121#define TOSHIBA_RBTX4938_IRQ_IOC_RAW_END 7
122
123#define TOSHIBA_RBTX4938_IRQ_IOC_BEG ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_BEG) /* 56 */
124#define TOSHIBA_RBTX4938_IRQ_IOC_END ((TX4938_IRQ_PIC_END+1)+TOSHIBA_RBTX4938_IRQ_IOC_RAW_END) /* 63 */
125#define RBTX4938_IRQ_LOCAL TX4938_IRQ_CP0_BEG
126#define RBTX4938_IRQ_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_NR_IRQ_LOCAL)
127#define RBTX4938_IRQ_IOC (RBTX4938_IRQ_IRC + RBTX4938_NR_IRQ_IRC)
128#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC) 108#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
129 109
130#define RBTX4938_IRQ_LOCAL_SOFT0 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT0)
131#define RBTX4938_IRQ_LOCAL_SOFT1 (RBTX4938_IRQ_LOCAL + RBTX4938_SOFT_INT1)
132#define RBTX4938_IRQ_LOCAL_IRC (RBTX4938_IRQ_LOCAL + RBTX4938_IRC_INT)
133#define RBTX4938_IRQ_LOCAL_TIMER (RBTX4938_IRQ_LOCAL + RBTX4938_TIMER_INT)
134#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR) 110#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
135#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR) 111#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
136#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n)) 112#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
@@ -158,11 +134,16 @@
158 134
159 135
160/* IOC (PCI, etc) */ 136/* IOC (PCI, etc) */
161#define RBTX4938_IRQ_IOCINT (TX4938_IRQ_NEST_EXT_ON_PIC) 137#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0))
162/* Onboard 10M Ether */ 138/* Onboard 10M Ether */
163#define RBTX4938_IRQ_ETHER (TX4938_IRQ_NEST_EXT_ON_PIC + 1) 139#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1))
164 140
165#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) 141#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
166#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) 142#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
167 143
168#endif /* __ASM_TX_BOARDS_RBTX4938_H */ 144void rbtx4938_prom_init(void);
145void rbtx4938_irq_setup(void);
146struct pci_dev;
147int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
148
149#endif /* __ASM_TXX9_RBTX4938_H */
diff --git a/include/asm-mips/tx4927/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h
index 5d93bab51254..9375e4fc2289 100644
--- a/include/asm-mips/tx4927/smsc_fdc37m81x.h
+++ b/include/asm-mips/txx9/smsc_fdc37m81x.h
@@ -1,6 +1,4 @@
1/* 1/*
2 * linux/include/asm-mips/tx4927/smsc_fdc37m81x.h
3 *
4 * Interface for smsc fdc48m81x Super IO chip 2 * Interface for smsc fdc48m81x Super IO chip
5 * 3 *
6 * Author: MontaVista Software, Inc. source@mvista.com 4 * Author: MontaVista Software, Inc. source@mvista.com
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/txx9/spi.h
index 6a60c83e152b..ddfb2a0dc432 100644
--- a/include/asm-mips/tx4938/spi.h
+++ b/include/asm-mips/txx9/spi.h
@@ -1,5 +1,4 @@
1/* 1/*
2 * linux/include/asm-mips/tx4938/spi.h
3 * Definitions for TX4937/TX4938 SPI 2 * Definitions for TX4937/TX4938 SPI
4 * 3 *
5 * Copyright (C) 2000-2001 Toshiba Corporation 4 * Copyright (C) 2000-2001 Toshiba Corporation
@@ -11,10 +10,10 @@
11 * 10 *
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) 11 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
13 */ 12 */
14#ifndef __ASM_TX_BOARDS_TX4938_SPI_H 13#ifndef __ASM_TXX9_SPI_H
15#define __ASM_TX_BOARDS_TX4938_SPI_H 14#define __ASM_TXX9_SPI_H
16 15
17extern int spi_eeprom_register(int chipid); 16extern int spi_eeprom_register(int chipid);
18extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); 17extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
19 18
20#endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ 19#endif /* __ASM_TXX9_SPI_H */
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/txx9/tx3927.h
index fb580333c102..ca414c7624e1 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/txx9/tx3927.h
@@ -5,10 +5,10 @@
5 * 5 *
6 * Copyright (C) 2000 Toshiba Corporation 6 * Copyright (C) 2000 Toshiba Corporation
7 */ 7 */
8#ifndef __ASM_TX3927_H 8#ifndef __ASM_TXX9_TX3927_H
9#define __ASM_TX3927_H 9#define __ASM_TXX9_TX3927_H
10 10
11#include <asm/jmr3927/txx927.h> 11#include <asm/txx9/txx927.h>
12 12
13#define TX3927_SDRAMC_REG 0xfffe8000 13#define TX3927_SDRAMC_REG 0xfffe8000
14#define TX3927_ROMC_REG 0xfffe9000 14#define TX3927_ROMC_REG 0xfffe9000
@@ -316,4 +316,8 @@ struct tx3927_ccfg_reg {
316#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch)) 316#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
317#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG) 317#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
318 318
319#endif /* __ASM_TX3927_H */ 319struct pci_controller;
320void __init tx3927_pcic_setup(struct pci_controller *channel,
321 unsigned long sdram_size, int extarb);
322
323#endif /* __ASM_TXX9_TX3927_H */
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
new file mode 100644
index 000000000000..46d60afc038b
--- /dev/null
+++ b/include/asm-mips/txx9/tx4927.h
@@ -0,0 +1,219 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2006 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_TXX9_TX4927_H
28#define __ASM_TXX9_TX4927_H
29
30#include <linux/types.h>
31#include <linux/io.h>
32#include <asm/txx9irq.h>
33#include <asm/txx9/tx4927pcic.h>
34
35#define TX4927_SDRAMC_REG 0xff1f8000
36#define TX4927_EBUSC_REG 0xff1f9000
37#define TX4927_PCIC_REG 0xff1fd000
38#define TX4927_CCFG_REG 0xff1fe000
39#define TX4927_IRC_REG 0xff1ff600
40#define TX4927_NR_TMR 3
41#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
42
43#define TX4927_IR_INT(n) (2 + (n))
44#define TX4927_IR_SIO(n) (8 + (n))
45#define TX4927_IR_PCIC 16
46#define TX4927_IR_PCIERR 22
47#define TX4927_NUM_IR 32
48
49#define TX4927_IRC_INT 2 /* IP[2] in Status register */
50
51struct tx4927_sdramc_reg {
52 volatile unsigned long long cr[4];
53 volatile unsigned long long unused0[4];
54 volatile unsigned long long tr;
55 volatile unsigned long long unused1[2];
56 volatile unsigned long long cmd;
57};
58
59struct tx4927_ebusc_reg {
60 volatile unsigned long long cr[8];
61};
62
63struct tx4927_ccfg_reg {
64 u64 ccfg;
65 u64 crir;
66 u64 pcfg;
67 u64 toea;
68 u64 clkctr;
69 u64 unused0;
70 u64 garbc;
71 u64 unused1;
72 u64 unused2;
73 u64 ramp;
74};
75
76/*
77 * CCFG
78 */
79/* CCFG : Chip Configuration */
80#define TX4927_CCFG_WDRST 0x0000020000000000ULL
81#define TX4927_CCFG_WDREXEN 0x0000010000000000ULL
82#define TX4927_CCFG_BCFG_MASK 0x000000ff00000000ULL
83#define TX4927_CCFG_TINTDIS 0x01000000
84#define TX4927_CCFG_PCI66 0x00800000
85#define TX4927_CCFG_PCIMODE 0x00400000
86#define TX4927_CCFG_DIVMODE_MASK 0x000e0000
87#define TX4927_CCFG_DIVMODE_8 (0x0 << 17)
88#define TX4927_CCFG_DIVMODE_12 (0x1 << 17)
89#define TX4927_CCFG_DIVMODE_16 (0x2 << 17)
90#define TX4927_CCFG_DIVMODE_10 (0x3 << 17)
91#define TX4927_CCFG_DIVMODE_2 (0x4 << 17)
92#define TX4927_CCFG_DIVMODE_3 (0x5 << 17)
93#define TX4927_CCFG_DIVMODE_4 (0x6 << 17)
94#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
95#define TX4927_CCFG_BEOW 0x00010000
96#define TX4927_CCFG_WR 0x00008000
97#define TX4927_CCFG_TOE 0x00004000
98#define TX4927_CCFG_PCIARB 0x00002000
99#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
100#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
101#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
102#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
103#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
104#define TX4927_CCFG_SYSSP_MASK 0x000000c0
105#define TX4927_CCFG_ENDIAN 0x00000004
106#define TX4927_CCFG_HALT 0x00000002
107#define TX4927_CCFG_ACEHOLD 0x00000001
108#define TX4927_CCFG_W1CBITS (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
109
110/* PCFG : Pin Configuration */
111#define TX4927_PCFG_SDCLKDLY_MASK 0x30000000
112#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
113#define TX4927_PCFG_SYSCLKEN 0x08000000
114#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
115#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
116#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
117#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
118#define TX4927_PCFG_SEL2 0x00000200
119#define TX4927_PCFG_SEL1 0x00000100
120#define TX4927_PCFG_DMASEL_ALL 0x000000ff
121#define TX4927_PCFG_DMASEL0_MASK 0x00000003
122#define TX4927_PCFG_DMASEL1_MASK 0x0000000c
123#define TX4927_PCFG_DMASEL2_MASK 0x00000030
124#define TX4927_PCFG_DMASEL3_MASK 0x000000c0
125#define TX4927_PCFG_DMASEL0_DRQ0 0x00000000
126#define TX4927_PCFG_DMASEL0_SIO1 0x00000001
127#define TX4927_PCFG_DMASEL0_ACL0 0x00000002
128#define TX4927_PCFG_DMASEL0_ACL2 0x00000003
129#define TX4927_PCFG_DMASEL1_DRQ1 0x00000000
130#define TX4927_PCFG_DMASEL1_SIO1 0x00000004
131#define TX4927_PCFG_DMASEL1_ACL1 0x00000008
132#define TX4927_PCFG_DMASEL1_ACL3 0x0000000c
133#define TX4927_PCFG_DMASEL2_DRQ2 0x00000000 /* SEL2=0 */
134#define TX4927_PCFG_DMASEL2_SIO0 0x00000010 /* SEL2=0 */
135#define TX4927_PCFG_DMASEL2_ACL1 0x00000000 /* SEL2=1 */
136#define TX4927_PCFG_DMASEL2_ACL2 0x00000020 /* SEL2=1 */
137#define TX4927_PCFG_DMASEL2_ACL0 0x00000030 /* SEL2=1 */
138#define TX4927_PCFG_DMASEL3_DRQ3 0x00000000
139#define TX4927_PCFG_DMASEL3_SIO0 0x00000040
140#define TX4927_PCFG_DMASEL3_ACL3 0x00000080
141#define TX4927_PCFG_DMASEL3_ACL1 0x000000c0
142
143/* CLKCTR : Clock Control */
144#define TX4927_CLKCTR_ACLCKD 0x02000000
145#define TX4927_CLKCTR_PIOCKD 0x01000000
146#define TX4927_CLKCTR_DMACKD 0x00800000
147#define TX4927_CLKCTR_PCICKD 0x00400000
148#define TX4927_CLKCTR_TM0CKD 0x00100000
149#define TX4927_CLKCTR_TM1CKD 0x00080000
150#define TX4927_CLKCTR_TM2CKD 0x00040000
151#define TX4927_CLKCTR_SIO0CKD 0x00020000
152#define TX4927_CLKCTR_SIO1CKD 0x00010000
153#define TX4927_CLKCTR_ACLRST 0x00000200
154#define TX4927_CLKCTR_PIORST 0x00000100
155#define TX4927_CLKCTR_DMARST 0x00000080
156#define TX4927_CLKCTR_PCIRST 0x00000040
157#define TX4927_CLKCTR_TM0RST 0x00000010
158#define TX4927_CLKCTR_TM1RST 0x00000008
159#define TX4927_CLKCTR_TM2RST 0x00000004
160#define TX4927_CLKCTR_SIO0RST 0x00000002
161#define TX4927_CLKCTR_SIO1RST 0x00000001
162
163#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
164#define tx4927_pcicptr \
165 ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
166#define tx4927_ccfgptr \
167 ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
168#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
169
170/* utilities */
171static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
172{
173#ifdef CONFIG_32BIT
174 unsigned long flags;
175 local_irq_save(flags);
176#endif
177 ____raw_writeq(____raw_readq(adr) & ~bits, adr);
178#ifdef CONFIG_32BIT
179 local_irq_restore(flags);
180#endif
181}
182static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
183{
184#ifdef CONFIG_32BIT
185 unsigned long flags;
186 local_irq_save(flags);
187#endif
188 ____raw_writeq(____raw_readq(adr) | bits, adr);
189#ifdef CONFIG_32BIT
190 local_irq_restore(flags);
191#endif
192}
193
194/* These functions are not interrupt safe. */
195static inline void tx4927_ccfg_clear(__u64 bits)
196{
197 ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
198 & ~(TX4927_CCFG_W1CBITS | bits),
199 &tx4927_ccfgptr->ccfg);
200}
201static inline void tx4927_ccfg_set(__u64 bits)
202{
203 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
204 & ~TX4927_CCFG_W1CBITS) | bits,
205 &tx4927_ccfgptr->ccfg);
206}
207static inline void tx4927_ccfg_change(__u64 change, __u64 new)
208{
209 ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
210 & ~(TX4927_CCFG_W1CBITS | change)) |
211 new,
212 &tx4927_ccfgptr->ccfg);
213}
214
215int tx4927_report_pciclk(void);
216int tx4927_pciclk66_setup(void);
217void tx4927_irq_init(void);
218
219#endif /* __ASM_TXX9_TX4927_H */
diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h
new file mode 100644
index 000000000000..d61c3d09c4a2
--- /dev/null
+++ b/include/asm-mips/txx9/tx4927pcic.h
@@ -0,0 +1,199 @@
1/*
2 * include/asm-mips/txx9/tx4927pcic.h
3 * TX4927 PCI controller definitions.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#ifndef __ASM_TXX9_TX4927PCIC_H
10#define __ASM_TXX9_TX4927PCIC_H
11
12#include <linux/pci.h>
13
14struct tx4927_pcic_reg {
15 u32 pciid;
16 u32 pcistatus;
17 u32 pciccrev;
18 u32 pcicfg1;
19 u32 p2gm0plbase; /* +10 */
20 u32 p2gm0pubase;
21 u32 p2gm1plbase;
22 u32 p2gm1pubase;
23 u32 p2gm2pbase; /* +20 */
24 u32 p2giopbase;
25 u32 unused0;
26 u32 pcisid;
27 u32 unused1; /* +30 */
28 u32 pcicapptr;
29 u32 unused2;
30 u32 pcicfg2;
31 u32 g2ptocnt; /* +40 */
32 u32 unused3[15];
33 u32 g2pstatus; /* +80 */
34 u32 g2pmask;
35 u32 pcisstatus;
36 u32 pcimask;
37 u32 p2gcfg; /* +90 */
38 u32 p2gstatus;
39 u32 p2gmask;
40 u32 p2gccmd;
41 u32 unused4[24]; /* +a0 */
42 u32 pbareqport; /* +100 */
43 u32 pbacfg;
44 u32 pbastatus;
45 u32 pbamask;
46 u32 pbabm; /* +110 */
47 u32 pbacreq;
48 u32 pbacgnt;
49 u32 pbacstate;
50 u64 g2pmgbase[3]; /* +120 */
51 u64 g2piogbase;
52 u32 g2pmmask[3]; /* +140 */
53 u32 g2piomask;
54 u64 g2pmpbase[3]; /* +150 */
55 u64 g2piopbase;
56 u32 pciccfg; /* +170 */
57 u32 pcicstatus;
58 u32 pcicmask;
59 u32 unused5;
60 u64 p2gmgbase[3]; /* +180 */
61 u64 p2giogbase;
62 u32 g2pcfgadrs; /* +1a0 */
63 u32 g2pcfgdata;
64 u32 unused6[8];
65 u32 g2pintack;
66 u32 g2pspc;
67 u32 unused7[12]; /* +1d0 */
68 u64 pdmca; /* +200 */
69 u64 pdmga;
70 u64 pdmpa;
71 u64 pdmctr;
72 u64 pdmcfg; /* +220 */
73 u64 pdmsts;
74};
75
76/* bits for PCICMD */
77/* see PCI_COMMAND_XXX in linux/pci_regs.h */
78
79/* bits for PCISTAT */
80/* see PCI_STATUS_XXX in linux/pci_regs.h */
81
82/* bits for IOBA/MBA */
83/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
84
85/* bits for G2PSTATUS/G2PMASK */
86#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
87#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
88#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
89
90/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
91#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
92
93/* bits for PBACFG */
94#define TX4927_PCIC_PBACFG_FIXPA 0x00000008
95#define TX4927_PCIC_PBACFG_RPBA 0x00000004
96#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
97#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
98
99/* bits for PBASTATUS/PBAMASK */
100#define TX4927_PCIC_PBASTATUS_ALL 0x00000001
101#define TX4927_PCIC_PBASTATUS_BM 0x00000001
102
103/* bits for G2PMnGBASE */
104#define TX4927_PCIC_G2PMnGBASE_BSDIS 0x0000002000000000ULL
105#define TX4927_PCIC_G2PMnGBASE_ECHG 0x0000001000000000ULL
106
107/* bits for G2PIOGBASE */
108#define TX4927_PCIC_G2PIOGBASE_BSDIS 0x0000002000000000ULL
109#define TX4927_PCIC_G2PIOGBASE_ECHG 0x0000001000000000ULL
110
111/* bits for PCICSTATUS/PCICMASK */
112#define TX4927_PCIC_PCICSTATUS_ALL 0x000007b8
113#define TX4927_PCIC_PCICSTATUS_PME 0x00000400
114#define TX4927_PCIC_PCICSTATUS_TLB 0x00000200
115#define TX4927_PCIC_PCICSTATUS_NIB 0x00000100
116#define TX4927_PCIC_PCICSTATUS_ZIB 0x00000080
117#define TX4927_PCIC_PCICSTATUS_PERR 0x00000020
118#define TX4927_PCIC_PCICSTATUS_SERR 0x00000010
119#define TX4927_PCIC_PCICSTATUS_GBE 0x00000008
120#define TX4927_PCIC_PCICSTATUS_IWB 0x00000002
121#define TX4927_PCIC_PCICSTATUS_E2PDONE 0x00000001
122
123/* bits for PCICCFG */
124#define TX4927_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
125#define TX4927_PCIC_PCICCFG_HRST 0x00000800
126#define TX4927_PCIC_PCICCFG_SRST 0x00000400
127#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
128#define TX4927_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
129#define TX4927_PCIC_PCICCFG_G2PM0EN 0x00000100
130#define TX4927_PCIC_PCICCFG_G2PM1EN 0x00000080
131#define TX4927_PCIC_PCICCFG_G2PM2EN 0x00000040
132#define TX4927_PCIC_PCICCFG_G2PIOEN 0x00000020
133#define TX4927_PCIC_PCICCFG_TCAR 0x00000010
134#define TX4927_PCIC_PCICCFG_ICAEN 0x00000008
135
136/* bits for P2GMnGBASE */
137#define TX4927_PCIC_P2GMnGBASE_TMEMEN 0x0000004000000000ULL
138#define TX4927_PCIC_P2GMnGBASE_TBSDIS 0x0000002000000000ULL
139#define TX4927_PCIC_P2GMnGBASE_TECHG 0x0000001000000000ULL
140
141/* bits for P2GIOGBASE */
142#define TX4927_PCIC_P2GIOGBASE_TIOEN 0x0000004000000000ULL
143#define TX4927_PCIC_P2GIOGBASE_TBSDIS 0x0000002000000000ULL
144#define TX4927_PCIC_P2GIOGBASE_TECHG 0x0000001000000000ULL
145
146#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
147#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
148
149/* bits for PDMCFG */
150#define TX4927_PCIC_PDMCFG_RSTFIFO 0x00200000
151#define TX4927_PCIC_PDMCFG_EXFER 0x00100000
152#define TX4927_PCIC_PDMCFG_REQDLY_MASK 0x00003800
153#define TX4927_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
154#define TX4927_PCIC_PDMCFG_REQDLY_16 (1 << 11)
155#define TX4927_PCIC_PDMCFG_REQDLY_32 (2 << 11)
156#define TX4927_PCIC_PDMCFG_REQDLY_64 (3 << 11)
157#define TX4927_PCIC_PDMCFG_REQDLY_128 (4 << 11)
158#define TX4927_PCIC_PDMCFG_REQDLY_256 (5 << 11)
159#define TX4927_PCIC_PDMCFG_REQDLY_512 (6 << 11)
160#define TX4927_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
161#define TX4927_PCIC_PDMCFG_ERRIE 0x00000400
162#define TX4927_PCIC_PDMCFG_NCCMPIE 0x00000200
163#define TX4927_PCIC_PDMCFG_NTCMPIE 0x00000100
164#define TX4927_PCIC_PDMCFG_CHNEN 0x00000080
165#define TX4927_PCIC_PDMCFG_XFRACT 0x00000040
166#define TX4927_PCIC_PDMCFG_BSWAP 0x00000020
167#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
168#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
169#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
170#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
171#define TX4927_PCIC_PDMCFG_XFRDIRC 0x00000002
172#define TX4927_PCIC_PDMCFG_CHRST 0x00000001
173
174/* bits for PDMSTS */
175#define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
176#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
177#define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
178#define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000
179#define TX4927_PCIC_PDMSTS_ERRINT 0x00000800
180#define TX4927_PCIC_PDMSTS_DONEINT 0x00000400
181#define TX4927_PCIC_PDMSTS_CHNEN 0x00000200
182#define TX4927_PCIC_PDMSTS_XFRACT 0x00000100
183#define TX4927_PCIC_PDMSTS_ACCMP 0x00000080
184#define TX4927_PCIC_PDMSTS_NCCMP 0x00000040
185#define TX4927_PCIC_PDMSTS_NTCMP 0x00000020
186#define TX4927_PCIC_PDMSTS_CFGERR 0x00000008
187#define TX4927_PCIC_PDMSTS_PCIERR 0x00000004
188#define TX4927_PCIC_PDMSTS_CHNERR 0x00000002
189#define TX4927_PCIC_PDMSTS_DATAERR 0x00000001
190#define TX4927_PCIC_PDMSTS_ALL_CMP 0x000000e0
191#define TX4927_PCIC_PDMSTS_ALL_ERR 0x0000000f
192
193struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
194 struct pci_controller *channel);
195void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
196 struct pci_controller *channel, int extarb);
197void tx4927_report_pcic_status(void);
198
199#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/txx9/tx4938.h
index e8807f5c61e9..12de68a4c10a 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/txx9/tx4938.h
@@ -1,5 +1,4 @@
1/* 1/*
2 * linux/include/asm-mips/tx4938/tx4938.h
3 * Definitions for TX4937/TX4938 2 * Definitions for TX4937/TX4938
4 * Copyright (C) 2000-2001 Toshiba Corporation 3 * Copyright (C) 2000-2001 Toshiba Corporation
5 * 4 *
@@ -10,17 +9,15 @@
10 * 9 *
11 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) 10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
12 */ 11 */
13#ifndef __ASM_TX_BOARDS_TX4938_H 12#ifndef __ASM_TXX9_TX4938_H
14#define __ASM_TX_BOARDS_TX4938_H 13#define __ASM_TXX9_TX4938_H
14
15/* some controllers are compatible with 4927 */
16#include <asm/txx9/tx4927.h>
15 17
16#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) 18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr))
17#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) 19#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b)
18 20
19#define TX4938_NR_IRQ_LOCAL TX4938_IRQ_PIC_BEG
20
21#define TX4938_IRQ_IRC_PCIC (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIC)
22#define TX4938_IRQ_IRC_PCIERR (TX4938_NR_IRQ_LOCAL + TX4938_IR_PCIERR)
23
24#define TX4938_PCIIO_0 0x10000000 21#define TX4938_PCIIO_0 0x10000000
25#define TX4938_PCIIO_1 0x01010000 22#define TX4938_PCIIO_1 0x01010000
26#define TX4938_PCIMEM_0 0x08000000 23#define TX4938_PCIMEM_0 0x08000000
@@ -52,9 +49,6 @@
52#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) 49#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
53#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) 50#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
54 51
55#ifdef __ASSEMBLY__
56#define _CONST64(c) c
57#else
58#define _CONST64(c) c##ull 52#define _CONST64(c) c##ull
59 53
60#include <asm/byteorder.h> 54#include <asm/byteorder.h>
@@ -114,68 +108,6 @@ struct tx4938_dma_reg {
114 endian_def_l2(unused0, mcr); 108 endian_def_l2(unused0, mcr);
115}; 109};
116 110
117struct tx4938_pcic_reg {
118 volatile unsigned long pciid;
119 volatile unsigned long pcistatus;
120 volatile unsigned long pciccrev;
121 volatile unsigned long pcicfg1;
122 volatile unsigned long p2gm0plbase; /* +10 */
123 volatile unsigned long p2gm0pubase;
124 volatile unsigned long p2gm1plbase;
125 volatile unsigned long p2gm1pubase;
126 volatile unsigned long p2gm2pbase; /* +20 */
127 volatile unsigned long p2giopbase;
128 volatile unsigned long unused0;
129 volatile unsigned long pcisid;
130 volatile unsigned long unused1; /* +30 */
131 volatile unsigned long pcicapptr;
132 volatile unsigned long unused2;
133 volatile unsigned long pcicfg2;
134 volatile unsigned long g2ptocnt; /* +40 */
135 volatile unsigned long unused3[15];
136 volatile unsigned long g2pstatus; /* +80 */
137 volatile unsigned long g2pmask;
138 volatile unsigned long pcisstatus;
139 volatile unsigned long pcimask;
140 volatile unsigned long p2gcfg; /* +90 */
141 volatile unsigned long p2gstatus;
142 volatile unsigned long p2gmask;
143 volatile unsigned long p2gccmd;
144 volatile unsigned long unused4[24]; /* +a0 */
145 volatile unsigned long pbareqport; /* +100 */
146 volatile unsigned long pbacfg;
147 volatile unsigned long pbastatus;
148 volatile unsigned long pbamask;
149 volatile unsigned long pbabm; /* +110 */
150 volatile unsigned long pbacreq;
151 volatile unsigned long pbacgnt;
152 volatile unsigned long pbacstate;
153 volatile unsigned long long g2pmgbase[3]; /* +120 */
154 volatile unsigned long long g2piogbase;
155 volatile unsigned long g2pmmask[3]; /* +140 */
156 volatile unsigned long g2piomask;
157 volatile unsigned long long g2pmpbase[3]; /* +150 */
158 volatile unsigned long long g2piopbase;
159 volatile unsigned long pciccfg; /* +170 */
160 volatile unsigned long pcicstatus;
161 volatile unsigned long pcicmask;
162 volatile unsigned long unused5;
163 volatile unsigned long long p2gmgbase[3]; /* +180 */
164 volatile unsigned long long p2giogbase;
165 volatile unsigned long g2pcfgadrs; /* +1a0 */
166 volatile unsigned long g2pcfgdata;
167 volatile unsigned long unused6[8];
168 volatile unsigned long g2pintack;
169 volatile unsigned long g2pspc;
170 volatile unsigned long unused7[12]; /* +1d0 */
171 volatile unsigned long long pdmca; /* +200 */
172 volatile unsigned long long pdmga;
173 volatile unsigned long long pdmpa;
174 volatile unsigned long long pdmctr;
175 volatile unsigned long long pdmcfg; /* +220 */
176 volatile unsigned long long pdmsts;
177};
178
179struct tx4938_aclc_reg { 111struct tx4938_aclc_reg {
180 volatile unsigned long acctlen; 112 volatile unsigned long acctlen;
181 volatile unsigned long acctldis; 113 volatile unsigned long acctldis;
@@ -263,18 +195,18 @@ struct tx4938_sramc_reg {
263}; 195};
264 196
265struct tx4938_ccfg_reg { 197struct tx4938_ccfg_reg {
266 volatile unsigned long long ccfg; 198 u64 ccfg;
267 volatile unsigned long long crir; 199 u64 crir;
268 volatile unsigned long long pcfg; 200 u64 pcfg;
269 volatile unsigned long long tear; 201 u64 toea;
270 volatile unsigned long long clkctr; 202 u64 clkctr;
271 volatile unsigned long long unused0; 203 u64 unused0;
272 volatile unsigned long long garbc; 204 u64 garbc;
273 volatile unsigned long long unused1; 205 u64 unused1;
274 volatile unsigned long long unused2; 206 u64 unused2;
275 volatile unsigned long long ramp; 207 u64 ramp;
276 volatile unsigned long long unused3; 208 u64 unused3;
277 volatile unsigned long long jmpadr; 209 u64 jmpadr;
278}; 210};
279 211
280#undef endian_def_l2 212#undef endian_def_l2
@@ -283,8 +215,6 @@ struct tx4938_ccfg_reg {
283#undef endian_def_b2s 215#undef endian_def_b2s
284#undef endian_def_b4 216#undef endian_def_b4
285 217
286#endif /* __ASSEMBLY__ */
287
288/* 218/*
289 * NDFMC 219 * NDFMC
290 */ 220 */
@@ -336,6 +266,8 @@ struct tx4938_ccfg_reg {
336#define TX4938_IR_ETH0 TX4938_IR_INT(4) 266#define TX4938_IR_ETH0 TX4938_IR_INT(4)
337#define TX4938_IR_ETH1 TX4938_IR_INT(3) 267#define TX4938_IR_ETH1 TX4938_IR_INT(3)
338 268
269#define TX4938_IRC_INT 2 /* IP[2] in Status register */
270
339/* 271/*
340 * CCFG 272 * CCFG
341 */ 273 */
@@ -361,7 +293,7 @@ struct tx4938_ccfg_reg {
361#define TX4938_CCFG_BEOW 0x00010000 293#define TX4938_CCFG_BEOW 0x00010000
362#define TX4938_CCFG_WR 0x00008000 294#define TX4938_CCFG_WR 0x00008000
363#define TX4938_CCFG_TOE 0x00004000 295#define TX4938_CCFG_TOE 0x00004000
364#define TX4938_CCFG_PCIXARB 0x00002000 296#define TX4938_CCFG_PCIARB 0x00002000
365#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00 297#define TX4938_CCFG_PCIDIVMODE_MASK 0x00001c00
366#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10) 298#define TX4938_CCFG_PCIDIVMODE_4 (0x1 << 10)
367#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10) 299#define TX4938_CCFG_PCIDIVMODE_4_5 (0x3 << 10)
@@ -437,110 +369,6 @@ struct tx4938_ccfg_reg {
437#define TX4938_CLKCTR_SIO0RST 0x00000002 369#define TX4938_CLKCTR_SIO0RST 0x00000002
438#define TX4938_CLKCTR_SIO1RST 0x00000001 370#define TX4938_CLKCTR_SIO1RST 0x00000001
439 371
440/* bits for G2PSTATUS/G2PMASK */
441#define TX4938_PCIC_G2PSTATUS_ALL 0x00000003
442#define TX4938_PCIC_G2PSTATUS_TTOE 0x00000002
443#define TX4938_PCIC_G2PSTATUS_RTOE 0x00000001
444
445/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
446#define TX4938_PCIC_PCISTATUS_ALL 0x0000f900
447
448/* bits for PBACFG */
449#define TX4938_PCIC_PBACFG_FIXPA 0x00000008
450#define TX4938_PCIC_PBACFG_RPBA 0x00000004
451#define TX4938_PCIC_PBACFG_PBAEN 0x00000002
452#define TX4938_PCIC_PBACFG_BMCEN 0x00000001
453
454/* bits for G2PMnGBASE */
455#define TX4938_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
456#define TX4938_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
457
458/* bits for G2PIOGBASE */
459#define TX4938_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
460#define TX4938_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
461
462/* bits for PCICSTATUS/PCICMASK */
463#define TX4938_PCIC_PCICSTATUS_ALL 0x000007b8
464#define TX4938_PCIC_PCICSTATUS_PME 0x00000400
465#define TX4938_PCIC_PCICSTATUS_TLB 0x00000200
466#define TX4938_PCIC_PCICSTATUS_NIB 0x00000100
467#define TX4938_PCIC_PCICSTATUS_ZIB 0x00000080
468#define TX4938_PCIC_PCICSTATUS_PERR 0x00000020
469#define TX4938_PCIC_PCICSTATUS_SERR 0x00000010
470#define TX4938_PCIC_PCICSTATUS_GBE 0x00000008
471#define TX4938_PCIC_PCICSTATUS_IWB 0x00000002
472#define TX4938_PCIC_PCICSTATUS_E2PDONE 0x00000001
473
474/* bits for PCICCFG */
475#define TX4938_PCIC_PCICCFG_GBWC_MASK 0x0fff0000
476#define TX4938_PCIC_PCICCFG_HRST 0x00000800
477#define TX4938_PCIC_PCICCFG_SRST 0x00000400
478#define TX4938_PCIC_PCICCFG_IRBER 0x00000200
479#define TX4938_PCIC_PCICCFG_G2PMEN(ch) (0x00000100>>(ch))
480#define TX4938_PCIC_PCICCFG_G2PM0EN 0x00000100
481#define TX4938_PCIC_PCICCFG_G2PM1EN 0x00000080
482#define TX4938_PCIC_PCICCFG_G2PM2EN 0x00000040
483#define TX4938_PCIC_PCICCFG_G2PIOEN 0x00000020
484#define TX4938_PCIC_PCICCFG_TCAR 0x00000010
485#define TX4938_PCIC_PCICCFG_ICAEN 0x00000008
486
487/* bits for P2GMnGBASE */
488#define TX4938_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
489#define TX4938_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
490#define TX4938_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
491
492/* bits for P2GIOGBASE */
493#define TX4938_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
494#define TX4938_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
495#define TX4938_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
496
497#define TX4938_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
498#define TX4938_PCIC_MAX_DEVNU TX4938_PCIC_IDSEL_AD_TO_SLOT(32)
499
500/* bits for PDMCFG */
501#define TX4938_PCIC_PDMCFG_RSTFIFO 0x00200000
502#define TX4938_PCIC_PDMCFG_EXFER 0x00100000
503#define TX4938_PCIC_PDMCFG_REQDLY_MASK 0x00003800
504#define TX4938_PCIC_PDMCFG_REQDLY_NONE (0 << 11)
505#define TX4938_PCIC_PDMCFG_REQDLY_16 (1 << 11)
506#define TX4938_PCIC_PDMCFG_REQDLY_32 (2 << 11)
507#define TX4938_PCIC_PDMCFG_REQDLY_64 (3 << 11)
508#define TX4938_PCIC_PDMCFG_REQDLY_128 (4 << 11)
509#define TX4938_PCIC_PDMCFG_REQDLY_256 (5 << 11)
510#define TX4938_PCIC_PDMCFG_REQDLY_512 (6 << 11)
511#define TX4938_PCIC_PDMCFG_REQDLY_1024 (7 << 11)
512#define TX4938_PCIC_PDMCFG_ERRIE 0x00000400
513#define TX4938_PCIC_PDMCFG_NCCMPIE 0x00000200
514#define TX4938_PCIC_PDMCFG_NTCMPIE 0x00000100
515#define TX4938_PCIC_PDMCFG_CHNEN 0x00000080
516#define TX4938_PCIC_PDMCFG_XFRACT 0x00000040
517#define TX4938_PCIC_PDMCFG_BSWAP 0x00000020
518#define TX4938_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
519#define TX4938_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
520#define TX4938_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
521#define TX4938_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
522#define TX4938_PCIC_PDMCFG_XFRDIRC 0x00000002
523#define TX4938_PCIC_PDMCFG_CHRST 0x00000001
524
525/* bits for PDMSTS */
526#define TX4938_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
527#define TX4938_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
528#define TX4938_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
529#define TX4938_PCIC_PDMSTS_FIFORP_MASK 0x00030000
530#define TX4938_PCIC_PDMSTS_ERRINT 0x00000800
531#define TX4938_PCIC_PDMSTS_DONEINT 0x00000400
532#define TX4938_PCIC_PDMSTS_CHNEN 0x00000200
533#define TX4938_PCIC_PDMSTS_XFRACT 0x00000100
534#define TX4938_PCIC_PDMSTS_ACCMP 0x00000080
535#define TX4938_PCIC_PDMSTS_NCCMP 0x00000040
536#define TX4938_PCIC_PDMSTS_NTCMP 0x00000020
537#define TX4938_PCIC_PDMSTS_CFGERR 0x00000008
538#define TX4938_PCIC_PDMSTS_PCIERR 0x00000004
539#define TX4938_PCIC_PDMSTS_CHNERR 0x00000002
540#define TX4938_PCIC_PDMSTS_DATAERR 0x00000001
541#define TX4938_PCIC_PDMSTS_ALL_CMP 0x000000e0
542#define TX4938_PCIC_PDMSTS_ALL_ERR 0x0000000f
543
544/* 372/*
545 * DMA 373 * DMA
546 */ 374 */
@@ -596,15 +424,15 @@ struct tx4938_ccfg_reg {
596#define TX4938_DMA_CSR_DESERR 0x00000002 424#define TX4938_DMA_CSR_DESERR 0x00000002
597#define TX4938_DMA_CSR_SORERR 0x00000001 425#define TX4938_DMA_CSR_SORERR 0x00000001
598 426
599#ifndef __ASSEMBLY__
600
601#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) 427#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
602#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) 428#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
603#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) 429#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
604#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) 430#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
605#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) 431#define tx4938_pcicptr tx4927_pcicptr
606#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) 432#define tx4938_pcic1ptr \
607#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) 433 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
434#define tx4938_ccfgptr \
435 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
608#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) 436#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
609#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) 437#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
610#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) 438#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG)
@@ -612,17 +440,26 @@ struct tx4938_ccfg_reg {
612#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG) 440#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
613 441
614 442
615#define TX4938_REV_MAJ_MIN() ((unsigned long)tx4938_ccfgptr->crir & 0x00ff) 443#define TX4938_REV_PCODE() \
616#define TX4938_REV_PCODE() ((unsigned long)tx4938_ccfgptr->crir >> 16) 444 ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
445
446#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
447#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
448#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
617 449
618#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) 450#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21)
619#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) 451#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21)
620 452
453#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)])
621#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) 454#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20)
622#define TX4938_EBUSC_SIZE(ch) \ 455#define TX4938_EBUSC_SIZE(ch) \
623 (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf)) 456 (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
624 457
625 458int tx4938_report_pciclk(void);
626#endif /* !__ASSEMBLY__ */ 459void tx4938_report_pci1clk(void);
460int tx4938_pciclk66_setup(void);
461struct pci_dev;
462int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
463void tx4938_irq_init(void);
627 464
628#endif 465#endif
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/txx9/txx927.h
index 25dcf2feb095..97dd7ad1a890 100644
--- a/include/asm-mips/jmr3927/txx927.h
+++ b/include/asm-mips/txx9/txx927.h
@@ -7,8 +7,8 @@
7 * 7 *
8 * Copyright (C) 2000 Toshiba Corporation 8 * Copyright (C) 2000 Toshiba Corporation
9 */ 9 */
10#ifndef __ASM_TXX927_H 10#ifndef __ASM_TXX9_TXX927_H
11#define __ASM_TXX927_H 11#define __ASM_TXX9_TXX927_H
12 12
13struct txx927_sio_reg { 13struct txx927_sio_reg {
14 volatile unsigned long lcr; 14 volatile unsigned long lcr;
@@ -118,4 +118,4 @@ struct txx927_sio_reg {
118 * PIO 118 * PIO
119 */ 119 */
120 120
121#endif /* __ASM_TXX927_H */ 121#endif /* __ASM_TXX9_TXX927_H */
diff --git a/include/asm-mips/vr41xx/cmbvr4133.h b/include/asm-mips/vr41xx/cmbvr4133.h
deleted file mode 100644
index 42300037d593..000000000000
--- a/include/asm-mips/vr41xx/cmbvr4133.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * include/asm-mips/vr41xx/cmbvr4133.h
3 *
4 * Include file for NEC CMB-VR4133.
5 *
6 * Author: Yoichi Yuasa <yyuasa@mvista.com, or source@mvista.com> and
7 * Jun Sun <jsun@mvista.com, or source@mvista.com> and
8 * Alex Sapkov <asapkov@ru.mvista.com>
9 *
10 * 2002-2004 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15#ifndef __NEC_CMBVR4133_H
16#define __NEC_CMBVR4133_H
17
18#include <asm/vr41xx/irq.h>
19
20/*
21 * General-Purpose I/O Pin Number
22 */
23#define CMBVR41XX_INTA_PIN 1
24#define CMBVR41XX_INTB_PIN 1
25#define CMBVR41XX_INTC_PIN 3
26#define CMBVR41XX_INTD_PIN 1
27#define CMBVR41XX_INTE_PIN 1
28
29/*
30 * Interrupt Number
31 */
32#define CMBVR41XX_INTA_IRQ GIU_IRQ(CMBVR41XX_INTA_PIN)
33#define CMBVR41XX_INTB_IRQ GIU_IRQ(CMBVR41XX_INTB_PIN)
34#define CMBVR41XX_INTC_IRQ GIU_IRQ(CMBVR41XX_INTC_PIN)
35#define CMBVR41XX_INTD_IRQ GIU_IRQ(CMBVR41XX_INTD_PIN)
36#define CMBVR41XX_INTE_IRQ GIU_IRQ(CMBVR41XX_INTE_PIN)
37
38#define I8259A_IRQ_BASE 72
39#define I8259_IRQ(x) (I8259A_IRQ_BASE + (x))
40#define TIMER_IRQ I8259_IRQ(0)
41#define KEYBOARD_IRQ I8259_IRQ(1)
42#define I8259_SLAVE_IRQ I8259_IRQ(2)
43#define UART3_IRQ I8259_IRQ(3)
44#define UART1_IRQ I8259_IRQ(4)
45#define UART2_IRQ I8259_IRQ(5)
46#define FDC_IRQ I8259_IRQ(6)
47#define PARPORT_IRQ I8259_IRQ(7)
48#define RTC_IRQ I8259_IRQ(8)
49#define USB_IRQ I8259_IRQ(9)
50#define I8259_INTA_IRQ I8259_IRQ(10)
51#define AUDIO_IRQ I8259_IRQ(11)
52#define AUX_IRQ I8259_IRQ(12)
53#define IDE_PRIMARY_IRQ I8259_IRQ(14)
54#define IDE_SECONDARY_IRQ I8259_IRQ(15)
55
56#endif /* __NEC_CMBVR4133_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 19:04:28 -0500