diff options
author | Marc St-Jean <stjeanma@pmc-sierra.com> | 2007-06-14 17:55:31 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-07-10 12:33:03 -0400 |
commit | 9267a30d1dc7dcd7cadb5eb6a5bbfed703feeefa (patch) | |
tree | 91fa5a1a4605cdf0a1f1db21e22073b87735ce7a /include/asm-mips/war.h | |
parent | 35832e26f95ba14a6b6f0519441c5cb64cca6bf9 (diff) |
[MIPS] PMC MSP71xx mips common
Patch to add mips common support for the PMC-Sierra MSP71xx devices.
Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/war.h')
-rw-r--r-- | include/asm-mips/war.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c507f1b8014e..45cb82724830 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h | |||
@@ -198,6 +198,14 @@ | |||
198 | #endif | 198 | #endif |
199 | 199 | ||
200 | /* | 200 | /* |
201 | * 34K core erratum: "Problems Executing the TLBR Instruction" | ||
202 | */ | ||
203 | #if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ | ||
204 | defined(CONFIG_PMC_MSP7120_FPGA) | ||
205 | #define MIPS34K_MISSED_ITLB_WAR 1 | ||
206 | #endif | ||
207 | |||
208 | /* | ||
201 | * Workarounds default to off | 209 | * Workarounds default to off |
202 | */ | 210 | */ |
203 | #ifndef ICACHE_REFILLS_WORKAROUND_WAR | 211 | #ifndef ICACHE_REFILLS_WORKAROUND_WAR |
@@ -236,5 +244,8 @@ | |||
236 | #ifndef R10000_LLSC_WAR | 244 | #ifndef R10000_LLSC_WAR |
237 | #define R10000_LLSC_WAR 0 | 245 | #define R10000_LLSC_WAR 0 |
238 | #endif | 246 | #endif |
247 | #ifndef MIPS34K_MISSED_ITLB_WAR | ||
248 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
249 | #endif | ||
239 | 250 | ||
240 | #endif /* _ASM_WAR_H */ | 251 | #endif /* _ASM_WAR_H */ |