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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2006-07-13 04:33:03 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-07-13 16:26:19 -0400
commit66151bbd20c6c62dbe5b131484c885086e3a8d29 (patch)
tree7ffdb72ca1f74dda598d1023098ef9bc0f7268c1 /include/asm-mips/vr41xx/vr41xx.h
parent5fd326573876e466c7693cbf06e9c88ecf86135d (diff)
[MIPS] vr41xx: Move IRQ numbers to asm-mips/vr41xx/irq.h
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/vr41xx/vr41xx.h')
-rw-r--r--include/asm-mips/vr41xx/vr41xx.h53
1 files changed, 0 insertions, 53 deletions
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
index 70828d5fae9c..dd3eb3dc5886 100644
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ b/include/asm-mips/vr41xx/vr41xx.h
@@ -74,59 +74,6 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock);
74/* 74/*
75 * Interrupt Control Unit 75 * Interrupt Control Unit
76 */ 76 */
77/* CPU core Interrupt Numbers */
78#define MIPS_CPU_IRQ_BASE 0
79#define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
80#define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0)
81#define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1)
82#define INT0_IRQ MIPS_CPU_IRQ(2)
83#define INT1_IRQ MIPS_CPU_IRQ(3)
84#define INT2_IRQ MIPS_CPU_IRQ(4)
85#define INT3_IRQ MIPS_CPU_IRQ(5)
86#define INT4_IRQ MIPS_CPU_IRQ(6)
87#define TIMER_IRQ MIPS_CPU_IRQ(7)
88
89/* SYINT1 Interrupt Numbers */
90#define SYSINT1_IRQ_BASE 8
91#define SYSINT1_IRQ(x) (SYSINT1_IRQ_BASE + (x))
92#define BATTRY_IRQ SYSINT1_IRQ(0)
93#define POWER_IRQ SYSINT1_IRQ(1)
94#define RTCLONG1_IRQ SYSINT1_IRQ(2)
95#define ELAPSEDTIME_IRQ SYSINT1_IRQ(3)
96/* RFU */
97#define PIU_IRQ SYSINT1_IRQ(5)
98#define AIU_IRQ SYSINT1_IRQ(6)
99#define KIU_IRQ SYSINT1_IRQ(7)
100#define GIUINT_IRQ SYSINT1_IRQ(8)
101#define SIU_IRQ SYSINT1_IRQ(9)
102#define BUSERR_IRQ SYSINT1_IRQ(10)
103#define SOFTINT_IRQ SYSINT1_IRQ(11)
104#define CLKRUN_IRQ SYSINT1_IRQ(12)
105#define DOZEPIU_IRQ SYSINT1_IRQ(13)
106#define SYSINT1_IRQ_LAST DOZEPIU_IRQ
107
108/* SYSINT2 Interrupt Numbers */
109#define SYSINT2_IRQ_BASE 24
110#define SYSINT2_IRQ(x) (SYSINT2_IRQ_BASE + (x))
111#define RTCLONG2_IRQ SYSINT2_IRQ(0)
112#define LED_IRQ SYSINT2_IRQ(1)
113#define HSP_IRQ SYSINT2_IRQ(2)
114#define TCLOCK_IRQ SYSINT2_IRQ(3)
115#define FIR_IRQ SYSINT2_IRQ(4)
116#define CEU_IRQ SYSINT2_IRQ(4) /* same number as FIR_IRQ */
117#define DSIU_IRQ SYSINT2_IRQ(5)
118#define PCI_IRQ SYSINT2_IRQ(6)
119#define SCU_IRQ SYSINT2_IRQ(7)
120#define CSI_IRQ SYSINT2_IRQ(8)
121#define BCU_IRQ SYSINT2_IRQ(9)
122#define ETHERNET_IRQ SYSINT2_IRQ(10)
123#define SYSINT2_IRQ_LAST ETHERNET_IRQ
124
125/* GIU Interrupt Numbers */
126#define GIU_IRQ_BASE 40
127#define GIU_IRQ(x) (GIU_IRQ_BASE + (x)) /* IRQ 40-71 */
128#define GIU_IRQ_LAST GIU_IRQ(31)
129
130extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); 77extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
131extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)); 78extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *));
132 79