aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips/txx9/tx4938.h
diff options
context:
space:
mode:
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-07-18 12:51:41 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-20 09:38:21 -0400
commit255033a9bb900a06c9a7798908ce12557d24fb66 (patch)
tree9bb4b8a54d8737d2126fb6e00c2d1bbe99670a89 /include/asm-mips/txx9/tx4938.h
parentb5d5accc7a2eb41f43ef346f3b258ba2f6342a1c (diff)
[MIPS] TXx9: Cleanups for 64-bit support
* Unify (and fix) mem_tx4938.c and mem_tx4927.c * Simplify prom_init * Kill volatiles and unused definitions for tx4927.h and tx4938.h Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/txx9/tx4938.h')
-rw-r--r--include/asm-mips/txx9/tx4938.h237
1 files changed, 28 insertions, 209 deletions
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
index 12de68a4c10a..6690246a1149 100644
--- a/include/asm-mips/txx9/tx4938.h
+++ b/include/asm-mips/txx9/tx4938.h
@@ -15,20 +15,11 @@
15/* some controllers are compatible with 4927 */ 15/* some controllers are compatible with 4927 */
16#include <asm/txx9/tx4927.h> 16#include <asm/txx9/tx4927.h>
17 17
18#define tx4938_read_nfmc(addr) (*(volatile unsigned int *)(addr)) 18#ifdef CONFIG_64BIT
19#define tx4938_write_nfmc(b, addr) (*(volatile unsigned int *)(addr)) = (b) 19#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
20 20#else
21#define TX4938_PCIIO_0 0x10000000 21#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
22#define TX4938_PCIIO_1 0x01010000 22#endif
23#define TX4938_PCIMEM_0 0x08000000
24#define TX4938_PCIMEM_1 0x11000000
25
26#define TX4938_PCIIO_SIZE_0 0x01000000
27#define TX4938_PCIIO_SIZE_1 0x00010000
28#define TX4938_PCIMEM_SIZE_0 0x08000000
29#define TX4938_PCIMEM_SIZE_1 0x00010000
30
31#define TX4938_REG_BASE 0xff1f0000 /* == TX4937_REG_BASE */
32#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */ 23#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
33 24
34/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */ 25/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
@@ -49,149 +40,8 @@
49#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700) 40#define TX4938_ACLC_REG (TX4938_REG_BASE + 0xf700)
50#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800) 41#define TX4938_SPI_REG (TX4938_REG_BASE + 0xf800)
51 42
52#define _CONST64(c) c##ull
53
54#include <asm/byteorder.h>
55
56#ifdef __BIG_ENDIAN
57#define endian_def_l2(e1, e2) \
58 volatile unsigned long e1, e2
59#define endian_def_s2(e1, e2) \
60 volatile unsigned short e1, e2
61#define endian_def_sb2(e1, e2, e3) \
62 volatile unsigned short e1;volatile unsigned char e2, e3
63#define endian_def_b2s(e1, e2, e3) \
64 volatile unsigned char e1, e2;volatile unsigned short e3
65#define endian_def_b4(e1, e2, e3, e4) \
66 volatile unsigned char e1, e2, e3, e4
67#else
68#define endian_def_l2(e1, e2) \
69 volatile unsigned long e2, e1
70#define endian_def_s2(e1, e2) \
71 volatile unsigned short e2, e1
72#define endian_def_sb2(e1, e2, e3) \
73 volatile unsigned char e3, e2;volatile unsigned short e1
74#define endian_def_b2s(e1, e2, e3) \
75 volatile unsigned short e3;volatile unsigned char e2, e1
76#define endian_def_b4(e1, e2, e3, e4) \
77 volatile unsigned char e4, e3, e2, e1
78#endif
79
80
81struct tx4938_sdramc_reg {
82 volatile unsigned long long cr[4];
83 volatile unsigned long long unused0[4];
84 volatile unsigned long long tr;
85 volatile unsigned long long unused1[2];
86 volatile unsigned long long cmd;
87 volatile unsigned long long sfcmd;
88};
89
90struct tx4938_ebusc_reg {
91 volatile unsigned long long cr[8];
92};
93
94struct tx4938_dma_reg {
95 struct tx4938_dma_ch_reg {
96 volatile unsigned long long cha;
97 volatile unsigned long long sar;
98 volatile unsigned long long dar;
99 endian_def_l2(unused0, cntr);
100 endian_def_l2(unused1, sair);
101 endian_def_l2(unused2, dair);
102 endian_def_l2(unused3, ccr);
103 endian_def_l2(unused4, csr);
104 } ch[4];
105 volatile unsigned long long dbr[8];
106 volatile unsigned long long tdhr;
107 volatile unsigned long long midr;
108 endian_def_l2(unused0, mcr);
109};
110
111struct tx4938_aclc_reg {
112 volatile unsigned long acctlen;
113 volatile unsigned long acctldis;
114 volatile unsigned long acregacc;
115 volatile unsigned long unused0;
116 volatile unsigned long acintsts;
117 volatile unsigned long acintmsts;
118 volatile unsigned long acinten;
119 volatile unsigned long acintdis;
120 volatile unsigned long acsemaph;
121 volatile unsigned long unused1[7];
122 volatile unsigned long acgpidat;
123 volatile unsigned long acgpodat;
124 volatile unsigned long acslten;
125 volatile unsigned long acsltdis;
126 volatile unsigned long acfifosts;
127 volatile unsigned long unused2[11];
128 volatile unsigned long acdmasts;
129 volatile unsigned long acdmasel;
130 volatile unsigned long unused3[6];
131 volatile unsigned long acaudodat;
132 volatile unsigned long acsurrdat;
133 volatile unsigned long accentdat;
134 volatile unsigned long aclfedat;
135 volatile unsigned long acaudiat;
136 volatile unsigned long unused4;
137 volatile unsigned long acmodoat;
138 volatile unsigned long acmodidat;
139 volatile unsigned long unused5[15];
140 volatile unsigned long acrevid;
141};
142
143
144struct tx4938_tmr_reg {
145 volatile unsigned long tcr;
146 volatile unsigned long tisr;
147 volatile unsigned long cpra;
148 volatile unsigned long cprb;
149 volatile unsigned long itmr;
150 volatile unsigned long unused0[3];
151 volatile unsigned long ccdr;
152 volatile unsigned long unused1[3];
153 volatile unsigned long pgmr;
154 volatile unsigned long unused2[3];
155 volatile unsigned long wtmr;
156 volatile unsigned long unused3[43];
157 volatile unsigned long trr;
158};
159
160struct tx4938_sio_reg {
161 volatile unsigned long lcr;
162 volatile unsigned long dicr;
163 volatile unsigned long disr;
164 volatile unsigned long cisr;
165 volatile unsigned long fcr;
166 volatile unsigned long flcr;
167 volatile unsigned long bgr;
168 volatile unsigned long tfifo;
169 volatile unsigned long rfifo;
170};
171
172struct tx4938_ndfmc_reg {
173 endian_def_l2(unused0, dtr);
174 endian_def_l2(unused1, mcr);
175 endian_def_l2(unused2, sr);
176 endian_def_l2(unused3, isr);
177 endian_def_l2(unused4, imr);
178 endian_def_l2(unused5, spr);
179 endian_def_l2(unused6, rstr);
180};
181
182struct tx4938_spi_reg {
183 volatile unsigned long mcr;
184 volatile unsigned long cr0;
185 volatile unsigned long cr1;
186 volatile unsigned long fs;
187 volatile unsigned long unused1;
188 volatile unsigned long sr;
189 volatile unsigned long dr;
190 volatile unsigned long unused2;
191};
192
193struct tx4938_sramc_reg { 43struct tx4938_sramc_reg {
194 volatile unsigned long long cr; 44 u64 cr;
195}; 45};
196 46
197struct tx4938_ccfg_reg { 47struct tx4938_ccfg_reg {
@@ -209,34 +59,6 @@ struct tx4938_ccfg_reg {
209 u64 jmpadr; 59 u64 jmpadr;
210}; 60};
211 61
212#undef endian_def_l2
213#undef endian_def_s2
214#undef endian_def_sb2
215#undef endian_def_b2s
216#undef endian_def_b4
217
218/*
219 * NDFMC
220 */
221
222/* NDFMCR : NDFMC Mode Control */
223#define TX4938_NDFMCR_WE 0x80
224#define TX4938_NDFMCR_ECC_ALL 0x60
225#define TX4938_NDFMCR_ECC_RESET 0x60
226#define TX4938_NDFMCR_ECC_READ 0x40
227#define TX4938_NDFMCR_ECC_ON 0x20
228#define TX4938_NDFMCR_ECC_OFF 0x00
229#define TX4938_NDFMCR_CE 0x10
230#define TX4938_NDFMCR_BSPRT 0x04
231#define TX4938_NDFMCR_ALE 0x02
232#define TX4938_NDFMCR_CLE 0x01
233
234/* NDFMCR : NDFMC Status */
235#define TX4938_NDFSR_BUSY 0x80
236
237/* NDFMCR : NDFMC Reset */
238#define TX4938_NDFRSTR_RST 0x01
239
240/* 62/*
241 * IRC 63 * IRC
242 */ 64 */
@@ -272,9 +94,9 @@ struct tx4938_ccfg_reg {
272 * CCFG 94 * CCFG
273 */ 95 */
274/* CCFG : Chip Configuration */ 96/* CCFG : Chip Configuration */
275#define TX4938_CCFG_WDRST _CONST64(0x0000020000000000) 97#define TX4938_CCFG_WDRST 0x0000020000000000ULL
276#define TX4938_CCFG_WDREXEN _CONST64(0x0000010000000000) 98#define TX4938_CCFG_WDREXEN 0x0000010000000000ULL
277#define TX4938_CCFG_BCFG_MASK _CONST64(0x000000ff00000000) 99#define TX4938_CCFG_BCFG_MASK 0x000000ff00000000ULL
278#define TX4938_CCFG_TINTDIS 0x01000000 100#define TX4938_CCFG_TINTDIS 0x01000000
279#define TX4938_CCFG_PCI66 0x00800000 101#define TX4938_CCFG_PCI66 0x00800000
280#define TX4938_CCFG_PCIMODE 0x00400000 102#define TX4938_CCFG_PCIMODE 0x00400000
@@ -310,12 +132,12 @@ struct tx4938_ccfg_reg {
310#define TX4938_CCFG_ACEHOLD 0x00000001 132#define TX4938_CCFG_ACEHOLD 0x00000001
311 133
312/* PCFG : Pin Configuration */ 134/* PCFG : Pin Configuration */
313#define TX4938_PCFG_ETH0_SEL _CONST64(0x8000000000000000) 135#define TX4938_PCFG_ETH0_SEL 0x8000000000000000ULL
314#define TX4938_PCFG_ETH1_SEL _CONST64(0x4000000000000000) 136#define TX4938_PCFG_ETH1_SEL 0x4000000000000000ULL
315#define TX4938_PCFG_ATA_SEL _CONST64(0x2000000000000000) 137#define TX4938_PCFG_ATA_SEL 0x2000000000000000ULL
316#define TX4938_PCFG_ISA_SEL _CONST64(0x1000000000000000) 138#define TX4938_PCFG_ISA_SEL 0x1000000000000000ULL
317#define TX4938_PCFG_SPI_SEL _CONST64(0x0800000000000000) 139#define TX4938_PCFG_SPI_SEL 0x0800000000000000ULL
318#define TX4938_PCFG_NDF_SEL _CONST64(0x0400000000000000) 140#define TX4938_PCFG_NDF_SEL 0x0400000000000000ULL
319#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000 141#define TX4938_PCFG_SDCLKDLY_MASK 0x30000000
320#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28) 142#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
321#define TX4938_PCFG_SYSCLKEN 0x08000000 143#define TX4938_PCFG_SYSCLKEN 0x08000000
@@ -336,8 +158,8 @@ struct tx4938_ccfg_reg {
336#define TX4938_PCFG_DMASEL3_SIO0 0x00000008 158#define TX4938_PCFG_DMASEL3_SIO0 0x00000008
337 159
338/* CLKCTR : Clock Control */ 160/* CLKCTR : Clock Control */
339#define TX4938_CLKCTR_NDFCKD _CONST64(0x0001000000000000) 161#define TX4938_CLKCTR_NDFCKD 0x0001000000000000ULL
340#define TX4938_CLKCTR_NDFRST _CONST64(0x0000000100000000) 162#define TX4938_CLKCTR_NDFRST 0x0000000100000000ULL
341#define TX4938_CLKCTR_ETH1CKD 0x80000000 163#define TX4938_CLKCTR_ETH1CKD 0x80000000
342#define TX4938_CLKCTR_ETH0CKD 0x40000000 164#define TX4938_CLKCTR_ETH0CKD 0x40000000
343#define TX4938_CLKCTR_SPICKD 0x20000000 165#define TX4938_CLKCTR_SPICKD 0x20000000
@@ -424,20 +246,16 @@ struct tx4938_ccfg_reg {
424#define TX4938_DMA_CSR_DESERR 0x00000002 246#define TX4938_DMA_CSR_DESERR 0x00000002
425#define TX4938_DMA_CSR_SORERR 0x00000001 247#define TX4938_DMA_CSR_SORERR 0x00000001
426 248
427#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) 249#define tx4938_sdramcptr tx4927_sdramcptr
428#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) 250#define tx4938_ebuscptr tx4927_ebuscptr
429#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
430#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
431#define tx4938_pcicptr tx4927_pcicptr 251#define tx4938_pcicptr tx4927_pcicptr
432#define tx4938_pcic1ptr \ 252#define tx4938_pcic1ptr \
433 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG) 253 ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
434#define tx4938_ccfgptr \ 254#define tx4938_ccfgptr \
435 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG) 255 ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
436#define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch))
437#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG) 256#define tx4938_pioptr ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
438#define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) 257#define tx4938_sramcptr \
439#define tx4938_spiptr ((struct tx4938_spi_reg *)TX4938_SPI_REG) 258 ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
440#define tx4938_sramcptr ((struct tx4938_sramc_reg *)TX4938_SRAMC_REG)
441 259
442 260
443#define TX4938_REV_PCODE() \ 261#define TX4938_REV_PCODE() \
@@ -447,14 +265,15 @@ struct tx4938_ccfg_reg {
447#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits) 265#define tx4938_ccfg_set(bits) tx4927_ccfg_set(bits)
448#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new) 266#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
449 267
450#define TX4938_SDRAMC_BA(ch) ((tx4938_sdramcptr->cr[ch] >> 49) << 21) 268#define TX4938_SDRAMC_CR(ch) TX4927_SDRAMC_CR(ch)
451#define TX4938_SDRAMC_SIZE(ch) (((tx4938_sdramcptr->cr[ch] >> 33) + 1) << 21) 269#define TX4938_SDRAMC_BA(ch) TX4927_SDRAMC_BA(ch)
270#define TX4938_SDRAMC_SIZE(ch) TX4927_SDRAMC_SIZE(ch)
452 271
453#define TX4938_EBUSC_CR(ch) __raw_readq(&tx4938_ebuscptr->cr[(ch)]) 272#define TX4938_EBUSC_CR(ch) TX4927_EBUSC_CR(ch)
454#define TX4938_EBUSC_BA(ch) ((tx4938_ebuscptr->cr[ch] >> 48) << 20) 273#define TX4938_EBUSC_BA(ch) TX4927_EBUSC_BA(ch)
455#define TX4938_EBUSC_SIZE(ch) \ 274#define TX4938_EBUSC_SIZE(ch) TX4927_EBUSC_SIZE(ch)
456 (0x00100000 << ((unsigned long)(tx4938_ebuscptr->cr[ch] >> 8) & 0xf))
457 275
276#define tx4938_get_mem_size() tx4927_get_mem_size()
458int tx4938_report_pciclk(void); 277int tx4938_report_pciclk(void);
459void tx4938_report_pci1clk(void); 278void tx4938_report_pci1clk(void);
460int tx4938_pciclk66_setup(void); 279int tx4938_pciclk66_setup(void);