diff options
author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2007-06-22 10:22:06 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-07-10 12:33:03 -0400 |
commit | f74cf6ff99a49741b0f243996b621777b2d610d4 (patch) | |
tree | 5812f82646aadcbd451e528379548866c5ca790d /include/asm-mips/tx4938 | |
parent | 3896b05418b9b8548a678231db754206b3ebe56e (diff) |
[MIPS] rbtx4938: Convert SPI codes to use generic SPI drivers
Use rtc-rs5c348 and at25 spi protocol driver and spi_txx9 spi
controller driver instead of platform dependent codes.
This patch also removes dependencies to old RTC interfaces such as
rtc_mips_get_time, etc.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/tx4938')
-rw-r--r-- | include/asm-mips/tx4938/rbtx4938.h | 6 | ||||
-rw-r--r-- | include/asm-mips/tx4938/spi.h | 56 |
2 files changed, 1 insertions, 61 deletions
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h index 0fbedafdcea8..74e7d8061e58 100644 --- a/include/asm-mips/tx4938/rbtx4938.h +++ b/include/asm-mips/tx4938/rbtx4938.h | |||
@@ -105,12 +105,6 @@ | |||
105 | #define rbtx4938_pcireset_ptr \ | 105 | #define rbtx4938_pcireset_ptr \ |
106 | ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR) | 106 | ((volatile unsigned char *)RBTX4938_PCIRESET_ADDR) |
107 | 107 | ||
108 | /* SPI */ | ||
109 | #define RBTX4938_SEEPROM1_CHIPID 0 | ||
110 | #define RBTX4938_SEEPROM2_CHIPID 1 | ||
111 | #define RBTX4938_SEEPROM3_CHIPID 2 | ||
112 | #define RBTX4938_SRTC_CHIPID 3 | ||
113 | |||
114 | /* | 108 | /* |
115 | * IRQ mappings | 109 | * IRQ mappings |
116 | */ | 110 | */ |
diff --git a/include/asm-mips/tx4938/spi.h b/include/asm-mips/tx4938/spi.h index 0dbbab820a5a..6a60c83e152b 100644 --- a/include/asm-mips/tx4938/spi.h +++ b/include/asm-mips/tx4938/spi.h | |||
@@ -14,61 +14,7 @@ | |||
14 | #ifndef __ASM_TX_BOARDS_TX4938_SPI_H | 14 | #ifndef __ASM_TX_BOARDS_TX4938_SPI_H |
15 | #define __ASM_TX_BOARDS_TX4938_SPI_H | 15 | #define __ASM_TX_BOARDS_TX4938_SPI_H |
16 | 16 | ||
17 | /* SPI */ | 17 | extern int spi_eeprom_register(int chipid); |
18 | struct spi_dev_desc { | ||
19 | unsigned int baud; | ||
20 | unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */ | ||
21 | unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */ | ||
22 | unsigned int polarity:1; /* 0:High-Active */ | ||
23 | unsigned int phase:1; /* 0:Sample-Then-Shift */ | ||
24 | }; | ||
25 | |||
26 | extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init; | ||
27 | extern void txx9_spi_irqinit(int irc_irq) __init; | ||
28 | extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc, | ||
29 | unsigned char **inbufs, unsigned int *incounts, | ||
30 | unsigned char **outbufs, unsigned int *outcounts, | ||
31 | int cansleep); | ||
32 | extern int spi_eeprom_write_enable(int chipid, int enable); | ||
33 | extern int spi_eeprom_read_status(int chipid); | ||
34 | extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); | 18 | extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len); |
35 | extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len); | ||
36 | extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init; | ||
37 | |||
38 | #define TXX9_IMCLK (txx9_gbus_clock / 2) | ||
39 | |||
40 | /* | ||
41 | * SPI | ||
42 | */ | ||
43 | |||
44 | /* SPMCR : SPI Master Control */ | ||
45 | #define TXx9_SPMCR_OPMODE 0xc0 | ||
46 | #define TXx9_SPMCR_CONFIG 0x40 | ||
47 | #define TXx9_SPMCR_ACTIVE 0x80 | ||
48 | #define TXx9_SPMCR_SPSTP 0x02 | ||
49 | #define TXx9_SPMCR_BCLR 0x01 | ||
50 | |||
51 | /* SPCR0 : SPI Status */ | ||
52 | #define TXx9_SPCR0_TXIFL_MASK 0xc000 | ||
53 | #define TXx9_SPCR0_RXIFL_MASK 0x3000 | ||
54 | #define TXx9_SPCR0_SIDIE 0x0800 | ||
55 | #define TXx9_SPCR0_SOEIE 0x0400 | ||
56 | #define TXx9_SPCR0_RBSIE 0x0200 | ||
57 | #define TXx9_SPCR0_TBSIE 0x0100 | ||
58 | #define TXx9_SPCR0_IFSPSE 0x0010 | ||
59 | #define TXx9_SPCR0_SBOS 0x0004 | ||
60 | #define TXx9_SPCR0_SPHA 0x0002 | ||
61 | #define TXx9_SPCR0_SPOL 0x0001 | ||
62 | |||
63 | /* SPSR : SPI Status */ | ||
64 | #define TXx9_SPSR_TBSI 0x8000 | ||
65 | #define TXx9_SPSR_RBSI 0x4000 | ||
66 | #define TXx9_SPSR_TBS_MASK 0x3800 | ||
67 | #define TXx9_SPSR_RBS_MASK 0x0700 | ||
68 | #define TXx9_SPSR_SPOE 0x0080 | ||
69 | #define TXx9_SPSR_IFSD 0x0008 | ||
70 | #define TXx9_SPSR_SIDLE 0x0004 | ||
71 | #define TXx9_SPSR_STRDY 0x0002 | ||
72 | #define TXx9_SPSR_SRRDY 0x0001 | ||
73 | 19 | ||
74 | #endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ | 20 | #endif /* __ASM_TX_BOARDS_TX4938_SPI_H */ |