diff options
author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2007-08-02 10:36:02 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-08-26 21:16:53 -0400 |
commit | c87abd75b35e8f991ff8ff1510d6fb62612c61fa (patch) | |
tree | de68c4446c35337c47c17253d769bfeee92f80b3 /include/asm-mips/tx4938/rbtx4938.h | |
parent | 8420fd00e88ef4f6082866aa151bc753b006b3b6 (diff) |
[MIPS] Cleanup TX39/TX49 irq code
Cleanup jmr3927, tx4927 and tx4938 irq codes, using common IRQ_CPU,
I8259 and IRQ_TXX9 irq routines.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/tx4938/rbtx4938.h')
-rw-r--r-- | include/asm-mips/tx4938/rbtx4938.h | 25 |
1 files changed, 5 insertions, 20 deletions
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h index 74e7d8061e58..b14acb575be2 100644 --- a/include/asm-mips/tx4938/rbtx4938.h +++ b/include/asm-mips/tx4938/rbtx4938.h | |||
@@ -14,6 +14,7 @@ | |||
14 | 14 | ||
15 | #include <asm/addrspace.h> | 15 | #include <asm/addrspace.h> |
16 | #include <asm/tx4938/tx4938.h> | 16 | #include <asm/tx4938/tx4938.h> |
17 | #include <asm/txx9irq.h> | ||
17 | 18 | ||
18 | /* CS */ | 19 | /* CS */ |
19 | #define RBTX4938_CE0 0x1c000000 /* 64M */ | 20 | #define RBTX4938_CE0 0x1c000000 /* 64M */ |
@@ -123,21 +124,11 @@ | |||
123 | #define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ | 124 | #define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ |
124 | #define RBTX4938_NR_IRQ_IOC 8 | 125 | #define RBTX4938_NR_IRQ_IOC 8 |
125 | 126 | ||
126 | #define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ | 127 | #define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE |
127 | #define MI8259_IRQ_ISA_RAW_END 15 | 128 | #define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1) |
128 | #define TX4938_IRQ_CP0_RAW_BEG 0 /* tx4938 cpu built-in cp0 */ | ||
129 | #define TX4938_IRQ_CP0_RAW_END 7 | ||
130 | #define TX4938_IRQ_PIC_RAW_BEG 0 /* tx4938 cpu build-in pic */ | ||
131 | #define TX4938_IRQ_PIC_RAW_END 31 | ||
132 | 129 | ||
133 | #define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ | 130 | #define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE |
134 | #define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ | 131 | #define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1) |
135 | |||
136 | #define TX4938_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG) /* 16 */ | ||
137 | #define TX4938_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END) /* 23 */ | ||
138 | |||
139 | #define TX4938_IRQ_PIC_BEG ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG) /* 24 */ | ||
140 | #define TX4938_IRQ_PIC_END ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END) /* 55 */ | ||
141 | #define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) | 132 | #define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) |
142 | #define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) | 133 | #define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) |
143 | #define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) | 134 | #define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) |
@@ -192,10 +183,4 @@ | |||
192 | #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) | 183 | #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) |
193 | #define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) | 184 | #define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) |
194 | 185 | ||
195 | /* IRCR : Int. Control */ | ||
196 | #define TX4938_IRCR_LOW 0x00000000 | ||
197 | #define TX4938_IRCR_HIGH 0x00000001 | ||
198 | #define TX4938_IRCR_DOWN 0x00000002 | ||
199 | #define TX4938_IRCR_UP 0x00000003 | ||
200 | |||
201 | #endif /* __ASM_TX_BOARDS_RBTX4938_H */ | 186 | #endif /* __ASM_TX_BOARDS_RBTX4938_H */ |