[MIPS] Cleanup TX39/TX49 irq code

Cleanup jmr3927, tx4927 and tx4938 irq codes, using common IRQ_CPU,
I8259 and IRQ_TXX9 irq routines.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 7 insertions, 67 deletions

diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
index 5dc40a867774..a60649569c2c 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h
@@ -50,7 +50,7 @@
 
 
 #define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
-#define RBTX4927_RTL_8019_IRQ  (29)
+#define RBTX4927_RTL_8019_IRQ  (TX4927_IRQ_PIC_BEG + 5)
 
 int toshiba_rbtx4927_irq_nested(int sw_irq);
 
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index de85bd2245f7..4bd4368e188c 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -28,6 +28,7 @@
 #define __ASM_TX4927_TX4927_H
 
 #include <asm/tx4927/tx4927_mips.h>
+#include <asm/txx9irq.h>
 
 /*
  This register naming came from the integrated CPU/controller name TX4927
@@ -421,32 +422,6 @@
 #define TX4927_PIO_LIMIT                0xf50f
 
 
-/* TX4927 Interrupt Controller (32-bit registers) */
-#define TX4927_IRC_BASE                 0xf510
-#define TX4927_IRC_IRFLAG0              0xf510
-#define TX4927_IRC_IRFLAG1              0xf514
-#define TX4927_IRC_IRPOL                0xf518
-#define TX4927_IRC_IRRCNT               0xf51c
-#define TX4927_IRC_IRMASKINT            0xf520
-#define TX4927_IRC_IRMASKEXT            0xf524
-#define TX4927_IRC_IRDEN                0xf600
-#define TX4927_IRC_IRDM0                0xf604
-#define TX4927_IRC_IRDM1                0xf608
-#define TX4927_IRC_IRLVL0               0xf610
-#define TX4927_IRC_IRLVL1               0xf614
-#define TX4927_IRC_IRLVL2               0xf618
-#define TX4927_IRC_IRLVL3               0xf61c
-#define TX4927_IRC_IRLVL4               0xf620
-#define TX4927_IRC_IRLVL5               0xf624
-#define TX4927_IRC_IRLVL6               0xf628
-#define TX4927_IRC_IRLVL7               0xf62c
-#define TX4927_IRC_IRMSK                0xf640
-#define TX4927_IRC_IREDC                0xf660
-#define TX4927_IRC_IRPND                0xf680
-#define TX4927_IRC_IRCS                 0xf6a0
-#define TX4927_IRC_LIMIT                0xf6ff
-
-
 /* TX4927 AC-link controller (32-bit registers) */
 #define TX4927_ACLC_BASE                0xf700
 #define TX4927_ACLC_ACCTLEN             0xf700
@@ -493,25 +468,11 @@
 #define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
 
 
+#define TX4927_IRQ_CP0_BEG  MIPS_CPU_IRQ_BASE
+#define TX4927_IRQ_CP0_END  (MIPS_CPU_IRQ_BASE + 8 - 1)
 
-
-
-#define MI8259_IRQ_ISA_RAW_BEG   0    /* optional backplane i8259 */
-#define MI8259_IRQ_ISA_RAW_END  15
-#define TX4927_IRQ_CP0_RAW_BEG   0    /* tx4927 cpu built-in cp0 */
-#define TX4927_IRQ_CP0_RAW_END   7
-#define TX4927_IRQ_PIC_RAW_BEG   0    /* tx4927 cpu build-in pic */
-#define TX4927_IRQ_PIC_RAW_END  31
-
-
-#define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG   /*  0 */
-#define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END   /* 15 */
-
-#define TX4927_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG)  /* 16 */
-#define TX4927_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END)  /* 23 */
-
-#define TX4927_IRQ_PIC_BEG  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG)  /* 24 */
-#define TX4927_IRQ_PIC_END  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END)  /* 55 */
+#define TX4927_IRQ_PIC_BEG  TXX9_IRQ_BASE
+#define TX4927_IRQ_PIC_END  (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
 
 
 #define TX4927_IRQ_USER0            (TX4927_IRQ_CP0_BEG+0)
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index 66c064690f41..f98b2bb719d5 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -48,7 +48,7 @@
 #define TX4927_PCI_CLK_ACK      0x04
 #define TX4927_PCI_CLK_ACE      0x02
 #define TX4927_PCI_CLK_ENDIAN   0x01
-#define TX4927_NR_IRQ_LOCAL     (8+16)
+#define TX4927_NR_IRQ_LOCAL     TX4927_IRQ_PIC_BEG
 #define TX4927_NR_IRQ_IRC       32      /* On-Chip IRC */
 
 #define TX4927_IR_PCIC          16
@@ -99,21 +99,6 @@ struct tx4927_ccfg_reg {
         volatile unsigned long long ramp;
 };
 
-struct tx4927_irc_reg {
-        volatile unsigned long cer;
-        volatile unsigned long cr[2];
-        volatile unsigned long unused0;
-        volatile unsigned long ilr[8];
-        volatile unsigned long unused1[4];
-        volatile unsigned long imr;
-        volatile unsigned long unused2[7];
-        volatile unsigned long scr;
-        volatile unsigned long unused3[7];
-        volatile unsigned long ssr;
-        volatile unsigned long unused4[7];
-        volatile unsigned long csr;
-};
-
 struct tx4927_pcic_reg {
         volatile unsigned long pciid;
         volatile unsigned long pcistatus;
@@ -182,11 +167,6 @@ struct tx4927_pcic_reg {
 
 #endif /* _LANGUAGE_ASSEMBLY */
 
-/* IRCSR : Int. Current Status */
-#define TX4927_IRCSR_IF         0x00010000
-#define TX4927_IRCSR_ILV_MASK   0x00000700
-#define TX4927_IRCSR_IVL_MASK   0x0000001f
-
 /*
  * PCIC
  */
@@ -278,7 +258,6 @@ struct tx4927_pcic_reg {
 #define tx4927_pcicptr          ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
 #define tx4927_ccfgptr          ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
 #define tx4927_ebuscptr         ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
-#define tx4927_ircptr           ((struct tx4927_irc_reg *)TX4927_IRC_REG)
 
 #endif /* _LANGUAGE_ASSEMBLY */