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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-07-10 11:31:36 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-15 13:44:35 -0400
commit22b1d707ffc99faebd86257ad19d5bb9fc624734 (patch)
tree9bd0bcd3878611d74db29e17f3c6e951f4656e61 /include/asm-mips/tx4927
parent14476007c90005c8992b786c15a59cca31f53268 (diff)
[MIPS] TXx9: Reorganize code
Move arch/mips/{jmr3927,tx4927,tx4938} into arch/mips/txx9/ tree. This will help more code sharing and maintainance. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/tx4927')
-rw-r--r--include/asm-mips/tx4927/smsc_fdc37m81x.h69
-rw-r--r--include/asm-mips/tx4927/toshiba_rbtx4927.h49
-rw-r--r--include/asm-mips/tx4927/tx4927.h280
3 files changed, 0 insertions, 398 deletions
diff --git a/include/asm-mips/tx4927/smsc_fdc37m81x.h b/include/asm-mips/tx4927/smsc_fdc37m81x.h
deleted file mode 100644
index 5d93bab51254..000000000000
--- a/include/asm-mips/tx4927/smsc_fdc37m81x.h
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * linux/include/asm-mips/tx4927/smsc_fdc37m81x.h
3 *
4 * Interface for smsc fdc48m81x Super IO chip
5 *
6 * Author: MontaVista Software, Inc. source@mvista.com
7 *
8 * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 *
13 * Copyright (C) 2004 MontaVista Software Inc.
14 * Manish Lachwani, mlachwani@mvista.com
15 */
16
17#ifndef _SMSC_FDC37M81X_H_
18#define _SMSC_FDC37M81X_H_
19
20/* Common Registers */
21#define SMSC_FDC37M81X_CONFIG_INDEX 0x00
22#define SMSC_FDC37M81X_CONFIG_DATA 0x01
23#define SMSC_FDC37M81X_CONF 0x02
24#define SMSC_FDC37M81X_INDEX 0x03
25#define SMSC_FDC37M81X_DNUM 0x07
26#define SMSC_FDC37M81X_DID 0x20
27#define SMSC_FDC37M81X_DREV 0x21
28#define SMSC_FDC37M81X_PCNT 0x22
29#define SMSC_FDC37M81X_PMGT 0x23
30#define SMSC_FDC37M81X_OSC 0x24
31#define SMSC_FDC37M81X_CONFPA0 0x26
32#define SMSC_FDC37M81X_CONFPA1 0x27
33#define SMSC_FDC37M81X_TEST4 0x2B
34#define SMSC_FDC37M81X_TEST5 0x2C
35#define SMSC_FDC37M81X_TEST1 0x2D
36#define SMSC_FDC37M81X_TEST2 0x2E
37#define SMSC_FDC37M81X_TEST3 0x2F
38
39/* Logical device numbers */
40#define SMSC_FDC37M81X_FDD 0x00
41#define SMSC_FDC37M81X_PARALLEL 0x03
42#define SMSC_FDC37M81X_SERIAL1 0x04
43#define SMSC_FDC37M81X_SERIAL2 0x05
44#define SMSC_FDC37M81X_KBD 0x07
45#define SMSC_FDC37M81X_AUXIO 0x08
46#define SMSC_FDC37M81X_NONE 0xff
47
48/* Logical device Config Registers */
49#define SMSC_FDC37M81X_ACTIVE 0x30
50#define SMSC_FDC37M81X_BASEADDR0 0x60
51#define SMSC_FDC37M81X_BASEADDR1 0x61
52#define SMSC_FDC37M81X_INT 0x70
53#define SMSC_FDC37M81X_INT2 0x72
54#define SMSC_FDC37M81X_LDCR_F0 0xF0
55
56/* Chip Config Values */
57#define SMSC_FDC37M81X_CONFIG_ENTER 0x55
58#define SMSC_FDC37M81X_CONFIG_EXIT 0xaa
59#define SMSC_FDC37M81X_CHIP_ID 0x4d
60
61unsigned long __init smsc_fdc37m81x_init(unsigned long port);
62
63void smsc_fdc37m81x_config_beg(void);
64
65void smsc_fdc37m81x_config_end(void);
66
67void smsc_fdc37m81x_config_set(u8 reg, u8 val);
68
69#endif
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
deleted file mode 100644
index d6b32acd6b7b..000000000000
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2002 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_TX4927_TOSHIBA_RBTX4927_H
28#define __ASM_TX4927_TOSHIBA_RBTX4927_H
29
30#include <asm/tx4927/tx4927.h>
31
32#ifdef CONFIG_PCI
33#define TBTX4927_ISA_IO_OFFSET TX4927_PCIIO
34#else
35#define TBTX4927_ISA_IO_OFFSET 0
36#endif
37
38#define RBTX4927_SW_RESET_DO (void __iomem *)0xbc00f000UL
39#define RBTX4927_SW_RESET_DO_SET 0x01
40
41#define RBTX4927_SW_RESET_ENABLE (void __iomem *)0xbc00f002UL
42#define RBTX4927_SW_RESET_ENABLE_SET 0x01
43
44#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
45#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5)
46
47int toshiba_rbtx4927_irq_nested(int sw_irq);
48
49#endif /* __ASM_TX4927_TOSHIBA_RBTX4927_H */
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
deleted file mode 100644
index 1d4816f3266f..000000000000
--- a/include/asm-mips/tx4927/tx4927.h
+++ /dev/null
@@ -1,280 +0,0 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * source@mvista.com
4 *
5 * Copyright 2001-2006 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
15 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
17 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
18 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
19 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
20 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
21 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27#ifndef __ASM_TX4927_TX4927_H
28#define __ASM_TX4927_TX4927_H
29
30#include <asm/txx9irq.h>
31
32#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
33#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
34
35#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE
36#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
37
38
39#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
40#define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1)
41#define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2)
42#define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7)
43
44#define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3)
45
46#define TX4927_CCFG_TOE 0x00004000
47#define TX4927_CCFG_WR 0x00008000
48#define TX4927_CCFG_TINTDIS 0x01000000
49
50#define TX4927_PCIMEM 0x08000000
51#define TX4927_PCIMEM_SIZE 0x08000000
52#define TX4927_PCIIO 0x16000000
53#define TX4927_PCIIO_SIZE 0x01000000
54
55#define TX4927_SDRAMC_REG 0xff1f8000
56#define TX4927_EBUSC_REG 0xff1f9000
57#define TX4927_PCIC_REG 0xff1fd000
58#define TX4927_CCFG_REG 0xff1fe000
59#define TX4927_IRC_REG 0xff1ff600
60#define TX4927_NR_TMR 3
61#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100)
62
63/* bits for ISTAT3/IMASK3/IMSTAT3 */
64#define TX4927_INT3B_PCID 0
65#define TX4927_INT3B_PCIC 1
66#define TX4927_INT3B_PCIB 2
67#define TX4927_INT3B_PCIA 3
68#define TX4927_INT3F_PCID (1 << TX4927_INT3B_PCID)
69#define TX4927_INT3F_PCIC (1 << TX4927_INT3B_PCIC)
70#define TX4927_INT3F_PCIB (1 << TX4927_INT3B_PCIB)
71#define TX4927_INT3F_PCIA (1 << TX4927_INT3B_PCIA)
72
73#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
74#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
75
76#define TX4927_IR_PCIC 16
77#define TX4927_IR_PCIERR 22
78#define TX4927_IR_PCIPMA 23
79#define TX4927_IRQ_IRC_PCIC (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIC)
80#define TX4927_IRQ_IRC_PCIERR (TX4927_NR_IRQ_LOCAL + TX4927_IR_PCIERR)
81#define TX4927_IRQ_IOC1 (TX4927_NR_IRQ_LOCAL + TX4927_NR_IRQ_IRC)
82#define TX4927_IRQ_IOC_PCID (TX4927_IRQ_IOC1 + TX4927_INT3B_PCID)
83#define TX4927_IRQ_IOC_PCIC (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIC)
84#define TX4927_IRQ_IOC_PCIB (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIB)
85#define TX4927_IRQ_IOC_PCIA (TX4927_IRQ_IOC1 + TX4927_INT3B_PCIA)
86
87#ifdef _LANGUAGE_ASSEMBLY
88#define _CONST64(c) c
89#else
90#define _CONST64(c) c##ull
91
92#include <asm/byteorder.h>
93
94struct tx4927_sdramc_reg {
95 volatile unsigned long long cr[4];
96 volatile unsigned long long unused0[4];
97 volatile unsigned long long tr;
98 volatile unsigned long long unused1[2];
99 volatile unsigned long long cmd;
100};
101
102struct tx4927_ebusc_reg {
103 volatile unsigned long long cr[8];
104};
105
106struct tx4927_ccfg_reg {
107 volatile unsigned long long ccfg;
108 volatile unsigned long long crir;
109 volatile unsigned long long pcfg;
110 volatile unsigned long long tear;
111 volatile unsigned long long clkctr;
112 volatile unsigned long long unused0;
113 volatile unsigned long long garbc;
114 volatile unsigned long long unused1;
115 volatile unsigned long long unused2;
116 volatile unsigned long long ramp;
117};
118
119struct tx4927_pcic_reg {
120 volatile unsigned long pciid;
121 volatile unsigned long pcistatus;
122 volatile unsigned long pciccrev;
123 volatile unsigned long pcicfg1;
124 volatile unsigned long p2gm0plbase; /* +10 */
125 volatile unsigned long p2gm0pubase;
126 volatile unsigned long p2gm1plbase;
127 volatile unsigned long p2gm1pubase;
128 volatile unsigned long p2gm2pbase; /* +20 */
129 volatile unsigned long p2giopbase;
130 volatile unsigned long unused0;
131 volatile unsigned long pcisid;
132 volatile unsigned long unused1; /* +30 */
133 volatile unsigned long pcicapptr;
134 volatile unsigned long unused2;
135 volatile unsigned long pcicfg2;
136 volatile unsigned long g2ptocnt; /* +40 */
137 volatile unsigned long unused3[15];
138 volatile unsigned long g2pstatus; /* +80 */
139 volatile unsigned long g2pmask;
140 volatile unsigned long pcisstatus;
141 volatile unsigned long pcimask;
142 volatile unsigned long p2gcfg; /* +90 */
143 volatile unsigned long p2gstatus;
144 volatile unsigned long p2gmask;
145 volatile unsigned long p2gccmd;
146 volatile unsigned long unused4[24]; /* +a0 */
147 volatile unsigned long pbareqport; /* +100 */
148 volatile unsigned long pbacfg;
149 volatile unsigned long pbastatus;
150 volatile unsigned long pbamask;
151 volatile unsigned long pbabm; /* +110 */
152 volatile unsigned long pbacreq;
153 volatile unsigned long pbacgnt;
154 volatile unsigned long pbacstate;
155 volatile unsigned long long g2pmgbase[3]; /* +120 */
156 volatile unsigned long long g2piogbase;
157 volatile unsigned long g2pmmask[3]; /* +140 */
158 volatile unsigned long g2piomask;
159 volatile unsigned long long g2pmpbase[3]; /* +150 */
160 volatile unsigned long long g2piopbase;
161 volatile unsigned long pciccfg; /* +170 */
162 volatile unsigned long pcicstatus;
163 volatile unsigned long pcicmask;
164 volatile unsigned long unused5;
165 volatile unsigned long long p2gmgbase[3]; /* +180 */
166 volatile unsigned long long p2giogbase;
167 volatile unsigned long g2pcfgadrs; /* +1a0 */
168 volatile unsigned long g2pcfgdata;
169 volatile unsigned long unused6[8];
170 volatile unsigned long g2pintack;
171 volatile unsigned long g2pspc;
172 volatile unsigned long unused7[12]; /* +1d0 */
173 volatile unsigned long long pdmca; /* +200 */
174 volatile unsigned long long pdmga;
175 volatile unsigned long long pdmpa;
176 volatile unsigned long long pdmcut;
177 volatile unsigned long long pdmcnt; /* +220 */
178 volatile unsigned long long pdmsts;
179 volatile unsigned long long unused8[2];
180 volatile unsigned long long pdmdb[4]; /* +240 */
181 volatile unsigned long long pdmtdh; /* +260 */
182 volatile unsigned long long pdmdms;
183};
184
185#endif /* _LANGUAGE_ASSEMBLY */
186
187/*
188 * PCIC
189 */
190
191/* bits for G2PSTATUS/G2PMASK */
192#define TX4927_PCIC_G2PSTATUS_ALL 0x00000003
193#define TX4927_PCIC_G2PSTATUS_TTOE 0x00000002
194#define TX4927_PCIC_G2PSTATUS_RTOE 0x00000001
195
196/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci.h */
197#define TX4927_PCIC_PCISTATUS_ALL 0x0000f900
198
199/* bits for PBACFG */
200#define TX4927_PCIC_PBACFG_RPBA 0x00000004
201#define TX4927_PCIC_PBACFG_PBAEN 0x00000002
202#define TX4927_PCIC_PBACFG_BMCEN 0x00000001
203
204/* bits for G2PMnGBASE */
205#define TX4927_PCIC_G2PMnGBASE_BSDIS _CONST64(0x0000002000000000)
206#define TX4927_PCIC_G2PMnGBASE_ECHG _CONST64(0x0000001000000000)
207
208/* bits for G2PIOGBASE */
209#define TX4927_PCIC_G2PIOGBASE_BSDIS _CONST64(0x0000002000000000)
210#define TX4927_PCIC_G2PIOGBASE_ECHG _CONST64(0x0000001000000000)
211
212/* bits for PCICSTATUS/PCICMASK */
213#define TX4927_PCIC_PCICSTATUS_ALL 0x000007dc
214
215/* bits for PCICCFG */
216#define TX4927_PCIC_PCICCFG_LBWC_MASK 0x0fff0000
217#define TX4927_PCIC_PCICCFG_HRST 0x00000800
218#define TX4927_PCIC_PCICCFG_SRST 0x00000400
219#define TX4927_PCIC_PCICCFG_IRBER 0x00000200
220#define TX4927_PCIC_PCICCFG_IMSE0 0x00000100
221#define TX4927_PCIC_PCICCFG_IMSE1 0x00000080
222#define TX4927_PCIC_PCICCFG_IMSE2 0x00000040
223#define TX4927_PCIC_PCICCFG_IISE 0x00000020
224#define TX4927_PCIC_PCICCFG_ATR 0x00000010
225#define TX4927_PCIC_PCICCFG_ICAE 0x00000008
226
227/* bits for P2GMnGBASE */
228#define TX4927_PCIC_P2GMnGBASE_TMEMEN _CONST64(0x0000004000000000)
229#define TX4927_PCIC_P2GMnGBASE_TBSDIS _CONST64(0x0000002000000000)
230#define TX4927_PCIC_P2GMnGBASE_TECHG _CONST64(0x0000001000000000)
231
232/* bits for P2GIOGBASE */
233#define TX4927_PCIC_P2GIOGBASE_TIOEN _CONST64(0x0000004000000000)
234#define TX4927_PCIC_P2GIOGBASE_TBSDIS _CONST64(0x0000002000000000)
235#define TX4927_PCIC_P2GIOGBASE_TECHG _CONST64(0x0000001000000000)
236
237#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
238#define TX4927_PCIC_MAX_DEVNU TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
239
240/*
241 * CCFG
242 */
243/* CCFG : Chip Configuration */
244#define TX4927_CCFG_PCI66 0x00800000
245#define TX4927_CCFG_PCIMIDE 0x00400000
246#define TX4927_CCFG_PCIXARB 0x00002000
247#define TX4927_CCFG_PCIDIVMODE_MASK 0x00001800
248#define TX4927_CCFG_PCIDIVMODE_2_5 0x00000000
249#define TX4927_CCFG_PCIDIVMODE_3 0x00000800
250#define TX4927_CCFG_PCIDIVMODE_5 0x00001000
251#define TX4927_CCFG_PCIDIVMODE_6 0x00001800
252
253#define TX4937_CCFG_PCIDIVMODE_MASK 0x00001c00
254#define TX4937_CCFG_PCIDIVMODE_8 0x00000000
255#define TX4937_CCFG_PCIDIVMODE_4 0x00000400
256#define TX4937_CCFG_PCIDIVMODE_9 0x00000800
257#define TX4937_CCFG_PCIDIVMODE_4_5 0x00000c00
258#define TX4937_CCFG_PCIDIVMODE_10 0x00001000
259#define TX4937_CCFG_PCIDIVMODE_5 0x00001400
260#define TX4937_CCFG_PCIDIVMODE_11 0x00001800
261#define TX4937_CCFG_PCIDIVMODE_5_5 0x00001c00
262
263/* PCFG : Pin Configuration */
264#define TX4927_PCFG_PCICLKEN_ALL 0x003f0000
265#define TX4927_PCFG_PCICLKEN(ch) (0x00010000<<(ch))
266
267/* CLKCTR : Clock Control */
268#define TX4927_CLKCTR_PCICKD 0x00400000
269#define TX4927_CLKCTR_PCIRST 0x00000040
270
271#ifndef _LANGUAGE_ASSEMBLY
272
273#define tx4927_sdramcptr ((struct tx4927_sdramc_reg *)TX4927_SDRAMC_REG)
274#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
275#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
276#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
277
278#endif /* _LANGUAGE_ASSEMBLY */
279
280#endif /* __ASM_TX4927_TX4927_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-02 11:41:27 -0400