[MIPS] Make support for weakly ordered LL/SC a config option.

None of weakly ordered processor supported in tree need this but it seems
like this could change ...

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 4 insertions, 4 deletions

diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 76339165bc20..eba2e3da9abe 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -117,7 +117,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
                 raw_local_irq_restore(flags);   /* implies memory barrier  */
         }
 
-        smp_mb();
+        smp_llsc_mb();
 
         return retval;
 }
@@ -165,7 +165,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
                 raw_local_irq_restore(flags);   /* implies memory barrier  */
         }
 
-        smp_mb();
+        smp_llsc_mb();
 
         return retval;
 }
@@ -246,7 +246,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
                 raw_local_irq_restore(flags);   /* implies memory barrier  */
         }
 
-        smp_mb();
+        smp_llsc_mb();
 
         return retval;
 }
@@ -352,7 +352,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
                 raw_local_irq_restore(flags);   /* implies memory barrier  */
         }
 
-        smp_mb();
+        smp_llsc_mb();
 
         return retval;
 }