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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2006-12-28 12:22:32 -0500
committerRalf Baechle <ralf@linux-mips.org>2007-02-18 16:31:37 -0500
commitc066a32a890c50ce59e91f8cea8eb5fd8d5821b9 (patch)
treed129af235d11d44c649f0743bc38535c3a229e41 /include/asm-mips/sni.h
parent5759906ca9e5201c3fd40d61c861ec1e441d3a24 (diff)
[MIPS] Support for several more SNI RM models.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/sni.h')
-rw-r--r--include/asm-mips/sni.h132
1 files changed, 124 insertions, 8 deletions
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index b9ba54d0dd35..62f9be6f7320 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -6,12 +6,72 @@
6 * for more details. 6 * for more details.
7 * 7 *
8 * Copyright (C) 1997, 1998 by Ralf Baechle 8 * Copyright (C) 1997, 1998 by Ralf Baechle
9 * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
9 */ 10 */
10#ifndef __ASM_SNI_H 11#ifndef __ASM_SNI_H
11#define __ASM_SNI_H 12#define __ASM_SNI_H
12 13
14extern unsigned int sni_brd_type;
15
16#define SNI_BRD_10 2
17#define SNI_BRD_10NEW 3
18#define SNI_BRD_TOWER_OASIC 4
19#define SNI_BRD_MINITOWER 5
20#define SNI_BRD_PCI_TOWER 6
21#define SNI_BRD_RM200 7
22#define SNI_BRD_PCI_MTOWER 8
23#define SNI_BRD_PCI_DESKTOP 9
24#define SNI_BRD_PCI_TOWER_CPLUS 10
25#define SNI_BRD_PCI_MTOWER_CPLUS 11
26
27/* RM400 cpu types */
28#define SNI_CPU_M8021 0x01
29#define SNI_CPU_M8030 0x04
30#define SNI_CPU_M8031 0x06
31#define SNI_CPU_M8034 0x0f
32#define SNI_CPU_M8037 0x07
33#define SNI_CPU_M8040 0x05
34#define SNI_CPU_M8043 0x09
35#define SNI_CPU_M8050 0x0b
36#define SNI_CPU_M8053 0x0d
37
13#define SNI_PORT_BASE 0xb4000000 38#define SNI_PORT_BASE 0xb4000000
14 39
40#ifndef __MIPSEL__
41/*
42 * ASIC PCI registers for big endian configuration.
43 */
44#define PCIMT_UCONF 0xbfff0004
45#define PCIMT_IOADTIMEOUT2 0xbfff000c
46#define PCIMT_IOMEMCONF 0xbfff0014
47#define PCIMT_IOMMU 0xbfff001c
48#define PCIMT_IOADTIMEOUT1 0xbfff0024
49#define PCIMT_DMAACCESS 0xbfff002c
50#define PCIMT_DMAHIT 0xbfff0034
51#define PCIMT_ERRSTATUS 0xbfff003c
52#define PCIMT_ERRADDR 0xbfff0044
53#define PCIMT_SYNDROME 0xbfff004c
54#define PCIMT_ITPEND 0xbfff0054
55#define IT_INT2 0x01
56#define IT_INTD 0x02
57#define IT_INTC 0x04
58#define IT_INTB 0x08
59#define IT_INTA 0x10
60#define IT_EISA 0x20
61#define IT_SCSI 0x40
62#define IT_ETH 0x80
63#define PCIMT_IRQSEL 0xbfff005c
64#define PCIMT_TESTMEM 0xbfff0064
65#define PCIMT_ECCREG 0xbfff006c
66#define PCIMT_CONFIG_ADDRESS 0xbfff0074
67#define PCIMT_ASIC_ID 0xbfff007c /* read */
68#define PCIMT_SOFT_RESET 0xbfff007c /* write */
69#define PCIMT_PIA_OE 0xbfff0084
70#define PCIMT_PIA_DATAOUT 0xbfff008c
71#define PCIMT_PIA_DATAIN 0xbfff0094
72#define PCIMT_CACHECONF 0xbfff009c
73#define PCIMT_INVSPACE 0xbfff00a4
74#else
15/* 75/*
16 * ASIC PCI registers for little endian configuration. 76 * ASIC PCI registers for little endian configuration.
17 */ 77 */
@@ -45,6 +105,8 @@
45#define PCIMT_PIA_DATAIN 0xbfff0090 105#define PCIMT_PIA_DATAIN 0xbfff0090
46#define PCIMT_CACHECONF 0xbfff0098 106#define PCIMT_CACHECONF 0xbfff0098
47#define PCIMT_INVSPACE 0xbfff00a0 107#define PCIMT_INVSPACE 0xbfff00a0
108#endif
109
48#define PCIMT_PCI_CONF 0xbfff0100 110#define PCIMT_PCI_CONF 0xbfff0100
49 111
50/* 112/*
@@ -73,6 +135,36 @@
73#define PCIMT_PWDN 0xbfdf0000 135#define PCIMT_PWDN 0xbfdf0000
74 136
75/* 137/*
138 * A20R based boards
139 */
140#define A20R_PT_CLOCK_BASE 0xbc040000
141#define A20R_PT_TIM0_ACK 0xbc050000
142#define A20R_PT_TIM1_ACK 0xbc060000
143
144#define SNI_MIPS_IRQ_CPU_BASE 16
145#define SNI_MIPS_IRQ_CPU_TIMER (SNI_MIPS_IRQ_CPU_BASE+7)
146
147#define SNI_A20R_IRQ_BASE SNI_MIPS_IRQ_CPU_BASE
148#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
149
150#define SNI_DS1216_A20R_BASE 0xbc081ffc
151#define SNI_DS1216_RM200_BASE 0xbcd41ffc
152
153#define SNI_PCIT_INT_REG 0xbfff000c
154
155#define SNI_PCIT_INT_START 24
156#define SNI_PCIT_INT_END 30
157
158#define PCIT_IRQ_ETHERNET (SNI_MIPS_IRQ_CPU_BASE + 5)
159#define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0)
160#define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1)
161#define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2)
162#define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3)
163#define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4)
164#define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5)
165
166
167/*
76 * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned 168 * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned
77 * to the other interrupts generated by ASIC PCI. 169 * to the other interrupts generated by ASIC PCI.
78 * 170 *
@@ -80,18 +172,22 @@
80 * ASIC PCI interrupt. 172 * ASIC PCI interrupt.
81 */ 173 */
82#define PCIMT_KEYBOARD_IRQ 1 174#define PCIMT_KEYBOARD_IRQ 1
83#define PCIMT_IRQ_INT2 16 175#define PCIMT_IRQ_INT2 24
84#define PCIMT_IRQ_INTD 17 176#define PCIMT_IRQ_INTD 25
85#define PCIMT_IRQ_INTC 18 177#define PCIMT_IRQ_INTC 26
86#define PCIMT_IRQ_INTB 19 178#define PCIMT_IRQ_INTB 27
87#define PCIMT_IRQ_INTA 20 179#define PCIMT_IRQ_INTA 28
88#define PCIMT_IRQ_EISA 21 180#define PCIMT_IRQ_EISA 29
89#define PCIMT_IRQ_SCSI 22 181#define PCIMT_IRQ_SCSI 30
90#define PCIMT_IRQ_ETHERNET 23 182
183#define PCIMT_IRQ_ETHERNET (SNI_MIPS_IRQ_CPU_BASE+6)
184
185#if 0
91#define PCIMT_IRQ_TEMPERATURE 24 186#define PCIMT_IRQ_TEMPERATURE 24
92#define PCIMT_IRQ_EISA_NMI 25 187#define PCIMT_IRQ_EISA_NMI 25
93#define PCIMT_IRQ_POWER_OFF 26 188#define PCIMT_IRQ_POWER_OFF 26
94#define PCIMT_IRQ_BUTTON 27 189#define PCIMT_IRQ_BUTTON 27
190#endif
95 191
96/* 192/*
97 * Base address for the mapped 16mb EISA bus segment. 193 * Base address for the mapped 16mb EISA bus segment.
@@ -101,4 +197,24 @@
101/* PCI EISA Interrupt acknowledge */ 197/* PCI EISA Interrupt acknowledge */
102#define PCIMT_INT_ACKNOWLEDGE 0xba000000 198#define PCIMT_INT_ACKNOWLEDGE 0xba000000
103 199
200/* board specific init functions */
201extern void sni_a20r_init (void);
202extern void sni_pcit_init (void);
203extern void sni_rm200_init (void);
204extern void sni_pcimt_init (void);
205
206/* board specific irq init functions */
207extern void sni_a20r_irq_init (void);
208extern void sni_pcit_irq_init (void);
209extern void sni_pcit_cplus_irq_init (void);
210extern void sni_rm200_irq_init (void);
211extern void sni_pcimt_irq_init (void);
212
213/* timer inits */
214extern void sni_cpu_time_init(void);
215
216/* common irq stuff */
217extern void (*sni_hwint)(void);
218extern struct irqaction sni_isa_irq;
219
104#endif /* __ASM_SNI_H */ 220#endif /* __ASM_SNI_H */