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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2007-02-23 15:39:38 -0500
committerRalf Baechle <ralf@linux-mips.org>2007-02-26 18:06:06 -0500
commitf13cc01d8d3630ba42680ac56b3bedfce812e531 (patch)
tree0737d5e36474827dff3bc05cb1071946b3e366fa /include/asm-mips/sni.h
parent3dac2561e2ed8d75a8bb682c25a32b271298ff49 (diff)
[MIPS] SNI: MIPS_CPU_IRQ_BASE cleanup
Use MIPS_CPU_IRQ_BASE instead of own define. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/sni.h')
-rw-r--r--include/asm-mips/sni.h9
1 files changed, 4 insertions, 5 deletions
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
index 62f9be6f7320..f257509b914f 100644
--- a/include/asm-mips/sni.h
+++ b/include/asm-mips/sni.h
@@ -141,10 +141,9 @@ extern unsigned int sni_brd_type;
141#define A20R_PT_TIM0_ACK 0xbc050000 141#define A20R_PT_TIM0_ACK 0xbc050000
142#define A20R_PT_TIM1_ACK 0xbc060000 142#define A20R_PT_TIM1_ACK 0xbc060000
143 143
144#define SNI_MIPS_IRQ_CPU_BASE 16 144#define SNI_MIPS_IRQ_CPU_TIMER (MIPS_CPU_IRQ_BASE+7)
145#define SNI_MIPS_IRQ_CPU_TIMER (SNI_MIPS_IRQ_CPU_BASE+7)
146 145
147#define SNI_A20R_IRQ_BASE SNI_MIPS_IRQ_CPU_BASE 146#define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
148#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) 147#define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
149 148
150#define SNI_DS1216_A20R_BASE 0xbc081ffc 149#define SNI_DS1216_A20R_BASE 0xbc081ffc
@@ -155,7 +154,7 @@ extern unsigned int sni_brd_type;
155#define SNI_PCIT_INT_START 24 154#define SNI_PCIT_INT_START 24
156#define SNI_PCIT_INT_END 30 155#define SNI_PCIT_INT_END 30
157 156
158#define PCIT_IRQ_ETHERNET (SNI_MIPS_IRQ_CPU_BASE + 5) 157#define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)
159#define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0) 158#define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0)
160#define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1) 159#define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1)
161#define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2) 160#define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2)
@@ -180,7 +179,7 @@ extern unsigned int sni_brd_type;
180#define PCIMT_IRQ_EISA 29 179#define PCIMT_IRQ_EISA 29
181#define PCIMT_IRQ_SCSI 30 180#define PCIMT_IRQ_SCSI 30
182 181
183#define PCIMT_IRQ_ETHERNET (SNI_MIPS_IRQ_CPU_BASE+6) 182#define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)
184 183
185#if 0 184#if 0
186#define PCIMT_IRQ_TEMPERATURE 24 185#define PCIMT_IRQ_TEMPERATURE 24