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authorRalf Baechle <ralf@linux-mips.org>2006-03-11 03:18:41 -0500
committerRalf Baechle <ralf@linux-mips.org>2006-03-21 08:27:47 -0500
commita3dddd560ee936495466d85ecc97490d171e8d31 (patch)
treee9b5d778b5249ce348d2285a9b886b83c510d813 /include/asm-mips/sn/sn0
parent59b3e8e9aac69d2d02853acac7e2affdfbabca50 (diff)
[MIPS] War on whitespace: cleanup initial spaces followed by tabs.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/sn/sn0')
-rw-r--r--include/asm-mips/sn/sn0/hubio.h12
1 files changed, 6 insertions, 6 deletions
diff --git a/include/asm-mips/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h
index 80cf6a52ed3b..f314da21b970 100644
--- a/include/asm-mips/sn/sn0/hubio.h
+++ b/include/asm-mips/sn/sn0/hubio.h
@@ -229,7 +229,7 @@ typedef union hubii_ilcsr_u {
229 icsr_llp_en: 1, /* LLP enable bit */ 229 icsr_llp_en: 1, /* LLP enable bit */
230 icsr_rsvd2: 1, /* reserver */ 230 icsr_rsvd2: 1, /* reserver */
231 icsr_wrm_reset: 1, /* Warm reset bit */ 231 icsr_wrm_reset: 1, /* Warm reset bit */
232 icsr_rsvd1: 2, /* Data ready offset */ 232 icsr_rsvd1: 2, /* Data ready offset */
233 icsr_null_to: 6; /* Null timeout */ 233 icsr_null_to: 6; /* Null timeout */
234 234
235 } icsr_fields_s; 235 } icsr_fields_s;
@@ -274,9 +274,9 @@ typedef union io_perf_sel {
274 u64 perf_sel_reg; 274 u64 perf_sel_reg;
275 struct { 275 struct {
276 u64 perf_rsvd : 48, 276 u64 perf_rsvd : 48,
277 perf_icct : 8, 277 perf_icct : 8,
278 perf_ippr1 : 4, 278 perf_ippr1 : 4,
279 perf_ippr0 : 4; 279 perf_ippr0 : 4;
280 } perf_sel_bits; 280 } perf_sel_bits;
281} io_perf_sel_t; 281} io_perf_sel_t;
282 282
@@ -287,8 +287,8 @@ typedef union io_perf_cnt {
287 u64 perf_cnt; 287 u64 perf_cnt;
288 struct { 288 struct {
289 u64 perf_rsvd1 : 32, 289 u64 perf_rsvd1 : 32,
290 perf_rsvd2 : 12, 290 perf_rsvd2 : 12,
291 perf_cnt : 20; 291 perf_cnt : 20;
292 } perf_cnt_bits; 292 } perf_cnt_bits;
293} io_perf_cnt_t; 293} io_perf_cnt_t;
294 294