Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

9 files changed, 3093 insertions, 0 deletions

diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h
new file mode 100644
index 000000000000..398815639fb8
--- /dev/null
+++ b/include/asm-mips/sn/sn0/addrs.h
@@ -0,0 +1,364 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_ADDRS_H
+#define _ASM_SN_SN0_ADDRS_H
+
+#include <linux/config.h>
+
+/*
+ * SN0 (on a T5) Address map
+ *
+ * This file contains a set of definitions and macros which are used
+ * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
+ * and UNCAC) used by the SN0 architecture.  It also contains addresses
+ * for "major" statically locatable PROM/Kernel data structures, such as
+ * the partition table, the configuration data structure, etc.
+ * We make an implicit assumption that the processor using this file
+ * follows the R10K's provisions for specifying uncached attributes;
+ * should this change, the base registers may very well become processor-
+ * dependent.
+ *
+ * For more information on the address spaces, see the "Local Resources"
+ * chapter of the Hub specification.
+ *
+ * NOTE: This header file is included both by C and by assembler source
+ *       files.  Please bracket any language-dependent definitions
+ *       appropriately.
+ */
+
+/*
+ * Some of the macros here need to be casted to appropriate types when used
+ * from C.  They definitely must not be casted from assembly language so we
+ * use some new ANSI preprocessor stuff to paste these on where needed.
+ */
+
+/*
+ * The following couple of definitions will eventually need to be variables,
+ * since the amount of address space assigned to each node depends on
+ * whether the system is running in N-mode (more nodes with less memory)
+ * or M-mode (fewer nodes with more memory).  We expect that it will
+ * be a while before we need to make this decision dynamically, though,
+ * so for now we just use defines bracketed by an ifdef.
+ */
+
+#ifdef CONFIG_SGI_SN0_N_MODE
+
+#define NODE_SIZE_BITS          31
+#define BWIN_SIZE_BITS          28
+
+#define NASID_BITS              9
+#define NASID_BITMASK           (0x1ffLL)
+#define NASID_SHFT              31
+#define NASID_META_BITS         5
+#define NASID_LOCAL_BITS        4
+
+#define BDDIR_UPPER_MASK        (UINT64_CAST 0x7ffff << 10)
+#define BDECC_UPPER_MASK        (UINT64_CAST 0x3ffffff << 3)
+
+#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */
+
+#define NODE_SIZE_BITS          32
+#define BWIN_SIZE_BITS          29
+
+#define NASID_BITMASK           (0xffLL)
+#define NASID_BITS              8
+#define NASID_SHFT              32
+#define NASID_META_BITS         4
+#define NASID_LOCAL_BITS        4
+
+#define BDDIR_UPPER_MASK        (UINT64_CAST 0xfffff << 10)
+#define BDECC_UPPER_MASK        (UINT64_CAST 0x7ffffff << 3)
+
+#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */
+
+#define NODE_ADDRSPACE_SIZE     (UINT64_CAST 1 << NODE_SIZE_BITS)
+
+#define NASID_MASK              (UINT64_CAST NASID_BITMASK << NASID_SHFT)
+#define NASID_GET(_pa)          (int) ((UINT64_CAST (_pa) >>            \
+                                        NASID_SHFT) & NASID_BITMASK)
+
+#if !defined(__ASSEMBLY__) && !defined(_STANDALONE)
+
+#define NODE_SWIN_BASE(nasid, widget)                                   \
+        ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)          \
+        : RAW_NODE_SWIN_BASE(nasid, widget))
+#else /* __ASSEMBLY__ || _STANDALONE */
+#define NODE_SWIN_BASE(nasid, widget) \
+     (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
+#endif /* __ASSEMBLY__ || _STANDALONE */
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define BWIN_INDEX_BITS         3
+#define BWIN_SIZE               (UINT64_CAST 1 << BWIN_SIZE_BITS)
+#define BWIN_SIZEMASK           (BWIN_SIZE - 1)
+#define BWIN_WIDGET_MASK        0x7
+#define NODE_BWIN_BASE0(nasid)  (NODE_IO_BASE(nasid) + BWIN_SIZE)
+#define NODE_BWIN_BASE(nasid, bigwin)   (NODE_BWIN_BASE0(nasid) +       \
+                        (UINT64_CAST (bigwin) << BWIN_SIZE_BITS))
+
+#define BWIN_WIDGETADDR(addr)   ((addr) & BWIN_SIZEMASK)
+#define BWIN_WINDOWNUM(addr)    (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+/*
+ * Verify if addr belongs to large window address of node with "nasid"
+ *
+ *
+ * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
+ * address
+ *
+ *
+ */
+
+#define NODE_BWIN_ADDR(nasid, addr)     \
+                (((addr) >= NODE_BWIN_BASE0(nasid)) && \
+                 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
+                                BWIN_SIZE)))
+
+/*
+ * The following define the major position-independent aliases used
+ * in SN0.
+ *      CALIAS -- Varies in size, points to the first n bytes of memory
+ *                      on the reader's node.
+ */
+
+#define CALIAS_BASE             CAC_BASE
+
+
+
+#define BRIDGE_REG_PTR(_base, _off)     ((volatile bridgereg_t *) \
+        ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
+
+#define SN0_WIDGET_BASE(_nasid, _wid)   (NODE_SWIN_BASE((_nasid), (_wid)))
+
+/* Turn on sable logging for the processors whose bits are set. */
+#ifdef SABLE
+#define SABLE_LOG_TRIGGER(_map) \
+                *((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map)
+#else
+#define SABLE_LOG_TRIGGER(_map)
+#endif /* SABLE */
+
+#ifndef __ASSEMBLY__
+#define KERN_NMI_ADDR(nasid, slice)                                     \
+                    TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET +      \
+                                  (IP27_NMI_KREGS_CPU_SIZE * (slice)))
+#endif /* !__ASSEMBLY__ */
+
+#ifdef PROM
+
+#define MISC_PROM_BASE          PHYS_TO_K0(0x01300000)
+#define MISC_PROM_SIZE          0x200000
+
+#define DIAG_BASE               PHYS_TO_K0(0x01500000)
+#define DIAG_SIZE               0x300000
+
+#define ROUTE_BASE              PHYS_TO_K0(0x01800000)
+#define ROUTE_SIZE              0x200000
+
+#define IP27PROM_FLASH_HDR      PHYS_TO_K0(0x01300000)
+#define IP27PROM_FLASH_DATA     PHYS_TO_K0(0x01301000)
+#define IP27PROM_CORP_MAX       32
+#define IP27PROM_CORP           PHYS_TO_K0(0x01800000)
+#define IP27PROM_CORP_SIZE      0x10000
+#define IP27PROM_CORP_STK       PHYS_TO_K0(0x01810000)
+#define IP27PROM_CORP_STKSIZE   0x2000
+#define IP27PROM_DECOMP_BUF     PHYS_TO_K0(0x01900000)
+#define IP27PROM_DECOMP_SIZE    0xfff00
+
+#define IP27PROM_BASE           PHYS_TO_K0(0x01a00000)
+#define IP27PROM_BASE_MAPPED    (UNCAC_BASE | 0x1fc00000)
+#define IP27PROM_SIZE_MAX       0x100000
+
+#define IP27PROM_PCFG           PHYS_TO_K0(0x01b00000)
+#define IP27PROM_PCFG_SIZE      0xd0000
+#define IP27PROM_ERRDMP         PHYS_TO_K1(0x01bd0000)
+#define IP27PROM_ERRDMP_SIZE    0xf000
+
+#define IP27PROM_INIT_START     PHYS_TO_K1(0x01bd0000)
+#define IP27PROM_CONSOLE        PHYS_TO_K1(0x01bdf000)
+#define IP27PROM_CONSOLE_SIZE   0x200
+#define IP27PROM_NETUART        PHYS_TO_K1(0x01bdf200)
+#define IP27PROM_NETUART_SIZE   0x100
+#define IP27PROM_UNUSED1        PHYS_TO_K1(0x01bdf300)
+#define IP27PROM_UNUSED1_SIZE   0x500
+#define IP27PROM_ELSC_BASE_A    PHYS_TO_K0(0x01bdf800)
+#define IP27PROM_ELSC_BASE_B    PHYS_TO_K0(0x01bdfc00)
+#define IP27PROM_STACK_A        PHYS_TO_K0(0x01be0000)
+#define IP27PROM_STACK_B        PHYS_TO_K0(0x01bf0000)
+#define IP27PROM_STACK_SHFT     16
+#define IP27PROM_STACK_SIZE     (1 << IP27PROM_STACK_SHFT)
+#define IP27PROM_INIT_END       PHYS_TO_K0(0x01c00000)
+
+#define SLAVESTACK_BASE         PHYS_TO_K0(0x01580000)
+#define SLAVESTACK_SIZE         0x40000
+
+#define ENETBUFS_BASE           PHYS_TO_K0(0x01f80000)
+#define ENETBUFS_SIZE           0x20000
+
+#define IO6PROM_BASE            PHYS_TO_K0(0x01c00000)
+#define IO6PROM_SIZE            0x400000
+#define IO6PROM_BASE_MAPPED     (UNCAC_BASE | 0x11c00000)
+#define IO6DPROM_BASE           PHYS_TO_K0(0x01c00000)
+#define IO6DPROM_SIZE           0x200000
+
+#define NODEBUGUNIX_ADDR        PHYS_TO_K0(0x00019000)
+#define DEBUGUNIX_ADDR          PHYS_TO_K0(0x00100000)
+
+#define IP27PROM_INT_LAUNCH     10      /* and 11 */
+#define IP27PROM_INT_NETUART    12      /* through 17 */
+
+#endif /* PROM */
+
+/*
+ * needed by symmon so it needs to be outside #if PROM
+ */
+#define IP27PROM_ELSC_SHFT      10
+#define IP27PROM_ELSC_SIZE      (1 << IP27PROM_ELSC_SHFT)
+
+/*
+ * This address is used by IO6PROM to build MemoryDescriptors of
+ * free memory. This address is important since unix gets loaded
+ * at this address, and this memory has to be FREE if unix is to
+ * be loaded.
+ */
+
+#define FREEMEM_BASE            PHYS_TO_K0(0x2000000)
+
+#define IO6PROM_STACK_SHFT      14      /* stack per cpu */
+#define IO6PROM_STACK_SIZE      (1 << IO6PROM_STACK_SHFT)
+
+/*
+ * IP27 PROM vectors
+ */
+
+#define IP27PROM_ENTRY          PHYS_TO_COMPATK1(0x1fc00000)
+#define IP27PROM_RESTART        PHYS_TO_COMPATK1(0x1fc00008)
+#define IP27PROM_SLAVELOOP      PHYS_TO_COMPATK1(0x1fc00010)
+#define IP27PROM_PODMODE        PHYS_TO_COMPATK1(0x1fc00018)
+#define IP27PROM_IOC3UARTPOD    PHYS_TO_COMPATK1(0x1fc00020)
+#define IP27PROM_FLASHLEDS      PHYS_TO_COMPATK1(0x1fc00028)
+#define IP27PROM_REPOD          PHYS_TO_COMPATK1(0x1fc00030)
+#define IP27PROM_LAUNCHSLAVE    PHYS_TO_COMPATK1(0x1fc00038)
+#define IP27PROM_WAITSLAVE      PHYS_TO_COMPATK1(0x1fc00040)
+#define IP27PROM_POLLSLAVE      PHYS_TO_COMPATK1(0x1fc00048)
+
+#define KL_UART_BASE    LOCAL_HUB_ADDR(MD_UREG0_0)      /* base of UART regs */
+#define KL_UART_CMD     LOCAL_HUB_ADDR(MD_UREG0_0)      /* UART command reg */
+#define KL_UART_DATA    LOCAL_HUB_ADDR(MD_UREG0_1)      /* UART data reg */
+#define KL_I2C_REG      MD_UREG0_0                      /* I2C reg */
+
+#ifndef __ASSEMBLY__
+
+/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
+ * CACHE_ERR_SP_PTR could either contain an address to the stack, or
+ * the stack could start at CACHE_ERR_SP_PTR
+ */
+#if defined (HUB_ERR_STS_WAR)
+#define CACHE_ERR_EFRAME        0x480
+#else /* HUB_ERR_STS_WAR */
+#define CACHE_ERR_EFRAME        0x400
+#endif /* HUB_ERR_STS_WAR */
+
+#define CACHE_ERR_ECCFRAME      (CACHE_ERR_EFRAME + EF_SIZE)
+#define CACHE_ERR_SP_PTR        (0x1000 - 32)   /* why -32? TBD */
+#define CACHE_ERR_IBASE_PTR     (0x1000 - 40)
+#define CACHE_ERR_SP            (CACHE_ERR_SP_PTR - 16)
+#define CACHE_ERR_AREA_SIZE     (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
+
+#endif  /* !__ASSEMBLY__ */
+
+#define _ARCSPROM
+
+#ifdef _STANDALONE
+
+/*
+ * The PROM needs to pass the device base address and the
+ * device pci cfg space address to the device drivers during
+ * install. The COMPONENT->Key field is used for this purpose.
+ * Macros needed by SN0 device drivers to convert the
+ * COMPONENT->Key field to the respective base address.
+ * Key field looks as follows:
+ *
+ *  +----------------------------------------------------+
+ *  |devnasid | widget  |pciid |hubwidid|hstnasid | adap |
+ *  |   2     |   1     |  1   |   1    |    2    |   1  |
+ *  +----------------------------------------------------+
+ *  |         |         |      |        |         |      |
+ *  64        48        40     32       24        8      0
+ *
+ * These are used by standalone drivers till the io infrastructure
+ * is in place.
+ */
+
+#ifndef __ASSEMBLY__
+
+#define uchar unsigned char
+
+#define KEY_DEVNASID_SHFT  48
+#define KEY_WIDID_SHFT     40
+#define KEY_PCIID_SHFT     32
+#define KEY_HUBWID_SHFT    24
+#define KEY_HSTNASID_SHFT  8
+
+#define MK_SN0_KEY(nasid, widid, pciid) \
+                        ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
+                                ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
+                                ((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
+
+#define ADD_HUBWID_KEY(key,hubwid)\
+                        (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
+
+#define ADD_HSTNASID_KEY(key,hstnasid)\
+                        (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
+
+#define GET_DEVNASID_FROM_KEY(key)      ((short)(key >> KEY_DEVNASID_SHFT))
+#define GET_WIDID_FROM_KEY(key)         ((uchar)(key >> KEY_WIDID_SHFT))
+#define GET_PCIID_FROM_KEY(key)         ((uchar)(key >> KEY_PCIID_SHFT))
+#define GET_HUBWID_FROM_KEY(key)        ((uchar)(key >> KEY_HUBWID_SHFT))
+#define GET_HSTNASID_FROM_KEY(key)      ((short)(key >> KEY_HSTNASID_SHFT))
+
+#define PCI_64_TARGID_SHFT              60
+
+#define GET_PCIBASE_FROM_KEY(key)  (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+                                        GET_WIDID_FROM_KEY(key))\
+                                        | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
+
+#define GET_PCICFGBASE_FROM_KEY(key) \
+                        (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+                              GET_WIDID_FROM_KEY(key))\
+                        | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
+
+#define GET_WIDBASE_FROM_KEY(key) \
+                        (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
+                              GET_WIDID_FROM_KEY(key)))
+
+#define PUT_INSTALL_STATUS(c,s)         c->Revision = s
+#define GET_INSTALL_STATUS(c)           c->Revision
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _STANDALONE */
+
+#if defined (HUB_ERR_STS_WAR)
+
+#define ERR_STS_WAR_REGISTER    IIO_IIBUSERR
+#define ERR_STS_WAR_ADDR        LOCAL_HUB_ADDR(IIO_IIBUSERR)
+#define ERR_STS_WAR_PHYSADDR    TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
+                                /* Used to match addr in error reg. */
+#define OLD_ERR_STS_WAR_OFFSET  ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
+
+#endif /* HUB_ERR_STS_WAR */
+
+#endif /* _ASM_SN_SN0_ADDRS_H */
diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h
new file mode 100644
index 000000000000..0e00dd474afc
--- /dev/null
+++ b/include/asm-mips/sn/sn0/arch.h
@@ -0,0 +1,89 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * SGI IP27 specific setup.
+ *
+ * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SN_SN0_ARCH_H
+#define _ASM_SN_SN0_ARCH_H
+
+#include <linux/config.h>
+
+#ifndef SABLE
+
+#ifndef SN0XXL  /* 128 cpu SMP max */
+/*
+ * This is the maximum number of nodes that can be part of a kernel.
+ * Effectively, it's the maximum number of compact node ids (cnodeid_t).
+ */
+#define MAX_COMPACT_NODES       64
+
+/*
+ * MAXCPUS refers to the maximum number of CPUs in a single kernel.
+ * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
+ */
+#define MAXCPUS                 128
+
+#else /* SN0XXL system */
+
+#define MAX_COMPACT_NODES       128
+#define MAXCPUS                 256
+
+#endif /* SN0XXL */
+
+/*
+ * This is the maximum number of NASIDS that can be present in a system.
+ * (Highest NASID plus one.)
+ */
+#define MAX_NASIDS              256
+
+/*
+ * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
+ */
+#define MAX_REGIONS             64
+#define MAX_NONPREMIUM_REGIONS  16
+#define MAX_PREMIUM_REGIONS     MAX_REGIONS
+
+/*
+ * MAX_PARITIONS refers to the maximum number of logically defined
+ * partitions the system can support.
+ */
+#define MAX_PARTITIONS          MAX_REGIONS
+
+
+#else
+
+#define MAX_COMPACT_NODES       4
+#define MAX_NASIDS              4
+#define MAXCPUS                 8
+
+#endif
+
+#define NASID_MASK_BYTES        ((MAX_NASIDS + 7) / 8)
+
+/*
+ * Slot constants for SN0
+ */
+#ifdef CONFIG_SGI_SN0_N_MODE
+#define MAX_MEM_SLOTS   16                      /* max slots per node */
+#else /* !CONFIG_SGI_SN0_N_MODE, assume M_MODE */
+#define MAX_MEM_SLOTS   32                      /* max slots per node */
+#endif /* defined(N_MODE) */
+
+#if SABLE_RTL
+#define SLOT_SHIFT              (28)
+#define SLOT_MIN_MEM_SIZE       (16*1024*1024)
+#else
+#define SLOT_SHIFT              (27)
+#define SLOT_MIN_MEM_SIZE       (32*1024*1024)
+#endif
+
+#define CPUS_PER_NODE           2       /* CPUs on a single hub */
+#define CPUS_PER_NODE_SHFT      1       /* Bits to shift in the node number */
+#define CPUS_PER_SUBNODE        2       /* CPUs on a single hub PI */
+
+#endif /* _ASM_SN_SN0_ARCH_H */
diff --git a/include/asm-mips/sn/sn0/hub.h b/include/asm-mips/sn/sn0/hub.h
new file mode 100644
index 000000000000..f5dbba6f4610
--- /dev/null
+++ b/include/asm-mips/sn/sn0/hub.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUB_H
+#define _ASM_SN_SN0_HUB_H
+
+/* The secret password; used to release protection */
+#define HUB_PASSWORD            0x53474972756c6573ull
+
+#define CHIPID_HUB              0
+#define CHIPID_ROUTER           1
+
+#define HUB_REV_1_0             1
+#define HUB_REV_2_0             2
+#define HUB_REV_2_1             3
+#define HUB_REV_2_2             4
+#define HUB_REV_2_3             5
+#define HUB_REV_2_4             6
+
+#define MAX_HUB_PATH            80
+
+#include <asm/sn/sn0/addrs.h>
+#include <asm/sn/sn0/hubpi.h>
+#include <asm/sn/sn0/hubmd.h>
+#include <asm/sn/sn0/hubio.h>
+#include <asm/sn/sn0/hubni.h>
+//#include <asm/sn/sn0/hubcore.h>
+
+#ifdef SABLE
+#define IP27_NO_HUBUART_INT     1
+#endif
+
+/* Translation of uncached attributes */
+#define UATTR_HSPEC     0
+#define UATTR_IO        1
+#define UATTR_MSPEC     2
+#define UATTR_UNCAC     3
+
+#endif /* _ASM_SN_SN0_HUB_H */
diff --git a/include/asm-mips/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h
new file mode 100644
index 000000000000..80cf6a52ed3b
--- /dev/null
+++ b/include/asm-mips/sn/sn0/hubio.h
@@ -0,0 +1,988 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SGI_SN_SN0_HUBIO_H
+#define _ASM_SGI_SN_SN0_HUBIO_H
+
+/*
+ * Hub I/O interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ * In general, the longer software name should be used when available.
+ */
+
+/*
+ * Slightly friendlier names for some common registers.
+ * The hardware definitions follow.
+ */
+#define IIO_WIDGET              IIO_WID      /* Widget identification */
+#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
+#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
+#define IIO_WIDGET_TOUT         IIO_WRTO     /* Widget request timeout */
+#define IIO_WIDGET_FLUSH        IIO_WTFR     /* Widget target flush */
+#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
+#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
+#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
+#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
+#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
+#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
+#define IIO_BTE_CRB_CNT         IIO_IBCN     /* IO BTE CRB count */
+
+#define IIO_LLP_CSR_IS_UP               0x00002000
+#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT       12
+
+/* key to IIO_PROTECT_OVRRD */
+#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
+
+/* BTE register names */
+#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
+#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
+#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1   IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
+
+/* BTE register offsets from base */
+#define BTEOFF_STAT             0
+#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
+
+
+/*
+ * The following definitions use the names defined in the IO interface
+ * document for ease of reference.  When possible, software should
+ * generally use the longer but clearer names defined above.
+ */
+
+#define IIO_BASE        0x400000
+#define IIO_BASE_BTE0   0x410000
+#define IIO_BASE_BTE1   0x420000
+#define IIO_BASE_PERF   0x430000
+#define IIO_PERF_CNT    0x430008
+
+#define IO_PERF_SETS    32
+
+#define IIO_WID         0x400000        /* Widget identification */
+#define IIO_WSTAT       0x400008        /* Widget status */
+#define IIO_WCR         0x400020        /* Widget control */
+
+#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  (0x7F)
+#define IIO_WSTAT_TXRETRY_SHFT  (16)
+#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+                                          IIO_WSTAT_TXRETRY_MASK)
+
+#define IIO_ILAPR       0x400100        /* Local Access Protection */
+#define IIO_ILAPO       0x400108        /* Protection override */
+#define IIO_IOWA        0x400110        /* outbound widget access */
+#define IIO_IIWA        0x400118        /* inbound widget access */
+#define IIO_IIDEM       0x400120        /* Inbound Device Error Mask */
+#define IIO_ILCSR       0x400128        /* LLP control and status */
+#define IIO_ILLR        0x400130        /* LLP Log */
+#define IIO_IIDSR       0x400138        /* Interrupt destination */
+
+#define IIO_IIBUSERR    0x1400208       /* Reads here cause a bus error. */
+
+/* IO Interrupt Destination Register */
+#define IIO_IIDSR_SENT_SHIFT    28
+#define IIO_IIDSR_SENT_MASK     0x10000000
+#define IIO_IIDSR_ENB_SHIFT     24
+#define IIO_IIDSR_ENB_MASK      0x01000000
+#define IIO_IIDSR_NODE_SHIFT    8
+#define IIO_IIDSR_NODE_MASK     0x0000ff00
+#define IIO_IIDSR_LVL_SHIFT     0
+#define IIO_IIDSR_LVL_MASK      0x0000003f
+
+
+/* GFX Flow Control Node/Widget Register */
+#define IIO_IGFX_0      0x400140        /* gfx node/widget register 0 */
+#define IIO_IGFX_1      0x400148        /* gfx node/widget register 1 */
+#define IIO_IGFX_W_NUM_BITS     4       /* size of widget num field */
+#define IIO_IGFX_W_NUM_MASK     ((1<<IIO_IGFX_W_NUM_BITS)-1)
+#define IIO_IGFX_W_NUM_SHIFT    0
+#define IIO_IGFX_N_NUM_BITS     9       /* size of node num field */
+#define IIO_IGFX_N_NUM_MASK     ((1<<IIO_IGFX_N_NUM_BITS)-1)
+#define IIO_IGFX_N_NUM_SHIFT    4
+#define IIO_IGFX_P_NUM_BITS     1       /* size of processor num field */
+#define IIO_IGFX_P_NUM_MASK     ((1<<IIO_IGFX_P_NUM_BITS)-1)
+#define IIO_IGFX_P_NUM_SHIFT    16
+#define IIO_IGFX_VLD_BITS       1       /* size of valid field */
+#define IIO_IGFX_VLD_MASK       ((1<<IIO_IGFX_VLD_BITS)-1)
+#define IIO_IGFX_VLD_SHIFT      20
+#define IIO_IGFX_INIT(widget, node, cpu, valid)                         (\
+        (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |     \
+        (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
+        (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) |     \
+        (((valid)  & IIO_IGFX_VLD_MASK)   << IIO_IGFX_VLD_SHIFT)         )
+
+/* Scratch registers (not all bits available) */
+#define IIO_SCRATCH_REG0        0x400150
+#define IIO_SCRATCH_REG1        0x400158
+#define IIO_SCRATCH_MASK        0x0000000f00f11fff
+
+#define IIO_SCRATCH_BIT0_0      0x0000000800000000
+#define IIO_SCRATCH_BIT0_1      0x0000000400000000
+#define IIO_SCRATCH_BIT0_2      0x0000000200000000
+#define IIO_SCRATCH_BIT0_3      0x0000000100000000
+#define IIO_SCRATCH_BIT0_4      0x0000000000800000
+#define IIO_SCRATCH_BIT0_5      0x0000000000400000
+#define IIO_SCRATCH_BIT0_6      0x0000000000200000
+#define IIO_SCRATCH_BIT0_7      0x0000000000100000
+#define IIO_SCRATCH_BIT0_8      0x0000000000010000
+#define IIO_SCRATCH_BIT0_9      0x0000000000001000
+#define IIO_SCRATCH_BIT0_R      0x0000000000000fff
+
+/* IO Translation Table Entries */
+#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
+                                        /* Hw manuals number them 1..7! */
+
+/*
+ * As a permanent workaround for a bug in the PI side of the hub, we've
+ * redefined big window 7 as small window 0.
+ */
+#define HUB_NUM_BIG_WINDOW      IIO_NUM_ITTES - 1
+
+/*
+ * Use the top big window as a surrogate for the first small window
+ */
+#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
+
+#define ILCSR_WARM_RESET        0x100
+/*
+ * The IO LLP control status register and widget control register
+ */
+#ifndef __ASSEMBLY__
+
+typedef union hubii_wid_u {
+        u64     wid_reg_value;
+        struct {
+                u64     wid_rsvd:       32,     /* unused */
+                        wid_rev_num:     4,     /* revision number */
+                        wid_part_num:   16,     /* the widget type: hub=c101 */
+                        wid_mfg_num:    11,     /* Manufacturer id (IBM) */
+                        wid_rsvd1:       1;     /* Reserved */
+        } wid_fields_s;
+} hubii_wid_t;
+
+
+typedef union hubii_wcr_u {
+        u64     wcr_reg_value;
+        struct {
+                u64     wcr_rsvd:       41,     /* unused */
+                        wcr_e_thresh:    5,     /* elasticity threshold */
+                        wcr_dir_con:     1,     /* widget direct connect */
+                        wcr_f_bad_pkt:   1,     /* Force bad llp pkt enable */
+                        wcr_xbar_crd:    3,     /* LLP crossbar credit */
+                        wcr_rsvd1:       8,     /* Reserved */
+                        wcr_tag_mode:    1,     /* Tag mode */
+                        wcr_widget_id:   4;     /* LLP crossbar credit */
+        } wcr_fields_s;
+} hubii_wcr_t;
+
+#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
+
+typedef union hubii_wstat_u {
+        u64      reg_value;
+        struct {
+                u64     rsvd1:          31,
+                        crazy:           1,     /* Crazy bit            */
+                        rsvd2:           8,
+                        llp_tx_cnt:      8,     /* LLP Xmit retry counter */
+                        rsvd3:           6,
+                        tx_max_rtry:     1,     /* LLP Retry Timeout Signal */
+                        rsvd4:           2,
+                        xt_tail_to:      1,     /* Xtalk Tail Timeout   */
+                        xt_crd_to:       1,     /* Xtalk Credit Timeout */
+                        pending:         4;     /* Pending Requests     */
+        } wstat_fields_s;
+} hubii_wstat_t;
+
+
+typedef union hubii_ilcsr_u {
+        u64     icsr_reg_value;
+        struct {
+                u64     icsr_rsvd:      22,     /* unused */
+                        icsr_max_burst: 10,     /* max burst */
+                        icsr_rsvd4:      6,     /* reserved */
+                        icsr_max_retry: 10,     /* max retry */
+                        icsr_rsvd3:      2,     /* reserved */
+                        icsr_lnk_stat:   2,     /* link status */
+                        icsr_bm8:        1,     /* Bit mode 8 */
+                        icsr_llp_en:     1,     /* LLP enable bit */
+                        icsr_rsvd2:      1,     /* reserver */
+                        icsr_wrm_reset:  1,     /* Warm reset bit */
+                        icsr_rsvd1:      2,     /* Data ready offset */
+                        icsr_null_to:    6;     /* Null timeout   */
+
+        } icsr_fields_s;
+} hubii_ilcsr_t;
+
+
+typedef union hubii_iowa_u {
+        u64     iowa_reg_value;
+        struct {
+                u64     iowa_rsvd:      48,     /* unused */
+                        iowa_wxoac:      8,     /* xtalk widget access bits */
+                        iowa_rsvd1:      7,     /* xtalk widget access bits */
+                        iowa_w0oac:      1;     /* xtalk widget access bits */
+        } iowa_fields_s;
+} hubii_iowa_t;
+
+typedef union hubii_iiwa_u {
+        u64     iiwa_reg_value;
+        struct {
+                u64     iiwa_rsvd:      48,     /* unused */
+                        iiwa_wxiac:      8,     /* hub wid access bits */
+                        iiwa_rsvd1:      7,     /* reserved */
+                        iiwa_w0iac:      1;     /* hub wid0 access */
+        } iiwa_fields_s;
+} hubii_iiwa_t;
+
+typedef union   hubii_illr_u {
+        u64     illr_reg_value;
+        struct {
+                u64     illr_rsvd:      32,     /* unused */
+                        illr_cb_cnt:    16,     /* checkbit error count */
+                        illr_sn_cnt:    16;     /* sequence number count */
+        } illr_fields_s;
+} hubii_illr_t;
+
+/* The structures below are defined to extract and modify the ii
+performance registers */
+
+/* io_perf_sel allows the caller to specify what tests will be
+   performed */
+typedef union io_perf_sel {
+        u64 perf_sel_reg;
+        struct {
+                u64     perf_rsvd  : 48,
+                        perf_icct  :  8,
+                        perf_ippr1 :  4,
+                        perf_ippr0 :  4;
+        } perf_sel_bits;
+} io_perf_sel_t;
+
+/* io_perf_cnt is to extract the count from the hub registers. Due to
+   hardware problems there is only one counter, not two. */
+
+typedef union io_perf_cnt {
+        u64     perf_cnt;
+        struct {
+                u64     perf_rsvd1 : 32,
+                                perf_rsvd2 : 12,
+                                perf_cnt   : 20;
+        } perf_cnt_bits;
+} io_perf_cnt_t;
+
+#endif /* !__ASSEMBLY__ */
+
+
+#define LNK_STAT_WORKING        0x2
+
+#define IIO_LLP_CB_MAX  0xffff
+#define IIO_LLP_SN_MAX  0xffff
+
+/* IO PRB Entries */
+#define IIO_NUM_IPRBS   (9)
+#define IIO_IOPRB_0     0x400198        /* PRB entry 0 */
+#define IIO_IOPRB_8     0x4001a0        /* PRB entry 8 */
+#define IIO_IOPRB_9     0x4001a8        /* PRB entry 9 */
+#define IIO_IOPRB_A     0x4001b0        /* PRB entry a */
+#define IIO_IOPRB_B     0x4001b8        /* PRB entry b */
+#define IIO_IOPRB_C     0x4001c0        /* PRB entry c */
+#define IIO_IOPRB_D     0x4001c8        /* PRB entry d */
+#define IIO_IOPRB_E     0x4001d0        /* PRB entry e */
+#define IIO_IOPRB_F     0x4001d8        /* PRB entry f */
+
+
+#define IIO_IXCC        0x4001e0        /* Crosstalk credit count timeout */
+#define IIO_IXTCC       IIO_IXCC
+#define IIO_IMEM        0x4001e8        /* Miscellaneous Enable Mask */
+#define IIO_IXTT        0x4001f0        /* Crosstalk tail timeout */
+#define IIO_IECLR       0x4001f8        /* IO error clear */
+#define IIO_IBCN        0x400200        /* IO BTE CRB count */
+
+/*
+ * IIO_IMEM Register fields.
+ */
+#define IIO_IMEM_W0ESD  0x1             /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD  (1 << 4)        /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD  (1 << 8)        /* BTE 1 Shut down due to error */
+
+/* PIO Read address Table Entries */
+#define IIO_IPCA        0x400300        /* PRB Counter adjust */
+#define IIO_NUM_PRTES   8               /* Total number of PRB table entries */
+#define IIO_PRTE_0      0x400308        /* PIO Read address table entry 0 */
+#define IIO_PRTE(_x)    (IIO_PRTE_0 + (8 * (_x)))
+#define IIO_WIDPRTE(x)  IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_IPDR        0x400388        /* PIO table entry deallocation */
+#define IIO_ICDR        0x400390        /* CRB Entry Deallocation */
+#define IIO_IFDR        0x400398        /* IOQ FIFO Depth */
+#define IIO_IIAP        0x4003a0        /* IIQ Arbitration Parameters */
+#define IIO_IMMR        IIO_IIAP
+#define IIO_ICMR        0x4003a8        /* CRB Managment Register */
+#define IIO_ICCR        0x4003b0        /* CRB Control Register */
+#define IIO_ICTO        0x4003b8        /* CRB Time Out Register */
+#define IIO_ICTP        0x4003c0        /* CRB Time Out Prescalar */
+
+
+/*
+ * ICMR register fields
+ */
+#define IIO_ICMR_PC_VLD_SHFT    36
+#define IIO_ICMR_PC_VLD_MASK    (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
+
+#define IIO_ICMR_CRB_VLD_SHFT   20
+#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+
+#define IIO_ICMR_FC_CNT_SHFT    16
+#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
+
+#define IIO_ICMR_C_CNT_SHFT     4
+#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
+
+#define IIO_ICMR_P_CNT_SHFT     0
+#define IIO_ICMR_P_CNT_MASK     (0xf << IIO_ICMR_P_CNT_SHFT)
+
+#define IIO_ICMR_PRECISE        (1UL << 52)
+#define IIO_ICMR_CLR_RPPD       (1UL << 13)
+#define IIO_ICMR_CLR_RQPD       (1UL << 12)
+
+/*
+ * IIO PIO Deallocation register field masks : (IIO_IPDR)
+ */
+#define IIO_IPDR_PND    (1 << 4)
+
+/*
+ * IIO CRB deallocation register field masks: (IIO_ICDR)
+ */
+#define IIO_ICDR_PND    (1 << 4)
+
+/*
+ * IIO CRB control register Fields: IIO_ICCR
+ */
+#define IIO_ICCR_PENDING        (0x10000)
+#define IIO_ICCR_CMD_MASK       (0xFF)
+#define IIO_ICCR_CMD_SHFT       (7)
+#define IIO_ICCR_CMD_NOP        (0x0)   /* No Op */
+#define IIO_ICCR_CMD_WAKE       (0x100) /* Reactivate CRB entry and process */
+#define IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
+#define IIO_ICCR_CMD_EJECT      (0x400) /* Contents of entry written to memory
+                                         * via a WB
+                                         */
+#define IIO_ICCR_CMD_FLUSH      (0x800)
+
+/*
+ * CRB manipulation macros
+ *      The CRB macros are slightly complicated, since there are up to
+ *      four registers associated with each CRB entry.
+ */
+#define IIO_NUM_CRBS            15      /* Number of CRBs */
+#define IIO_NUM_NORMAL_CRBS     12      /* Number of regular CRB entries */
+#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_ICRB_OFFSET         8
+#define IIO_ICRB_0              0x400400
+/* XXX - This is now tuneable:
+        #define IIO_FIRST_PC_ENTRY 12
+ */
+
+#define IIO_ICRB_A(_x)  (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
+#define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
+#define IIO_ICRB_C(_x)  (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
+#define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
+
+/* XXX - IBUE register coming for Hub 2 */
+
+/*
+ *
+ * CRB Register description.
+ *
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ *
+ * Many of the fields in CRB are status bits used by hardware
+ * for implementation of the protocol. It's very dangerous to
+ * mess around with the CRB registers.
+ *
+ * It's OK to read the CRB registers and try to make sense out of the
+ * fields in CRB.
+ *
+ * Updating CRB requires all activities in Hub IIO to be quiesced.
+ * otherwise, a write to CRB could corrupt other CRB entries.
+ * CRBs are here only as a back door peek to hub IIO's status.
+ * Quiescing implies  no dmas no PIOs
+ * either directly from the cpu or from sn0net.
+ * this is not something that can be done easily. So, AVOID updating
+ * CRBs.
+ */
+
+/*
+ * Fields in CRB Register A
+ */
+#ifndef __ASSEMBLY__
+typedef union icrba_u {
+        u64     reg_value;
+        struct {
+                u64     resvd:  6,
+                        stall_bte0: 1,  /* Stall BTE 0 */
+                        stall_bte1: 1,  /* Stall BTE 1 */
+                        error:  1,      /* CRB has an error     */
+                        ecode:  3,      /* Error Code           */
+                        lnetuce: 1,     /* SN0net Uncorrectable error */
+                        mark:   1,      /* CRB Has been marked  */
+                        xerr:   1,      /* Error bit set in xtalk header */
+                        sidn:   4,      /* SIDN field from xtalk        */
+                        tnum:   5,      /* TNUM field in xtalk          */
+                        addr:   38,     /* Address of request   */
+                        valid:  1,      /* Valid status         */
+                        iow:    1;      /* IO Write operation   */
+        } icrba_fields_s;
+} icrba_t;
+
+/* This is an alternate typedef for the HUB1 CRB A in order to allow
+   runtime selection of the format based on the REV_ID field of the
+   NI_STATUS_REV_ID register. */
+typedef union h1_icrba_u {
+        u64     reg_value;
+
+        struct {
+                u64     resvd:  6,
+                        unused: 1,      /* Unused but RW!!      */
+                        error:  1,      /* CRB has an error     */
+                        ecode:  4,      /* Error Code           */
+                        lnetuce: 1,     /* SN0net Uncorrectable error */
+                        mark:   1,      /* CRB Has been marked  */
+                        xerr:   1,      /* Error bit set in xtalk header */
+                        sidn:   4,      /* SIDN field from xtalk        */
+                        tnum:   5,      /* TNUM field in xtalk          */
+                        addr:   38,     /* Address of request   */
+                        valid:  1,      /* Valid status         */
+                        iow:    1;      /* IO Write operation   */
+        } h1_icrba_fields_s;
+} h1_icrba_t;
+
+/* XXX - Is this still right?  Check the spec. */
+#define ICRBN_A_CERR_SHFT       54
+#define ICRBN_A_ERR_MASK        0x3ff
+
+#if 0   /* Disabled, this causes namespace polution and break allmodconfig */
+/*
+ * Easy access macros.
+ */
+#define a_error         icrba_fields_s.error
+#define a_ecode         icrba_fields_s.ecode
+#define a_lnetuce       icrba_fields_s.lnetuce
+#define a_mark          icrba_fields_s.mark
+#define a_xerr          icrba_fields_s.xerr
+#define a_sidn          icrba_fields_s.sidn
+#define a_tnum          icrba_fields_s.tnum
+#define a_addr          icrba_fields_s.addr
+#define a_valid         icrba_fields_s.valid
+#define a_iow           icrba_fields_s.iow
+#endif
+
+#endif /* !__ASSEMBLY__ */
+
+#define IIO_ICRB_ADDR_SHFT      2       /* Shift to get proper address */
+
+/*
+ * values for "ecode" field
+ */
+#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+                                         * e.g. WINV to a Read only line.
+                                         */
+#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
+#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
+#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+
+
+
+/*
+ * Fields in CRB Register B
+ */
+#ifndef __ASSEMBLY__
+typedef union icrbb_u {
+        u64     reg_value;
+        struct {
+            u64 rsvd1:  5,
+                btenum: 1,      /* BTE to which entry belongs to */
+                cohtrans: 1,    /* Coherent transaction */
+                xtsize: 2,      /* Xtalk operation size
+                                 * 0: Double Word
+                                 * 1: 32 Bytes.
+                                 * 2: 128 Bytes,
+                                 * 3: Reserved.
+                                 */
+                srcnode: 9,     /* Source Node ID               */
+                srcinit: 2,     /* Source Initiator:
+                                 * See below for field values.
+                                 */
+                useold: 1,      /* Use OLD command for processing */
+                imsgtype: 2,    /* Incoming message type
+                                 * see below for field values
+                                 */
+                imsg:   8,      /* Incoming message     */
+                initator: 3,    /* Initiator of original request
+                                 * See below for field values.
+                                 */
+                reqtype: 5,     /* Identifies type of request
+                                 * See below for field values.
+                                 */
+                rsvd2:  7,
+                ackcnt: 11,     /* Invalidate ack count */
+                resp:   1,      /* data response  given to processor */
+                ack:    1,      /* indicates data ack received  */
+                hold:   1,      /* entry is gathering inval acks */
+                wb_pend:1,      /* waiting for writeback to complete */
+                intvn:  1,      /* Intervention */
+                stall_ib: 1,    /* Stall Ibuf (from crosstalk) */
+                stall_intr: 1;  /* Stall internal interrupts */
+        } icrbb_field_s;
+} icrbb_t;
+
+/* This is an alternate typedef for the HUB1 CRB B in order to allow
+   runtime selection of the format based on the REV_ID field of the
+   NI_STATUS_REV_ID register. */
+typedef union h1_icrbb_u {
+        u64     reg_value;
+        struct {
+                u64     rsvd1:  5,
+                        btenum: 1,      /* BTE to which entry belongs to */
+                        cohtrans: 1,    /* Coherent transaction */
+                        xtsize: 2,      /* Xtalk operation size
+                                         * 0: Double Word
+                                         * 1: 32 Bytes.
+                                         * 2: 128 Bytes,
+                                         * 3: Reserved.
+                                         */
+                        srcnode: 9,     /* Source Node ID               */
+                        srcinit: 2,     /* Source Initiator:
+                                         * See below for field values.
+                                         */
+                        useold: 1,      /* Use OLD command for processing */
+                        imsgtype: 2,    /* Incoming message type
+                                         * see below for field values
+                                         */
+                        imsg:   8,      /* Incoming message     */
+                        initator: 3,    /* Initiator of original request
+                                         * See below for field values.
+                                         */
+                        rsvd2:  1,
+                        pcache: 1,      /* entry belongs to partial cache */
+                        reqtype: 5,     /* Identifies type of request
+                                         * See below for field values.
+                                         */
+                        stl_ib: 1,      /* stall Ibus coming from xtalk */
+                        stl_intr: 1,    /* Stall internal interrupts */
+                        stl_bte0: 1,    /* Stall BTE 0  */
+                        stl_bte1: 1,    /* Stall BTE 1  */
+                        intrvn: 1,      /* Req was target of intervention */
+                        ackcnt: 11,     /* Invalidate ack count */
+                        resp:   1,      /* data response  given to processor */
+                        ack:    1,      /* indicates data ack received  */
+                        hold:   1,      /* entry is gathering inval acks */
+                        wb_pend:1,      /* waiting for writeback to complete */
+                        sleep:  1,      /* xtalk req sleeping till IO-sync */
+                        pnd_reply: 1,   /* replies not issed due to IOQ full */
+                        pnd_req: 1;     /* reqs not issued due to IOQ full */
+        } h1_icrbb_field_s;
+} h1_icrbb_t;
+
+
+#define b_imsgtype      icrbb_field_s.imsgtype
+#define b_btenum        icrbb_field_s.btenum
+#define b_cohtrans      icrbb_field_s.cohtrans
+#define b_xtsize        icrbb_field_s.xtsize
+#define b_srcnode       icrbb_field_s.srcnode
+#define b_srcinit       icrbb_field_s.srcinit
+#define b_imsgtype      icrbb_field_s.imsgtype
+#define b_imsg          icrbb_field_s.imsg
+#define b_initiator     icrbb_field_s.initiator
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * values for field xtsize
+ */
+#define IIO_ICRB_XTSIZE_DW      0       /* Xtalk operation size is 8 bytes  */
+#define IIO_ICRB_XTSIZE_32      1       /* Xtalk operation size is 32 bytes */
+#define IIO_ICRB_XTSIZE_128     2       /* Xtalk operation size is 128 bytes */
+
+/*
+ * values for field srcinit
+ */
+#define IIO_ICRB_PROC0          0       /* Source of request is Proc 0 */
+#define IIO_ICRB_PROC1          1       /* Source of request is Proc 1 */
+#define IIO_ICRB_GB_REQ         2       /* Source is Guranteed BW request */
+#define IIO_ICRB_IO_REQ         3       /* Source is Normal IO request  */
+
+/*
+ * Values for field imsgtype
+ */
+#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
+#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
+#define IIO_ICRB_IMSGT_SN0NET   2       /* Incoming message from SN0 net */
+#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
+
+/*
+ * values for field initiator.
+ */
+#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
+#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
+#define IIO_ICRB_INIT_SN0NET    0x2     /* Message originated in SN0net */
+#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
+#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
+
+/*
+ * Values for field reqtype.
+ */
+/* XXX - Need to fix this for Hub 2 */
+#define IIO_ICRB_REQ_DWRD       0       /* Request type double word     */
+#define IIO_ICRB_REQ_QCLRD      1       /* Request is Qrtr Caceh line Rd */
+#define IIO_ICRB_REQ_BLKRD      2       /* Request is block read        */
+#define IIO_ICRB_REQ_RSHU       6       /* Request is BTE block read    */
+#define IIO_ICRB_REQ_REXU       7       /* request is BTE Excl Read     */
+#define IIO_ICRB_REQ_RDEX       8       /* Request is Read Exclusive    */
+#define IIO_ICRB_REQ_WINC       9       /* Request is Write Invalidate  */
+#define IIO_ICRB_REQ_BWINV      10      /* Request is BTE Winv          */
+#define IIO_ICRB_REQ_PIORD      11      /* Request is PIO read          */
+#define IIO_ICRB_REQ_PIOWR      12      /* Request is PIO Write         */
+#define IIO_ICRB_REQ_PRDM       13      /* Request is Fetch&Op          */
+#define IIO_ICRB_REQ_PWRM       14      /* Request is Store &Op         */
+#define IIO_ICRB_REQ_PTPWR      15      /* Request is Peer to peer      */
+#define IIO_ICRB_REQ_WB         16      /* Request is Write back        */
+#define IIO_ICRB_REQ_DEX        17      /* Retained DEX Cache line      */
+
+/*
+ * Fields in CRB Register C
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef union icrbc_s {
+        u64     reg_value;
+        struct {
+                u64     rsvd:   6,
+                        sleep:  1,
+                        pricnt: 4,      /* Priority count sent with Read req */
+                        pripsc: 4,      /* Priority Pre scalar  */
+                        bteop:  1,      /* BTE Operation        */
+                        push_be: 34,    /* Push address Byte enable
+                                         * Holds push addr, if CRB is for BTE
+                                         * If CRB belongs to Partial cache,
+                                         * this contains byte enables bits
+                                         * ([47:46] = 0)
+                                         */
+                        suppl:  11,     /* Supplemental field   */
+                        barrop: 1,      /* Barrier Op bit set in xtalk req */
+                        doresp: 1,      /* Xtalk req needs a response   */
+                        gbr:    1;      /* GBR bit set in xtalk packet  */
+        } icrbc_field_s;
+} icrbc_t;
+
+#define c_pricnt        icrbc_field_s.pricnt
+#define c_pripsc        icrbc_field_s.pripsc
+#define c_bteop         icrbc_field_s.bteop
+#define c_bteaddr       icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_benable       icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_suppl         icrbc_field_s.suppl
+#define c_barrop        icrbc_field_s.barrop
+#define c_doresp        icrbc_field_s.doresp
+#define c_gbr   icrbc_field_s.gbr
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Fields in CRB Register D
+ */
+
+#ifndef __ASSEMBLY__
+typedef union icrbd_s {
+        u64     reg_value;
+        struct {
+            u64 rsvd:   38,
+                toutvld: 1,     /* Timeout in progress for this CRB */
+                ctxtvld: 1,     /* Context field below is valid */
+                rsvd2:  1,
+                context: 15,    /* Bit vector:
+                                 * Has a bit set for each CRB entry
+                                 * which needs to be deallocated
+                                 * before this CRB entry is processed.
+                                 * Set only for barrier operations.
+                                 */
+                timeout: 8;     /* Timeout Upper 8 bits */
+        } icrbd_field_s;
+} icrbd_t;
+
+#define icrbd_toutvld   icrbd_field_s.toutvld
+#define icrbd_ctxtvld   icrbd_field_s.ctxtvld
+#define icrbd_context   icrbd_field_s.context
+
+
+typedef union hubii_ifdr_u {
+        u64     hi_ifdr_value;
+        struct {
+                u64     ifdr_rsvd:      49,
+                        ifdr_maxrp:      7,
+                        ifdr_rsvd1:      1,
+                        ifdr_maxrq:      7;
+        } hi_ifdr_fields;
+} hubii_ifdr_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Hardware designed names for the BTE control registers.
+ */
+#define IIO_IBLS_0      0x410000        /* BTE length/status 0 */
+#define IIO_IBSA_0      0x410008        /* BTE source address 0 */
+#define IIO_IBDA_0      0x410010        /* BTE destination address 0 */
+#define IIO_IBCT_0      0x410018        /* BTE control/terminate 0 */
+#define IIO_IBNA_0      0x410020        /* BTE notification address 0 */
+#define IIO_IBNR_0      IIO_IBNA_0
+#define IIO_IBIA_0      0x410028        /* BTE interrupt address 0 */
+
+#define IIO_IBLS_1      0x420000        /* BTE length/status 1 */
+#define IIO_IBSA_1      0x420008        /* BTE source address 1 */
+#define IIO_IBDA_1      0x420010        /* BTE destination address 1 */
+#define IIO_IBCT_1      0x420018        /* BTE control/terminate 1 */
+#define IIO_IBNA_1      0x420020        /* BTE notification address 1 */
+#define IIO_IBNR_1      IIO_IBNA_1
+#define IIO_IBIA_1      0x420028        /* BTE interrupt address 1 */
+
+/*
+ * More miscellaneous registers
+ */
+#define IIO_IPCR        0x430000        /* Performance Control */
+#define IIO_IPPR        0x430008        /* Performance Profiling */
+
+/*
+ * IO Error Clear register bit field definitions
+ */
+#define IECLR_BTE1              (1 << 18)  /* clear bte error 1 ??? */
+#define IECLR_BTE0              (1 << 17)  /* clear bte error 0 ??? */
+#define IECLR_CRAZY             (1 << 16)  /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F             (1 << 15)  /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E             (1 << 14)  /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D             (1 << 13)  /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C             (1 << 12)  /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B             (1 << 11)  /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A             (1 << 10)  /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9             (1 << 9)   /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8             (1 << 8)   /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0             (1 << 0)   /* clear err bit in PRB_0 reg */
+
+/*
+ * IO PIO Read Table Entry format
+ */
+
+#ifndef __ASSEMBLY__
+
+typedef union iprte_a {
+        u64     entry;
+        struct {
+            u64 rsvd1     : 7,  /* Reserved field               */
+                valid     : 1,  /* Maps to a timeout entry      */
+                rsvd2     : 1,
+                srcnode   : 9,  /* Node which did this PIO      */
+                initiator : 2,  /* If T5A or T5B or IO          */
+                rsvd3     : 3,
+                addr      : 38, /* Physical address of PIO      */
+                rsvd4     : 3;
+        } iprte_fields;
+} iprte_a_t;
+
+#define iprte_valid     iprte_fields.valid
+#define iprte_timeout   iprte_fields.timeout
+#define iprte_srcnode   iprte_fields.srcnode
+#define iprte_init      iprte_fields.initiator
+#define iprte_addr      iprte_fields.addr
+
+#endif /* !__ASSEMBLY__ */
+
+#define IPRTE_ADDRSHFT  3
+
+/*
+ * Hub IIO PRB Register format.
+ */
+
+#ifndef __ASSEMBLY__
+/*
+ * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
+ * "Status" fields, and should only be used in case of clean up after errors.
+ */
+
+typedef union iprb_u {
+        u64     reg_value;
+        struct {
+            u64 rsvd1:  15,
+                error:  1,      /* Widget rcvd wr resp pkt w/ error */
+                ovflow: 5,      /* Over flow count. perf measurement */
+                fire_and_forget: 1, /* Launch Write without response */
+                mode:   2,      /* Widget operation Mode        */
+                rsvd2:  2,
+                bnakctr: 14,
+                rsvd3:  2,
+                anakctr: 14,
+                xtalkctr: 8;
+        } iprb_fields_s;
+} iprb_t;
+
+#define iprb_regval     reg_value
+
+#define iprb_error      iprb_fields_s.error
+#define iprb_ovflow     iprb_fields_s.ovflow
+#define iprb_ff         iprb_fields_s.fire_and_forget
+#define iprb_mode       iprb_fields_s.mode
+#define iprb_bnakctr    iprb_fields_s.bnakctr
+#define iprb_anakctr    iprb_fields_s.anakctr
+#define iprb_xtalkctr   iprb_fields_s.xtalkctr
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * values for mode field in iprb_t.
+ * For details of the meanings of NAK and Accept, refer the PIO flow
+ * document
+ */
+#define IPRB_MODE_NORMAL        (0)
+#define IPRB_MODE_COLLECT_A     (1)     /* PRB in collect A mode */
+#define IPRB_MODE_SERVICE_A     (2)     /* NAK B and Accept A */
+#define IPRB_MODE_SERVICE_B     (3)     /* NAK A and Accept B */
+
+/*
+ * IO CRB entry C_A to E_A : Partial (cache) CRBS
+ */
+#ifndef __ASSEMBLY__
+typedef union icrbp_a {
+        u64   ip_reg;       /* the entire register value        */
+        struct {
+             u64 error: 1,  /*    63, error occurred            */
+                ln_uce: 1,  /*    62: uncorrectable memory      */
+                ln_ae:  1,  /*    61: protection violation      */
+                ln_werr:1,  /*    60: write access error        */
+                ln_aerr:1,  /*    59: sn0net: Address error     */
+                ln_perr:1,  /*    58: sn0net: poison error      */
+                timeout:1,  /*    57: CRB timed out             */
+                l_bdpkt:1,  /*    56: truncated pkt on sn0net   */
+                c_bdpkt:1,  /*    55: truncated pkt on xtalk    */
+                c_err:  1,  /*    54: incoming xtalk req, err set*/
+                rsvd1: 12,  /* 53-42: reserved                  */
+                valid:  1,  /*    41: Valid status              */
+                sidn:   4,  /* 40-37: SIDN field of xtalk rqst  */
+                tnum:   5,  /* 36-32: TNUM of xtalk request     */
+                bo:     1,  /*    31: barrier op set in xtalk rqst*/
+                resprqd:1,  /*    30: xtalk rqst requires response*/
+                gbr:    1,  /*    29: gbr bit set in xtalk rqst */
+                size:   2,  /* 28-27: size of xtalk request     */
+                excl:   4,  /* 26-23: exclusive bit(s)          */
+                stall:  3,  /* 22-20: stall (xtalk, bte 0/1)    */
+                intvn:  1,  /*    19: rqst target of intervention*/
+                resp:   1,  /*    18: Data response given to t5 */
+                ack:    1,  /*    17: Data ack received.        */
+                hold:   1,  /*    16: crb gathering invalidate acks*/
+                wb:     1,  /*    15: writeback pending.        */
+                ack_cnt:11, /* 14-04: counter of invalidate acks*/
+                tscaler:4;  /* 03-00: Timeout prescaler         */
+        } ip_fmt;
+} icrbp_a_t;
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * A couple of defines to go with the above structure.
+ */
+#define ICRBP_A_CERR_SHFT       54
+#define ICRBP_A_ERR_MASK        0x3ff
+
+#ifndef __ASSEMBLY__
+typedef union hubii_idsr {
+        u64 iin_reg;
+        struct {
+                u64 rsvd1 : 35,
+                    isent : 1,
+                    rsvd2 : 3,
+                    ienable: 1,
+                    rsvd  : 7,
+                    node  : 9,
+                    rsvd4 : 1,
+                    level : 7;
+        } iin_fmt;
+} hubii_idsr_t;
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * IO BTE Length/Status (IIO_IBLS) register bit field definitions
+ */
+#define IBLS_BUSY               (0x1 << 20)
+#define IBLS_ERROR_SHFT         16
+#define IBLS_ERROR              (0x1 << IBLS_ERROR_SHFT)
+#define IBLS_LENGTH_MASK        0xffff
+
+/*
+ * IO BTE Control/Terminate register (IBCT) register bit field definitions
+ */
+#define IBCT_POISON             (0x1 << 8)
+#define IBCT_NOTIFY             (0x1 << 4)
+#define IBCT_ZFIL_MODE          (0x1 << 0)
+
+/*
+ * IO BTE Interrupt Address Register (IBIA) register bit field definitions
+ */
+#define IBIA_LEVEL_SHFT         16
+#define IBIA_LEVEL_MASK         (0x7f << IBIA_LEVEL_SHFT)
+#define IBIA_NODE_ID_SHFT       0
+#define IBIA_NODE_ID_MASK       (0x1ff)
+
+/*
+ * Miscellaneous hub constants
+ */
+
+/* Number of widgets supported by hub */
+#define HUB_NUM_WIDGET          9
+#define HUB_WIDGET_ID_MIN       0x8
+#define HUB_WIDGET_ID_MAX       0xf
+
+#define HUB_WIDGET_PART_NUM     0xc101
+#define MAX_HUBS_PER_XBOW       2
+
+/*
+ * Get a hub's widget id from widget control register
+ */
+#define IIO_WCR_WID_GET(nasid)  (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
+#define IIO_WST_ERROR_MASK      (UINT64_CAST 1 << 32) /* Widget status error */
+
+/*
+ * Number of credits Hub widget has while sending req/response to
+ * xbow.
+ * Value of 3 is required by Xbow 1.1
+ * We may be able to increase this to 4 with Xbow 1.2.
+ */
+#define       HUBII_XBOW_CREDIT       3
+#define       HUBII_XBOW_REV2_CREDIT  4
+
+#endif /* _ASM_SGI_SN_SN0_HUBIO_H */
diff --git a/include/asm-mips/sn/sn0/hubmd.h b/include/asm-mips/sn/sn0/hubmd.h
new file mode 100644
index 000000000000..a66def4e0ba0
--- /dev/null
+++ b/include/asm-mips/sn/sn0/hubmd.h
@@ -0,0 +1,790 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubmd.h>, revision 1.59.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUBMD_H
+#define _ASM_SN_SN0_HUBMD_H
+
+#include <linux/config.h>
+
+/*
+ * Hub Memory/Directory interface registers
+ */
+#define CACHE_SLINE_SIZE        128     /* Secondary cache line size on SN0 */
+
+#define MAX_REGIONS             64
+
+/* Hardware page size and shift */
+
+#define MD_PAGE_SIZE            4096     /* Page size in bytes              */
+#define MD_PAGE_NUM_SHFT        12       /* Address to page number shift    */
+
+/* Register offsets from LOCAL_HUB or REMOTE_HUB */
+
+#define MD_BASE                 0x200000
+#define MD_BASE_PERF            0x210000
+#define MD_BASE_JUNK            0x220000
+
+#define MD_IO_PROTECT           0x200000 /* MD and core register protection */
+#define MD_IO_PROT_OVRRD        0x200008 /* Clear my bit in MD_IO_PROTECT   */
+#define MD_HSPEC_PROTECT        0x200010 /* BDDIR, LBOOT, RBOOT protection  */
+#define MD_MEMORY_CONFIG        0x200018 /* Memory/Directory DIMM control   */
+#define MD_REFRESH_CONTROL      0x200020 /* Memory/Directory refresh ctrl   */
+#define MD_FANDOP_CAC_STAT      0x200028 /* Fetch-and-op cache status       */
+#define MD_MIG_DIFF_THRESH      0x200030 /* Page migr. count diff thresh.   */
+#define MD_MIG_VALUE_THRESH     0x200038 /* Page migr. count abs. thresh.   */
+#define MD_MIG_CANDIDATE        0x200040 /* Latest page migration candidate */
+#define MD_MIG_CANDIDATE_CLR    0x200048 /* Clear page migration candidate  */
+#define MD_DIR_ERROR            0x200050 /* Directory DIMM error            */
+#define MD_DIR_ERROR_CLR        0x200058 /* Directory DIMM error clear      */
+#define MD_PROTOCOL_ERROR       0x200060 /* Directory protocol error        */
+#define MD_PROTOCOL_ERROR_CLR   0x200068 /* Directory protocol error clear  */
+#define MD_MEM_ERROR            0x200070 /* Memory DIMM error               */
+#define MD_MEM_ERROR_CLR        0x200078 /* Memory DIMM error clear         */
+#define MD_MISC_ERROR           0x200080 /* Miscellaneous MD error          */
+#define MD_MISC_ERROR_CLR       0x200088 /* Miscellaneous MD error clear    */
+#define MD_MEM_DIMM_INIT        0x200090 /* Memory DIMM mode initization.   */
+#define MD_DIR_DIMM_INIT        0x200098 /* Directory DIMM mode init.       */
+#define MD_MOQ_SIZE             0x2000a0 /* MD outgoing queue size          */
+#define MD_MLAN_CTL             0x2000a8 /* NIC (Microlan) control register */
+
+#define MD_PERF_SEL             0x210000 /* Select perf monitor events      */
+#define MD_PERF_CNT0            0x210010 /* Performance counter 0           */
+#define MD_PERF_CNT1            0x210018 /* Performance counter 1           */
+#define MD_PERF_CNT2            0x210020 /* Performance counter 2           */
+#define MD_PERF_CNT3            0x210028 /* Performance counter 3           */
+#define MD_PERF_CNT4            0x210030 /* Performance counter 4           */
+#define MD_PERF_CNT5            0x210038 /* Performance counter 5           */
+
+#define MD_UREG0_0              0x220000 /* uController/UART 0 register     */
+#define MD_UREG0_1              0x220008 /* uController/UART 0 register     */
+#define MD_UREG0_2              0x220010 /* uController/UART 0 register     */
+#define MD_UREG0_3              0x220018 /* uController/UART 0 register     */
+#define MD_UREG0_4              0x220020 /* uController/UART 0 register     */
+#define MD_UREG0_5              0x220028 /* uController/UART 0 register     */
+#define MD_UREG0_6              0x220030 /* uController/UART 0 register     */
+#define MD_UREG0_7              0x220038 /* uController/UART 0 register     */
+
+#define MD_SLOTID_USTAT         0x220048 /* Hub slot ID & UART/uCtlr status */
+#define MD_LED0                 0x220050 /* Eight-bit LED for CPU A         */
+#define MD_LED1                 0x220058 /* Eight-bit LED for CPU B         */
+
+#define MD_UREG1_0              0x220080 /* uController/UART 1 register     */
+#define MD_UREG1_1              0x220088 /* uController/UART 1 register     */
+#define MD_UREG1_2              0x220090 /* uController/UART 1 register     */
+#define MD_UREG1_3              0x220098 /* uController/UART 1 register     */
+#define MD_UREG1_4              0x2200a0 /* uController/UART 1 register     */
+#define MD_UREG1_5              0x2200a8 /* uController/UART 1 register     */
+#define MD_UREG1_6              0x2200b0 /* uController/UART 1 register     */
+#define MD_UREG1_7              0x2200b8 /* uController/UART 1 register     */
+#define MD_UREG1_8              0x2200c0 /* uController/UART 1 register     */
+#define MD_UREG1_9              0x2200c8 /* uController/UART 1 register     */
+#define MD_UREG1_10             0x2200d0 /* uController/UART 1 register     */
+#define MD_UREG1_11             0x2200d8 /* uController/UART 1 register     */
+#define MD_UREG1_12             0x2200e0 /* uController/UART 1 register     */
+#define MD_UREG1_13             0x2200e8 /* uController/UART 1 register     */
+#define MD_UREG1_14             0x2200f0 /* uController/UART 1 register     */
+#define MD_UREG1_15             0x2200f8 /* uController/UART 1 register     */
+
+#ifdef CONFIG_SGI_SN0_N_MODE
+#define MD_MEM_BANKS            4        /* 4 banks of memory max in N mode */
+#else
+#define MD_MEM_BANKS            8        /* 8 banks of memory max in M mode */
+#endif
+
+/*
+ * MD_MEMORY_CONFIG fields
+ *
+ *   MD_SIZE_xxx are useful for representing the size of a SIMM or bank
+ *   (SIMM pair).  They correspond to the values needed for the bit
+ *   triplets (MMC_BANK_MASK) in the MD_MEMORY_CONFIG register for bank size.
+ *   Bits not used by the MD are used by software.
+ */
+
+#define MD_SIZE_EMPTY           0       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_8MB             1
+#define MD_SIZE_16MB            2
+#define MD_SIZE_32MB            3       /* Broken in Hub 1                  */
+#define MD_SIZE_64MB            4       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_128MB           5       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_256MB           6
+#define MD_SIZE_512MB           7       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_1GB             8
+#define MD_SIZE_2GB             9
+#define MD_SIZE_4GB             10
+
+#define MD_SIZE_BYTES(size)     ((size) == 0 ? 0 : 0x400000L << (size))
+#define MD_SIZE_MBYTES(size)    ((size) == 0 ? 0 :   4       << (size))
+
+#define MMC_FPROM_CYC_SHFT      49      /* Have to use UINT64_CAST, instead */
+#define MMC_FPROM_CYC_MASK      (UINT64_CAST 31 << 49)  /* of 'L' suffix,   */
+#define MMC_FPROM_WR_SHFT       44                      /* for assembler    */
+#define MMC_FPROM_WR_MASK       (UINT64_CAST 31 << 44)
+#define MMC_UCTLR_CYC_SHFT      39
+#define MMC_UCTLR_CYC_MASK      (UINT64_CAST 31 << 39)
+#define MMC_UCTLR_WR_SHFT       34
+#define MMC_UCTLR_WR_MASK       (UINT64_CAST 31 << 34)
+#define MMC_DIMM0_SEL_SHFT      32
+#define MMC_DIMM0_SEL_MASK      (UINT64_CAST 3 << 32)
+#define MMC_IO_PROT_EN_SHFT     31
+#define MMC_IO_PROT_EN_MASK     (UINT64_CAST 1 << 31)
+#define MMC_IO_PROT             (UINT64_CAST 1 << 31)
+#define MMC_ARB_MLSS_SHFT       30
+#define MMC_ARB_MLSS_MASK       (UINT64_CAST 1 << 30)
+#define MMC_ARB_MLSS            (UINT64_CAST 1 << 30)
+#define MMC_IGNORE_ECC_SHFT     29
+#define MMC_IGNORE_ECC_MASK     (UINT64_CAST 1 << 29)
+#define MMC_IGNORE_ECC          (UINT64_CAST 1 << 29)
+#define MMC_DIR_PREMIUM_SHFT    28
+#define MMC_DIR_PREMIUM_MASK    (UINT64_CAST 1 << 28)
+#define MMC_DIR_PREMIUM         (UINT64_CAST 1 << 28)
+#define MMC_REPLY_GUAR_SHFT     24
+#define MMC_REPLY_GUAR_MASK     (UINT64_CAST 15 << 24)
+#define MMC_BANK_SHFT(_b)       ((_b) * 3)
+#define MMC_BANK_MASK(_b)       (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
+#define MMC_BANK_ALL_MASK       0xffffff
+#define MMC_RESET_DEFAULTS      (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
+                                 UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
+                                 UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
+                                 UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
+                                 MMC_IGNORE_ECC | MMC_DIR_PREMIUM | \
+                                 UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
+                                 MMC_BANK_ALL_MASK)
+
+/* MD_REFRESH_CONTROL fields */
+
+#define MRC_ENABLE_SHFT         63
+#define MRC_ENABLE_MASK         (UINT64_CAST 1 << 63)
+#define MRC_ENABLE              (UINT64_CAST 1 << 63)
+#define MRC_COUNTER_SHFT        12
+#define MRC_COUNTER_MASK        (UINT64_CAST 0xfff << 12)
+#define MRC_CNT_THRESH_MASK     0xfff
+#define MRC_RESET_DEFAULTS      (UINT64_CAST 0x400)
+
+/* MD_MEM_DIMM_INIT and MD_DIR_DIMM_INIT fields */
+
+#define MDI_SELECT_SHFT         32
+#define MDI_SELECT_MASK         (UINT64_CAST 0x0f << 32)
+#define MDI_DIMM_MODE_MASK      (UINT64_CAST 0xfff)
+
+/* MD_MOQ_SIZE fields */
+
+#define MMS_RP_SIZE_SHFT        8
+#define MMS_RP_SIZE_MASK        (UINT64_CAST 0x3f << 8)
+#define MMS_RQ_SIZE_SHFT        0
+#define MMS_RQ_SIZE_MASK        (UINT64_CAST 0x1f)
+#define MMS_RESET_DEFAULTS      (0x32 << 8 | 0x12)
+
+/* MD_FANDOP_CAC_STAT fields */
+
+#define MFC_VALID_SHFT          63
+#define MFC_VALID_MASK          (UINT64_CAST 1 << 63)
+#define MFC_VALID               (UINT64_CAST 1 << 63)
+#define MFC_ADDR_SHFT           6
+#define MFC_ADDR_MASK           (UINT64_CAST 0x3ffffff)
+
+/* MD_MLAN_CTL fields */
+
+#define MLAN_PHI1_SHFT          27
+#define MLAN_PHI1_MASK          (UINT64_CAST 0x7f << 27)
+#define MLAN_PHI0_SHFT          20
+#define MLAN_PHI0_MASK          (UINT64_CAST 0x7f << 27)
+#define MLAN_PULSE_SHFT         10
+#define MLAN_PULSE_MASK         (UINT64_CAST 0x3ff << 10)
+#define MLAN_SAMPLE_SHFT        2
+#define MLAN_SAMPLE_MASK        (UINT64_CAST 0xff << 2)
+#define MLAN_DONE_SHFT          1
+#define MLAN_DONE_MASK          2
+#define MLAN_DONE               (UINT64_CAST 0x02)
+#define MLAN_RD_DATA            (UINT64_CAST 0x01)
+#define MLAN_RESET_DEFAULTS     (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
+                                 UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
+
+/* MD_SLOTID_USTAT bit definitions */
+
+#define MSU_CORECLK_TST_SHFT    7       /* You don't wanna know             */
+#define MSU_CORECLK_TST_MASK    (UINT64_CAST 1 << 7)
+#define MSU_CORECLK_TST         (UINT64_CAST 1 << 7)
+#define MSU_CORECLK_SHFT        6       /* You don't wanna know             */
+#define MSU_CORECLK_MASK        (UINT64_CAST 1 << 6)
+#define MSU_CORECLK             (UINT64_CAST 1 << 6)
+#define MSU_NETSYNC_SHFT        5       /* You don't wanna know             */
+#define MSU_NETSYNC_MASK        (UINT64_CAST 1 << 5)
+#define MSU_NETSYNC             (UINT64_CAST 1 << 5)
+#define MSU_FPROMRDY_SHFT       4       /* Flash PROM ready bit             */
+#define MSU_FPROMRDY_MASK       (UINT64_CAST 1 << 4)
+#define MSU_FPROMRDY            (UINT64_CAST 1 << 4)
+#define MSU_I2CINTR_SHFT                3       /* I2C interrupt bit   */
+#define MSU_I2CINTR_MASK                (UINT64_CAST 1 << 3)
+#define MSU_I2CINTR             (UINT64_CAST 1 << 3)
+#define MSU_SLOTID_MASK         0xff
+#define MSU_SN0_SLOTID_SHFT     0       /* Slot ID                          */
+#define MSU_SN0_SLOTID_MASK     (UINT64_CAST 7)
+#define MSU_SN00_SLOTID_SHFT    7
+#define MSU_SN00_SLOTID_MASK    (UINT64_CAST 0x80)
+
+#define MSU_PIMM_PSC_SHFT       4
+#define MSU_PIMM_PSC_MASK       (0xf << MSU_PIMM_PSC_SHFT)
+
+/* MD_MIG_DIFF_THRESH bit definitions */
+
+#define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_DIFF_THRES_VALID_SHFT 63
+#define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
+
+/* MD_MIG_VALUE_THRESH bit definitions */
+
+#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_VALUE_THRES_VALID_SHFT 63
+#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
+
+/* MD_MIG_CANDIDATE bit definitions */
+
+#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
+#define MD_MIG_CANDIDATE_VALID_SHFT 63
+#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
+#define MD_MIG_CANDIDATE_TYPE_SHFT 30
+#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
+#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
+#define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
+#define MD_MIG_CANDIDATE_INITIATOR_SHFT 18
+#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
+#define MD_MIG_CANDIDATE_NODEID_SHFT 20
+#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
+#define MD_MIG_CANDIDATE_ADDR_SHFT 14  /* The address starts at bit 14 */
+
+/* Other MD definitions */
+
+#define MD_BANK_SHFT            29                      /* log2(512 MB)     */
+#define MD_BANK_MASK            (UINT64_CAST 7 << 29)
+#define MD_BANK_SIZE            (UINT64_CAST 1 << MD_BANK_SHFT)   /* 512 MB */
+#define MD_BANK_OFFSET(_b)      (UINT64_CAST (_b) << MD_BANK_SHFT)
+
+/*
+ * The following definitions cover the bit field definitions for the
+ * various MD registers.  For multi-bit registers, we define both
+ * a shift amount and a mask value.  By convention, if you want to
+ * isolate a field, you should mask the field and then shift it down,
+ * since this makes the masks useful without a shift.
+ */
+
+/* Directory entry states for both premium and standard SIMMs. */
+
+#define MD_DIR_SHARED           (UINT64_CAST 0x0)       /* 000 */
+#define MD_DIR_POISONED         (UINT64_CAST 0x1)       /* 001 */
+#define MD_DIR_EXCLUSIVE        (UINT64_CAST 0x2)       /* 010 */
+#define MD_DIR_BUSY_SHARED      (UINT64_CAST 0x3)       /* 011 */
+#define MD_DIR_BUSY_EXCL        (UINT64_CAST 0x4)       /* 100 */
+#define MD_DIR_WAIT             (UINT64_CAST 0x5)       /* 101 */
+#define MD_DIR_UNOWNED          (UINT64_CAST 0x7)       /* 111 */
+
+/*
+ * The MD_DIR_FORCE_ECC bit can be added directory entry write data
+ * to forcing the ECC to be written as-is instead of recalculated.
+ */
+
+#define MD_DIR_FORCE_ECC        (UINT64_CAST 1 << 63)
+
+/*
+ * Premium SIMM directory entry shifts and masks.  Each is valid only in the
+ * context(s) indicated, where A, B, and C indicate the directory entry format
+ * as shown, and low and/or high indicates which double-word of the entry.
+ *
+ * Format A:  STATE = shared, FINE = 1
+ * Format B:  STATE = shared, FINE = 0
+ * Format C:  STATE != shared (FINE must be 0)
+ */
+
+#define MD_PDIR_MASK            0xffffffffffff          /* Whole entry      */
+#define MD_PDIR_ECC_SHFT        0                       /* ABC low or high  */
+#define MD_PDIR_ECC_MASK        0x7f
+#define MD_PDIR_PRIO_SHFT       8                       /* ABC low          */
+#define MD_PDIR_PRIO_MASK       (0xf << 8)
+#define MD_PDIR_AX_SHFT         7                       /* ABC low          */
+#define MD_PDIR_AX_MASK         (1 << 7)
+#define MD_PDIR_AX              (1 << 7)
+#define MD_PDIR_FINE_SHFT       12                      /* ABC low          */
+#define MD_PDIR_FINE_MASK       (1 << 12)
+#define MD_PDIR_FINE            (1 << 12)
+#define MD_PDIR_OCT_SHFT        13                      /* A low            */
+#define MD_PDIR_OCT_MASK        (7 << 13)
+#define MD_PDIR_STATE_SHFT      13                      /* BC low           */
+#define MD_PDIR_STATE_MASK      (7 << 13)
+#define MD_PDIR_ONECNT_SHFT     16                      /* BC low           */
+#define MD_PDIR_ONECNT_MASK     (0x3f << 16)
+#define MD_PDIR_PTR_SHFT        22                      /* C low            */
+#define MD_PDIR_PTR_MASK        (UINT64_CAST 0x7ff << 22)
+#define MD_PDIR_VECMSB_SHFT     22                      /* AB low           */
+#define MD_PDIR_VECMSB_BITMASK  0x3ffffff
+#define MD_PDIR_VECMSB_BITSHFT  27
+#define MD_PDIR_VECMSB_MASK     (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
+#define MD_PDIR_CWOFF_SHFT      7                       /* C high           */
+#define MD_PDIR_CWOFF_MASK      (7 << 7)
+#define MD_PDIR_VECLSB_SHFT     10                      /* AB high          */
+#define MD_PDIR_VECLSB_BITMASK  (UINT64_CAST 0x3fffffffff)
+#define MD_PDIR_VECLSB_BITSHFT  0
+#define MD_PDIR_VECLSB_MASK     (MD_PDIR_VECLSB_BITMASK << 10)
+
+/*
+ * Directory initialization values
+ */
+
+#define MD_PDIR_INIT_LO         (MD_DIR_UNOWNED << MD_PDIR_STATE_SHFT | \
+                                 MD_PDIR_AX)
+#define MD_PDIR_INIT_HI         0
+#define MD_PDIR_INIT_PROT       (MD_PROT_RW << MD_PPROT_IO_SHFT | \
+                                 MD_PROT_RW << MD_PPROT_SHFT)
+
+/*
+ * Standard SIMM directory entry shifts and masks.  Each is valid only in the
+ * context(s) indicated, where A and C indicate the directory entry format
+ * as shown, and low and/or high indicates which double-word of the entry.
+ *
+ * Format A:  STATE == shared
+ * Format C:  STATE != shared
+ */
+
+#define MD_SDIR_MASK            0xffff                  /* Whole entry      */
+#define MD_SDIR_ECC_SHFT        0                       /* AC low or high   */
+#define MD_SDIR_ECC_MASK        0x1f
+#define MD_SDIR_PRIO_SHFT       6                       /* AC low           */
+#define MD_SDIR_PRIO_MASK       (1 << 6)
+#define MD_SDIR_AX_SHFT         5                       /* AC low           */
+#define MD_SDIR_AX_MASK         (1 << 5)
+#define MD_SDIR_AX              (1 << 5)
+#define MD_SDIR_STATE_SHFT      7                       /* AC low           */
+#define MD_SDIR_STATE_MASK      (7 << 7)
+#define MD_SDIR_PTR_SHFT        10                      /* C low            */
+#define MD_SDIR_PTR_MASK        (0x3f << 10)
+#define MD_SDIR_CWOFF_SHFT      5                       /* C high           */
+#define MD_SDIR_CWOFF_MASK      (7 << 5)
+#define MD_SDIR_VECMSB_SHFT     11                      /* A low            */
+#define MD_SDIR_VECMSB_BITMASK  0x1f
+#define MD_SDIR_VECMSB_BITSHFT  7
+#define MD_SDIR_VECMSB_MASK     (MD_SDIR_VECMSB_BITMASK << 11)
+#define MD_SDIR_VECLSB_SHFT     5                       /* A high           */
+#define MD_SDIR_VECLSB_BITMASK  0x7ff
+#define MD_SDIR_VECLSB_BITSHFT  0
+#define MD_SDIR_VECLSB_MASK     (MD_SDIR_VECLSB_BITMASK << 5)
+
+/*
+ * Directory initialization values
+ */
+
+#define MD_SDIR_INIT_LO         (MD_DIR_UNOWNED << MD_SDIR_STATE_SHFT | \
+                                 MD_SDIR_AX)
+#define MD_SDIR_INIT_HI         0
+#define MD_SDIR_INIT_PROT       (MD_PROT_RW << MD_SPROT_SHFT)
+
+/* Protection and migration field values */
+
+#define MD_PROT_RW              (UINT64_CAST 0x6)
+#define MD_PROT_RO              (UINT64_CAST 0x3)
+#define MD_PROT_NO              (UINT64_CAST 0x0)
+#define MD_PROT_BAD             (UINT64_CAST 0x5)
+
+/* Premium SIMM protection entry shifts and masks. */
+
+#define MD_PPROT_SHFT           0                       /* Prot. field      */
+#define MD_PPROT_MASK           7
+#define MD_PPROT_MIGMD_SHFT     3                       /* Migration mode   */
+#define MD_PPROT_MIGMD_MASK     (3 << 3)
+#define MD_PPROT_REFCNT_SHFT    5                       /* Reference count  */
+#define MD_PPROT_REFCNT_WIDTH   0x7ffff
+#define MD_PPROT_REFCNT_MASK    (MD_PPROT_REFCNT_WIDTH << 5)
+
+#define MD_PPROT_IO_SHFT        45                      /* I/O Prot field   */
+#define MD_PPROT_IO_MASK        (UINT64_CAST 7 << 45)
+
+/* Standard SIMM protection entry shifts and masks. */
+
+#define MD_SPROT_SHFT           0                       /* Prot. field      */
+#define MD_SPROT_MASK           7
+#define MD_SPROT_MIGMD_SHFT     3                       /* Migration mode   */
+#define MD_SPROT_MIGMD_MASK     (3 << 3)
+#define MD_SPROT_REFCNT_SHFT    5                       /* Reference count  */
+#define MD_SPROT_REFCNT_WIDTH   0x7ff
+#define MD_SPROT_REFCNT_MASK    (MD_SPROT_REFCNT_WIDTH << 5)
+
+/* Migration modes used in protection entries */
+
+#define MD_PROT_MIGMD_IREL      (UINT64_CAST 0x3 << 3)
+#define MD_PROT_MIGMD_IABS      (UINT64_CAST 0x2 << 3)
+#define MD_PROT_MIGMD_PREL      (UINT64_CAST 0x1 << 3)
+#define MD_PROT_MIGMD_OFF       (UINT64_CAST 0x0 << 3)
+
+
+/*
+ * Operations on page migration threshold register
+ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * LED register macros
+ */
+
+#define CPU_LED_ADDR(_nasid, _slice)                                       \
+        (private.p_sn00 ?                                                  \
+         REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) :         \
+         REMOTE_HUB_ADDR((_nasid), MD_LED0    + ((_slice) << 3)))
+
+#define SET_CPU_LEDS(_nasid, _slice,  _val)                                \
+        (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
+
+#define SET_MY_LEDS(_v)                                                    \
+        SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
+
+/*
+ * Operations on Memory/Directory DIMM control register
+ */
+
+#define DIRTYPE_PREMIUM 1
+#define DIRTYPE_STANDARD 0
+#define MD_MEMORY_CONFIG_DIR_TYPE_GET(region) (\
+        (REMOTE_HUB_L(region, MD_MEMORY_CONFIG) & MMC_DIR_PREMIUM_MASK) >> \
+        MMC_DIR_PREMIUM_SHFT)
+
+
+/*
+ * Operations on page migration count difference and absolute threshold
+ * registers
+ */
+
+#define MD_MIG_DIFF_THRESH_GET(region) ( \
+        REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
+        MD_MIG_DIFF_THRES_VALUE_MASK)
+
+#define MD_MIG_DIFF_THRESH_SET(region, value) (                         \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                MD_MIG_DIFF_THRES_VALID_MASK | (value)))
+
+#define MD_MIG_DIFF_THRESH_DISABLE(region) (                    \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
+                             & ~MD_MIG_DIFF_THRES_VALID_MASK))
+
+#define MD_MIG_DIFF_THRESH_ENABLE(region) (                     \
+        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
+                REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
+                             | MD_MIG_DIFF_THRES_VALID_MASK))
+
+#define MD_MIG_DIFF_THRESH_IS_ENABLED(region) (                         \
+        REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) &                    \
+               MD_MIG_DIFF_THRES_VALID_MASK)
+
+#define MD_MIG_VALUE_THRESH_GET(region) (                               \
+        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &  \
+        MD_MIG_VALUE_THRES_VALUE_MASK)
+
+#define MD_MIG_VALUE_THRESH_SET(region, value) (                        \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                MD_MIG_VALUE_THRES_VALID_MASK | (value)))
+
+#define MD_MIG_VALUE_THRESH_DISABLE(region) (                   \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                REMOTE_HUB_L(region, MD_MIG_VALUE_THRESH)               \
+                             & ~MD_MIG_VALUE_THRES_VALID_MASK))
+
+#define MD_MIG_VALUE_THRESH_ENABLE(region) (                    \
+        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
+                REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH)             \
+                             | MD_MIG_VALUE_THRES_VALID_MASK))
+
+#define MD_MIG_VALUE_THRESH_IS_ENABLED(region) (                        \
+        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &                    \
+               MD_MIG_VALUE_THRES_VALID_MASK)
+
+/*
+ * Operations on page migration candidate register
+ */
+
+#define MD_MIG_CANDIDATE_GET(my_region_id) ( \
+        REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))
+
+#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)
+
+#define MD_MIG_CANDIDATE_NODEID(value) ( \
+        ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)
+
+#define MD_MIG_CANDIDATE_TYPE(value) ( \
+        ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)
+
+#define MD_MIG_CANDIDATE_VALID(value) ( \
+        ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)
+
+/*
+ * Macros to retrieve fields in the protection entry
+ */
+
+/* for Premium SIMM */
+#define MD_PPROT_REFCNT_GET(value) ( \
+        ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)
+
+#define MD_PPROT_MIGMD_GET(value) ( \
+        ((value) & MD_PPROT_MIGMD_MASK) >> MD_PPROT_MIGMD_SHFT)
+
+/* for Standard SIMM */
+#define MD_SPROT_REFCNT_GET(value) ( \
+        ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
+
+#define MD_SPROT_MIGMD_GET(value) ( \
+        ((value) & MD_SPROT_MIGMD_MASK) >> MD_SPROT_MIGMD_SHFT)
+
+/*
+ * Format of dir_error, mem_error, protocol_error and misc_error registers
+ */
+
+struct dir_error_reg {
+        u64     uce_vld:   1,   /*    63: valid directory uce   */
+                ae_vld:    1,   /*    62: valid dir prot ecc error */
+                ce_vld:    1,   /*    61: valid correctable ECC err*/
+                rsvd1:    19,   /* 60-42: reserved              */
+                bad_prot:  3,   /* 41-39: encoding, bad access rights*/
+                bad_syn:   7,   /* 38-32: bad dir syndrome      */
+                rsvd2:     2,   /* 31-30: reserved              */
+                hspec_addr:27,  /* 29-03: bddir space bad entry */
+                uce_ovr:   1,   /*     2: multiple dir uce's    */
+                ae_ovr:    1,   /*     1: multiple prot ecc errs*/
+                ce_ovr:    1;   /*     0: multiple correctable errs */
+};
+
+typedef union md_dir_error {
+        u64     derr_reg;       /* the entire register          */
+        struct dir_error_reg derr_fmt;  /* the register format          */
+} md_dir_error_t;
+
+
+struct mem_error_reg {
+        u64     uce_vld:   1,   /*    63: valid memory uce      */
+                ce_vld:    1,   /*    62: valid correctable ECC err*/
+                rsvd1:    22,   /* 61-40: reserved              */
+                bad_syn:   8,   /* 39-32: bad mem ecc syndrome  */
+                address:  29,   /* 31-03: bad entry pointer     */
+                rsvd2:     1,   /*     2: reserved              */
+                uce_ovr:   1,   /*     1: multiple mem uce's    */
+                ce_ovr:    1;   /*     0: multiple correctable errs */
+};
+
+
+typedef union md_mem_error {
+        u64     merr_reg;       /* the entire register          */
+        struct mem_error_reg  merr_fmt; /* format of the mem_error reg  */
+} md_mem_error_t;
+
+
+struct proto_error_reg {
+        u64     valid:     1,   /*    63: valid protocol error  */
+                rsvd1:     2,   /* 62-61: reserved              */
+                initiator:11,   /* 60-50: id of request initiator*/
+                backoff:   2,   /* 49-48: backoff control       */
+                msg_type:  8,   /* 47-40: type of request       */
+                access:    2,   /* 39-38: access rights of initiator*/
+                priority:  1,   /*    37: priority level of requestor*/
+                dir_state: 4,   /* 36-33: state of directory    */
+                pointer_me:1,   /*    32: initiator same as dir ptr */
+                address:  29,   /* 31-03: request address       */
+                rsvd2:     2,   /* 02-01: reserved              */
+                overrun:   1;   /*     0: multiple protocol errs */
+};
+
+typedef union md_proto_error {
+        u64     perr_reg;       /* the entire register          */
+        struct proto_error_reg  perr_fmt; /* format of the register     */
+} md_proto_error_t;
+
+
+struct md_sdir_high_fmt {
+        unsigned short sd_hi_bvec : 11,
+                       sd_hi_ecc  : 5;
+};
+
+
+typedef union md_sdir_high {
+        /* The 16 bits of standard directory, upper word */
+        unsigned short sd_hi_val;
+        struct  md_sdir_high_fmt sd_hi_fmt;
+}md_sdir_high_t;
+
+
+struct md_sdir_low_shared_fmt {
+        /* The meaning of lower directory, shared */
+        unsigned short  sds_lo_bvec  : 5,
+                        sds_lo_unused: 1,
+                        sds_lo_state : 3,
+                        sds_lo_prio  : 1,
+                        sds_lo_ax    : 1,
+                        sds_lo_ecc   : 5;
+};
+
+struct md_sdir_low_exclusive_fmt {
+        /* The meaning of lower directory, exclusive */
+        unsigned short  sde_lo_ptr   : 6,
+                        sde_lo_state : 3,
+                        sde_lo_prio  : 1,
+                        sde_lo_ax    : 1,
+                        sde_lo_ecc   : 5;
+};
+
+
+typedef union md_sdir_low {
+        /* The 16 bits of standard directory, lower word */
+        unsigned short  sd_lo_val;
+        struct  md_sdir_low_exclusive_fmt sde_lo_fmt;
+        struct  md_sdir_low_shared_fmt sds_lo_fmt;
+}md_sdir_low_t;
+
+
+
+struct md_pdir_high_fmt {
+        u64     pd_hi_unused   : 16,
+                pd_hi_bvec     : 38,
+                pd_hi_unused1  : 3,
+                pd_hi_ecc      : 7;
+};
+
+
+typedef union md_pdir_high {
+        /* The 48 bits of standard directory, upper word */
+        u64     pd_hi_val;
+        struct md_pdir_high_fmt pd_hi_fmt;
+}md_pdir_high_t;
+
+
+struct md_pdir_low_shared_fmt {
+        /* The meaning of lower directory, shared */
+        u64     pds_lo_unused   : 16,
+                pds_lo_bvec     : 26,
+                pds_lo_cnt      :  6,
+                pds_lo_state    :  3,
+                pds_lo_ste      :  1,
+                pds_lo_prio     :  4,
+                pds_lo_ax       :  1,
+                pds_lo_ecc      :  7;
+};
+
+struct md_pdir_low_exclusive_fmt {
+        /* The meaning of lower directory, exclusive */
+        u64     pde_lo_unused   : 31,
+                pde_lo_ptr      : 11,
+                pde_lo_unused1  :  6,
+                pde_lo_state    :  3,
+                pde_lo_ste      :  1,
+                pde_lo_prio     :  4,
+                pde_lo_ax       :  1,
+                pde_lo_ecc      :  7;
+};
+
+
+typedef union md_pdir_loent {
+        /* The 48 bits of premium directory, lower word */
+        u64     pd_lo_val;
+        struct md_pdir_low_exclusive_fmt pde_lo_fmt;
+        struct md_pdir_low_shared_fmt   pds_lo_fmt;
+}md_pdir_low_t;
+
+
+/*
+ *   the following two "union" definitions and two
+ *   "struct" definitions are used in vmdump.c to
+ *   represent directory memory information.
+ */
+
+typedef union   md_dir_high     {
+        md_sdir_high_t  md_sdir_high;
+        md_pdir_high_t  md_pdir_high;
+} md_dir_high_t;
+
+typedef union   md_dir_low      {
+        md_sdir_low_t   md_sdir_low;
+        md_pdir_low_t   md_pdir_low;
+} md_dir_low_t;
+
+typedef struct  bddir_entry     {
+        md_dir_low_t    md_dir_low;
+        md_dir_high_t   md_dir_high;
+} bddir_entry_t;
+
+typedef struct  dir_mem_entry   {
+        u64             prcpf[MAX_REGIONS];
+        bddir_entry_t   directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
+} dir_mem_entry_t;
+
+
+
+typedef union md_perf_sel {
+        u64     perf_sel_reg;
+        struct  {
+                u64     perf_rsvd : 60,
+                        perf_en   :  1,
+                        perf_sel  :  3;
+        } perf_sel_bits;
+} md_perf_sel_t;
+
+typedef union md_perf_cnt {
+        u64     perf_cnt;
+        struct  {
+                u64     perf_rsvd : 44,
+                        perf_cnt  : 20;
+        } perf_cnt_bits;
+} md_perf_cnt_t;
+
+
+#endif /* !__ASSEMBLY__ */
+
+
+#define DIR_ERROR_VALID_MASK    0xe000000000000000
+#define DIR_ERROR_VALID_SHFT    61
+#define DIR_ERROR_VALID_UCE     0x8000000000000000
+#define DIR_ERROR_VALID_AE      0x4000000000000000
+#define DIR_ERROR_VALID_CE      0x2000000000000000
+
+#define MEM_ERROR_VALID_MASK    0xc000000000000000
+#define MEM_ERROR_VALID_SHFT    62
+#define MEM_ERROR_VALID_UCE     0x8000000000000000
+#define MEM_ERROR_VALID_CE      0x4000000000000000
+
+#define PROTO_ERROR_VALID_MASK  0x8000000000000000
+
+#define MISC_ERROR_VALID_MASK   0x3ff
+
+/*
+ * Mask for hspec address that is stored in the dir error register.
+ * This represents bits 29 through 3.
+ */
+#define DIR_ERR_HSPEC_MASK      0x3ffffff8
+#define ERROR_HSPEC_MASK        0x3ffffff8
+#define ERROR_HSPEC_SHFT        3
+#define ERROR_ADDR_MASK         0xfffffff8
+#define ERROR_ADDR_SHFT         3
+
+/*
+ * MD_MISC_ERROR register defines.
+ */
+
+#define MMCE_VALID_MASK         0x3ff
+#define MMCE_ILL_MSG_SHFT       8
+#define MMCE_ILL_MSG_MASK       (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
+#define MMCE_ILL_REV_SHFT       6
+#define MMCE_ILL_REV_MASK       (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
+#define MMCE_LONG_PACK_SHFT     4
+#define MMCE_LONG_PACK_MASK     (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
+#define MMCE_SHORT_PACK_SHFT    2
+#define MMCE_SHORT_PACK_MASK    (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
+#define MMCE_BAD_DATA_SHFT      0
+#define MMCE_BAD_DATA_MASK      (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
+
+
+#define MD_PERF_COUNTERS        6
+#define MD_PERF_SETS            6
+
+#define MEM_DIMM_MASK                           0xe0000000
+#define MEM_DIMM_SHFT                           29
+
+#endif /* _ASM_SN_SN0_HUBMD_H */
diff --git a/include/asm-mips/sn/sn0/hubni.h b/include/asm-mips/sn/sn0/hubni.h
new file mode 100644
index 000000000000..b40d3ef97a12
--- /dev/null
+++ b/include/asm-mips/sn/sn0/hubni.h
@@ -0,0 +1,255 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
+ *
+ * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SGI_SN0_HUBNI_H
+#define _ASM_SGI_SN0_HUBNI_H
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#endif
+
+/*
+ * Hub Network Interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ */
+
+#define NI_BASE                 0x600000
+#define NI_BASE_TABLES          0x630000
+
+#define NI_STATUS_REV_ID        0x600000 /* Hub network status, rev, and ID */
+#define NI_PORT_RESET           0x600008 /* Reset the network interface     */
+#define NI_PROTECTION           0x600010 /* NI register access permissions  */
+#define NI_GLOBAL_PARMS         0x600018 /* LLP parameters                  */
+#define NI_SCRATCH_REG0         0x600100 /* Scratch register 0 (64 bits)    */
+#define NI_SCRATCH_REG1         0x600108 /* Scratch register 1 (64 bits)    */
+#define NI_DIAG_PARMS           0x600110 /* Parameters for diags            */
+
+#define NI_VECTOR_PARMS         0x600200 /* Vector PIO routing parameters   */
+#define NI_VECTOR               0x600208 /* Vector PIO route                */
+#define NI_VECTOR_DATA          0x600210 /* Vector PIO data                 */
+#define NI_VECTOR_STATUS        0x600300 /* Vector PIO return status        */
+#define NI_RETURN_VECTOR        0x600308 /* Vector PIO return vector        */
+#define NI_VECTOR_READ_DATA     0x600310 /* Vector PIO read data            */
+#define NI_VECTOR_CLEAR         0x600380 /* Vector PIO read & clear status  */
+
+#define NI_IO_PROTECT           0x600400 /* PIO protection bits             */
+#define NI_IO_PROT_OVRRD        0x600408 /* PIO protection bit override     */
+
+#define NI_AGE_CPU0_MEMORY      0x600500 /* CPU 0 memory age control        */
+#define NI_AGE_CPU0_PIO         0x600508 /* CPU 0 PIO age control           */
+#define NI_AGE_CPU1_MEMORY      0x600510 /* CPU 1 memory age control        */
+#define NI_AGE_CPU1_PIO         0x600518 /* CPU 1 PIO age control           */
+#define NI_AGE_GBR_MEMORY       0x600520 /* GBR memory age control          */
+#define NI_AGE_GBR_PIO          0x600528 /* GBR PIO age control             */
+#define NI_AGE_IO_MEMORY        0x600530 /* IO memory age control           */
+#define NI_AGE_IO_PIO           0x600538 /* IO PIO age control              */
+#define NI_AGE_REG_MIN          NI_AGE_CPU0_MEMORY
+#define NI_AGE_REG_MAX          NI_AGE_IO_PIO
+
+#define NI_PORT_PARMS           0x608000 /* LLP Parameters                  */
+#define NI_PORT_ERROR           0x608008 /* LLP Errors                      */
+#define NI_PORT_ERROR_CLEAR     0x608088 /* Clear the error bits            */
+
+#define NI_META_TABLE0          0x638000 /* First meta routing table entry  */
+#define NI_META_TABLE(_x)       (NI_META_TABLE0 + (8 * (_x)))
+#define NI_META_ENTRIES         32
+
+#define NI_LOCAL_TABLE0         0x638100 /* First local routing table entry */
+#define NI_LOCAL_TABLE(_x)      (NI_LOCAL_TABLE0 + (8 * (_x)))
+#define NI_LOCAL_ENTRIES        16
+
+/*
+ * NI_STATUS_REV_ID mask and shift definitions
+ * Have to use UINT64_CAST instead of 'L' suffix, for assembler.
+ */
+
+#define NSRI_8BITMODE_SHFT      30
+#define NSRI_8BITMODE_MASK      (UINT64_CAST 0x1 << 30)
+#define NSRI_LINKUP_SHFT        29
+#define NSRI_LINKUP_MASK        (UINT64_CAST 0x1 << 29)
+#define NSRI_DOWNREASON_SHFT    28              /* 0=failed, 1=never came   */
+#define NSRI_DOWNREASON_MASK    (UINT64_CAST 0x1 << 28) /*    out of reset. */
+#define NSRI_MORENODES_SHFT     18
+#define NSRI_MORENODES_MASK     (UINT64_CAST 1 << 18)   /* Max. # of nodes  */
+#define  MORE_MEMORY            0
+#define  MORE_NODES             1
+#define NSRI_REGIONSIZE_SHFT    17
+#define NSRI_REGIONSIZE_MASK    (UINT64_CAST 1 << 17)   /* Granularity      */
+#define  REGIONSIZE_FINE        1
+#define  REGIONSIZE_COARSE      0
+#define NSRI_NODEID_SHFT        8
+#define NSRI_NODEID_MASK        (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID    */
+#define NSRI_REV_SHFT           4
+#define NSRI_REV_MASK           (UINT64_CAST 0xf << 4)  /* Chip Revision    */
+#define NSRI_CHIPID_SHFT        0
+#define NSRI_CHIPID_MASK        (UINT64_CAST 0xf)       /* Chip type ID     */
+
+/*
+ * In fine mode, each node is a region.  In coarse mode, there are
+ * eight nodes per region.
+ */
+#define NASID_TO_FINEREG_SHFT   0
+#define NASID_TO_COARSEREG_SHFT 3
+
+/* NI_PORT_RESET mask definitions */
+
+#define NPR_PORTRESET           (UINT64_CAST 1 << 7)    /* Send warm reset  */
+#define NPR_LINKRESET           (UINT64_CAST 1 << 1)    /* Send link reset  */
+#define NPR_LOCALRESET          (UINT64_CAST 1)         /* Reset entire hub */
+
+/* NI_PROTECTION mask and shift definitions */
+
+#define NPROT_RESETOK           (UINT64_CAST 1)
+
+/* NI_GLOBAL_PARMS mask and shift definitions */
+
+#define NGP_MAXRETRY_SHFT       48              /* Maximum retries          */
+#define NGP_MAXRETRY_MASK       (UINT64_CAST 0x3ff << 48)
+#define NGP_TAILTOWRAP_SHFT     32              /* Tail timeout wrap        */
+#define NGP_TAILTOWRAP_MASK     (UINT64_CAST 0xffff << 32)
+
+#define NGP_CREDITTOVAL_SHFT    16              /* Tail timeout wrap        */
+#define NGP_CREDITTOVAL_MASK    (UINT64_CAST 0xf << 16)
+#define NGP_TAILTOVAL_SHFT      4               /* Tail timeout value       */
+#define NGP_TAILTOVAL_MASK      (UINT64_CAST 0xf << 4)
+
+/* NI_DIAG_PARMS mask and shift definitions */
+
+#define NDP_PORTTORESET         (UINT64_CAST 1 << 18)   /* Port tmout reset */
+#define NDP_LLP8BITMODE         (UINT64_CAST 1 << 12)   /* LLP 8-bit mode   */
+#define NDP_PORTDISABLE         (UINT64_CAST 1 <<  6)   /* Port disable     */
+#define NDP_SENDERROR           (UINT64_CAST 1)         /* Send data error  */
+
+/*
+ * NI_VECTOR_PARMS mask and shift definitions.
+ * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
+ */
+
+#define NVP_PIOID_SHFT          40
+#define NVP_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
+#define NVP_WRITEID_SHFT        32
+#define NVP_WRITEID_MASK        (UINT64_CAST 0xff << 32)
+#define NVP_ADDRESS_MASK        (UINT64_CAST 0xffff8)   /* Bits 19:3        */
+#define NVP_TYPE_SHFT           0
+#define NVP_TYPE_MASK           (UINT64_CAST 0x3)
+
+/* NI_VECTOR_STATUS mask and shift definitions */
+
+#define NVS_VALID               (UINT64_CAST 1 << 63)
+#define NVS_OVERRUN             (UINT64_CAST 1 << 62)
+#define NVS_TARGET_SHFT         51
+#define NVS_TARGET_MASK         (UINT64_CAST 0x3ff << 51)
+#define NVS_PIOID_SHFT          40
+#define NVS_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
+#define NVS_WRITEID_SHFT        32
+#define NVS_WRITEID_MASK        (UINT64_CAST 0xff << 32)
+#define NVS_ADDRESS_MASK        (UINT64_CAST 0xfffffff8)   /* Bits 31:3     */
+#define NVS_TYPE_SHFT           0
+#define NVS_TYPE_MASK           (UINT64_CAST 0x7)
+#define NVS_ERROR_MASK          (UINT64_CAST 0x4)  /* bit set means error */
+
+
+#define  PIOTYPE_READ           0       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_WRITE          1       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_UNDEFINED      2       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_EXCHANGE       3       /* VECTOR_PARMS and VECTOR_STATUS   */
+#define  PIOTYPE_ADDR_ERR       4       /* VECTOR_STATUS only               */
+#define  PIOTYPE_CMD_ERR        5       /* VECTOR_STATUS only               */
+#define  PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
+#define  PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
+
+/* NI_AGE_XXX mask and shift definitions */
+
+#define NAGE_VCH_SHFT           10
+#define NAGE_VCH_MASK           (UINT64_CAST 3 << 10)
+#define NAGE_CC_SHFT            8
+#define NAGE_CC_MASK            (UINT64_CAST 3 << 8)
+#define NAGE_AGE_SHFT           0
+#define NAGE_AGE_MASK           (UINT64_CAST 0xff)
+#define NAGE_MASK               (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
+
+#define  VCHANNEL_A             0
+#define  VCHANNEL_B             1
+#define  VCHANNEL_ANY           2
+
+/* NI_PORT_PARMS mask and shift definitions */
+
+#define NPP_NULLTO_SHFT         10
+#define NPP_NULLTO_MASK         (UINT64_CAST 0x3f << 16)
+#define NPP_MAXBURST_SHFT       0
+#define NPP_MAXBURST_MASK       (UINT64_CAST 0x3ff)
+#define NPP_RESET_DFLT_HUB20    ((UINT64_CAST 1     << NPP_NULLTO_SHFT) | \
+                                 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
+#define NPP_RESET_DEFAULTS      ((UINT64_CAST 6     << NPP_NULLTO_SHFT) | \
+                                 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
+
+
+/* NI_PORT_ERROR mask and shift definitions */
+
+#define NPE_LINKRESET           (UINT64_CAST 1 << 37)
+#define NPE_INTERNALERROR       (UINT64_CAST 1 << 36)
+#define NPE_BADMESSAGE          (UINT64_CAST 1 << 35)
+#define NPE_BADDEST             (UINT64_CAST 1 << 34)
+#define NPE_FIFOOVERFLOW        (UINT64_CAST 1 << 33)
+#define NPE_CREDITTO_SHFT       28
+#define NPE_CREDITTO_MASK       (UINT64_CAST 0xf << 28)
+#define NPE_TAILTO_SHFT         24
+#define NPE_TAILTO_MASK         (UINT64_CAST 0xf << 24)
+#define NPE_RETRYCOUNT_SHFT     16
+#define NPE_RETRYCOUNT_MASK     (UINT64_CAST 0xff << 16)
+#define NPE_CBERRCOUNT_SHFT     8
+#define NPE_CBERRCOUNT_MASK     (UINT64_CAST 0xff << 8)
+#define NPE_SNERRCOUNT_SHFT     0
+#define NPE_SNERRCOUNT_MASK     (UINT64_CAST 0xff << 0)
+#define NPE_MASK                0x3effffffff
+
+#define NPE_COUNT_MAX           0xff
+
+#define NPE_FATAL_ERRORS        (NPE_LINKRESET | NPE_INTERNALERROR |    \
+                                 NPE_BADMESSAGE | NPE_BADDEST |         \
+                                 NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
+                                 NPE_TAILTO_MASK)
+
+/* NI_META_TABLE mask and shift definitions */
+
+#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
+
+/* NI_LOCAL_TABLE mask and shift definitions */
+
+#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
+
+#ifndef __ASSEMBLY__
+
+typedef union   hubni_port_error_u {
+        u64     nipe_reg_value;
+        struct {
+            u64 nipe_rsvd:      26,     /* unused */
+                nipe_lnk_reset:  1,     /* link reset */
+                nipe_intl_err:   1,     /* internal error */
+                nipe_bad_msg:    1,     /* bad message */
+                nipe_bad_dest:   1,     /* bad dest     */
+                nipe_fifo_ovfl:  1,     /* fifo overflow */
+                nipe_rsvd1:      1,     /* unused */
+                nipe_credit_to:  4,     /* credit timeout */
+                nipe_tail_to:    4,     /* tail timeout */
+                nipe_retry_cnt:  8,     /* retry error count */
+                nipe_cb_cnt:     8,     /* checkbit error count */
+                nipe_sn_cnt:     8;     /* sequence number count */
+        } nipe_fields_s;
+} hubni_port_error_t;
+
+#define NI_LLP_RETRY_MAX        0xff
+#define NI_LLP_CB_MAX           0xff
+#define NI_LLP_SN_MAX           0xff
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_SGI_SN0_HUBNI_H */
diff --git a/include/asm-mips/sn/sn0/hubpi.h b/include/asm-mips/sn/sn0/hubpi.h
new file mode 100644
index 000000000000..355bba8552e3
--- /dev/null
+++ b/include/asm-mips/sn/sn0/hubpi.h
@@ -0,0 +1,427 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_HUBPI_H
+#define _ASM_SN_SN0_HUBPI_H
+
+#include <linux/types.h>
+
+/*
+ * Hub I/O interface registers
+ *
+ * All registers in this file are subject to change until Hub chip tapeout.
+ * All register "addresses" are actually offsets.  Use the LOCAL_HUB
+ * or REMOTE_HUB macros to synthesize an actual address
+ */
+
+#define PI_BASE                 0x000000
+
+/* General protection and control registers */
+
+#define PI_CPU_PROTECT          0x000000 /* CPU Protection                  */
+#define PI_PROT_OVERRD          0x000008 /* Clear CPU Protection bit        */
+#define PI_IO_PROTECT           0x000010 /* Interrupt Pending Protection    */
+#define PI_REGION_PRESENT       0x000018 /* Indicates whether region exists */
+#define PI_CPU_NUM              0x000020 /* CPU Number ID                   */
+#define PI_CALIAS_SIZE          0x000028 /* Cached Alias Size               */
+#define PI_MAX_CRB_TIMEOUT      0x000030 /* Maximum Timeout for CRB         */
+#define PI_CRB_SFACTOR          0x000038 /* Scale factor for CRB timeout    */
+
+/* CALIAS values */
+#define PI_CALIAS_SIZE_0        0
+#define PI_CALIAS_SIZE_4K       1
+#define PI_CALIAS_SIZE_8K       2
+#define PI_CALIAS_SIZE_16K      3
+#define PI_CALIAS_SIZE_32K      4
+#define PI_CALIAS_SIZE_64K      5
+#define PI_CALIAS_SIZE_128K     6
+#define PI_CALIAS_SIZE_256K     7
+#define PI_CALIAS_SIZE_512K     8
+#define PI_CALIAS_SIZE_1M       9
+#define PI_CALIAS_SIZE_2M       10
+#define PI_CALIAS_SIZE_4M       11
+#define PI_CALIAS_SIZE_8M       12
+#define PI_CALIAS_SIZE_16M      13
+#define PI_CALIAS_SIZE_32M      14
+#define PI_CALIAS_SIZE_64M      15
+
+/* Processor control and status checking */
+
+#define PI_CPU_PRESENT_A        0x000040 /* CPU Present A                   */
+#define PI_CPU_PRESENT_B        0x000048 /* CPU Present B                   */
+#define PI_CPU_ENABLE_A         0x000050 /* CPU Enable A                    */
+#define PI_CPU_ENABLE_B         0x000058 /* CPU Enable B                    */
+#define PI_REPLY_LEVEL          0x000060 /* Reply Level                     */
+#define PI_HARDRESET_BIT        0x020068 /* Bit cleared by s/w on SR        */
+#define PI_NMI_A                0x000070 /* NMI to CPU A                    */
+#define PI_NMI_B                0x000078 /* NMI to CPU B                    */
+#define PI_NMI_OFFSET           (PI_NMI_B - PI_NMI_A)
+#define PI_SOFTRESET            0x000080 /* Softreset (to both CPUs)        */
+
+/* Regular Interrupt register checking.  */
+
+#define PI_INT_PEND_MOD         0x000090 /* Write to set pending ints       */
+#define PI_INT_PEND0            0x000098 /* Read to get pending ints        */
+#define PI_INT_PEND1            0x0000a0 /* Read to get pending ints        */
+#define PI_INT_MASK0_A          0x0000a8 /* Interrupt Mask 0 for CPU A      */
+#define PI_INT_MASK1_A          0x0000b0 /* Interrupt Mask 1 for CPU A      */
+#define PI_INT_MASK0_B          0x0000b8 /* Interrupt Mask 0 for CPU B      */
+#define PI_INT_MASK1_B          0x0000c0 /* Interrupt Mask 1 for CPU B      */
+
+#define PI_INT_MASK_OFFSET      0x10     /* Offset from A to B              */
+
+/* Crosscall interrupts */
+
+#define PI_CC_PEND_SET_A        0x0000c8 /* CC Interrupt Pending Set, CPU A */
+#define PI_CC_PEND_SET_B        0x0000d0 /* CC Interrupt Pending Set, CPU B */
+#define PI_CC_PEND_CLR_A        0x0000d8 /* CC Interrupt Pending Clr, CPU A */
+#define PI_CC_PEND_CLR_B        0x0000e0 /* CC Interrupt Pending Clr, CPU B */
+#define PI_CC_MASK              0x0000e8 /* CC Interrupt mask               */
+
+#define PI_INT_SET_OFFSET       0x08     /* Offset from A to B              */
+
+/* Realtime Counter and Profiler control registers */
+
+#define PI_RT_COUNT             0x030100 /* Real Time Counter               */
+#define PI_RT_COMPARE_A         0x000108 /* Real Time Compare A             */
+#define PI_RT_COMPARE_B         0x000110 /* Real Time Compare B             */
+#define PI_PROFILE_COMPARE      0x000118 /* L5 int to both cpus when == RTC */
+#define PI_RT_PEND_A            0x000120 /* Set if RT int for A pending     */
+#define PI_RT_PEND_B            0x000128 /* Set if RT int for B pending     */
+#define PI_PROF_PEND_A          0x000130 /* Set if Prof int for A pending   */
+#define PI_PROF_PEND_B          0x000138 /* Set if Prof int for B pending   */
+#define PI_RT_EN_A              0x000140 /* RT int for CPU A enable         */
+#define PI_RT_EN_B              0x000148 /* RT int for CPU B enable         */
+#define PI_PROF_EN_A            0x000150 /* PROF int for CPU A enable       */
+#define PI_PROF_EN_B            0x000158 /* PROF int for CPU B enable       */
+#define PI_RT_LOCAL_CTRL        0x000160 /* RT control register             */
+#define PI_RT_FILTER_CTRL       0x000168 /* GCLK Filter control register    */
+
+#define PI_COUNT_OFFSET         0x08     /* A to B offset for all counts    */
+
+/* Built-In Self Test support */
+
+#define PI_BIST_WRITE_DATA      0x000200 /* BIST write data                 */
+#define PI_BIST_READ_DATA       0x000208 /* BIST read data                  */
+#define PI_BIST_COUNT_TARG      0x000210 /* BIST Count and Target           */
+#define PI_BIST_READY           0x000218 /* BIST Ready indicator            */
+#define PI_BIST_SHIFT_LOAD      0x000220 /* BIST control                    */
+#define PI_BIST_SHIFT_UNLOAD    0x000228 /* BIST control                    */
+#define PI_BIST_ENTER_RUN       0x000230 /* BIST control                    */
+
+/* Graphics control registers */
+
+#define PI_GFX_PAGE_A           0x000300 /* Graphics page A                 */
+#define PI_GFX_CREDIT_CNTR_A    0x000308 /* Graphics credit counter A       */
+#define PI_GFX_BIAS_A           0x000310 /* Graphics bias A                 */
+#define PI_GFX_INT_CNTR_A       0x000318 /* Graphics interrupt counter A    */
+#define PI_GFX_INT_CMP_A        0x000320 /* Graphics interrupt comparator A */
+#define PI_GFX_PAGE_B           0x000328 /* Graphics page B                 */
+#define PI_GFX_CREDIT_CNTR_B    0x000330 /* Graphics credit counter B       */
+#define PI_GFX_BIAS_B           0x000338 /* Graphics bias B                 */
+#define PI_GFX_INT_CNTR_B       0x000340 /* Graphics interrupt counter B    */
+#define PI_GFX_INT_CMP_B        0x000348 /* Graphics interrupt comparator B */
+
+#define PI_GFX_OFFSET           (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
+#define PI_GFX_PAGE_ENABLE      0x0000010000000000LL
+
+/* Error and timeout registers */
+#define PI_ERR_INT_PEND         0x000400 /* Error Interrupt Pending         */
+#define PI_ERR_INT_MASK_A       0x000408 /* Error Interrupt mask for CPU A  */
+#define PI_ERR_INT_MASK_B       0x000410 /* Error Interrupt mask for CPU B  */
+#define PI_ERR_STACK_ADDR_A     0x000418 /* Error stack address for CPU A   */
+#define PI_ERR_STACK_ADDR_B     0x000420 /* Error stack address for CPU B   */
+#define PI_ERR_STACK_SIZE       0x000428 /* Error Stack Size                */
+#define PI_ERR_STATUS0_A        0x000430 /* Error Status 0A                 */
+#define PI_ERR_STATUS0_A_RCLR   0x000438 /* Error Status 0A clear on read   */
+#define PI_ERR_STATUS1_A        0x000440 /* Error Status 1A                 */
+#define PI_ERR_STATUS1_A_RCLR   0x000448 /* Error Status 1A clear on read   */
+#define PI_ERR_STATUS0_B        0x000450 /* Error Status 0B                 */
+#define PI_ERR_STATUS0_B_RCLR   0x000458 /* Error Status 0B clear on read   */
+#define PI_ERR_STATUS1_B        0x000460 /* Error Status 1B                 */
+#define PI_ERR_STATUS1_B_RCLR   0x000468 /* Error Status 1B clear on read   */
+#define PI_SPOOL_CMP_A          0x000470 /* Spool compare for CPU A         */
+#define PI_SPOOL_CMP_B          0x000478 /* Spool compare for CPU B         */
+#define PI_CRB_TIMEOUT_A        0x000480 /* Timed out CRB entries for A     */
+#define PI_CRB_TIMEOUT_B        0x000488 /* Timed out CRB entries for B     */
+#define PI_SYSAD_ERRCHK_EN      0x000490 /* Enables SYSAD error checking    */
+#define PI_BAD_CHECK_BIT_A      0x000498 /* Force SYSAD check bit error     */
+#define PI_BAD_CHECK_BIT_B      0x0004a0 /* Force SYSAD check bit error     */
+#define PI_NACK_CNT_A           0x0004a8 /* Consecutive NACK counter        */
+#define PI_NACK_CNT_B           0x0004b0 /*     "       " for CPU B         */
+#define PI_NACK_CMP             0x0004b8 /* NACK count compare              */
+#define PI_STACKADDR_OFFSET     (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
+#define PI_ERRSTAT_OFFSET       (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
+#define PI_RDCLR_OFFSET         (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
+
+/* Bits in PI_ERR_INT_PEND */
+#define PI_ERR_SPOOL_CMP_B      0x00000001      /* Spool end hit high water */
+#define PI_ERR_SPOOL_CMP_A      0x00000002
+#define PI_ERR_SPUR_MSG_B       0x00000004      /* Spurious message intr.   */
+#define PI_ERR_SPUR_MSG_A       0x00000008
+#define PI_ERR_WRB_TERR_B       0x00000010      /* WRB TERR                 */
+#define PI_ERR_WRB_TERR_A       0x00000020
+#define PI_ERR_WRB_WERR_B       0x00000040      /* WRB WERR                 */
+#define PI_ERR_WRB_WERR_A       0x00000080
+#define PI_ERR_SYSSTATE_B       0x00000100      /* SysState parity error    */
+#define PI_ERR_SYSSTATE_A       0x00000200
+#define PI_ERR_SYSAD_DATA_B     0x00000400      /* SysAD data parity error  */
+#define PI_ERR_SYSAD_DATA_A     0x00000800
+#define PI_ERR_SYSAD_ADDR_B     0x00001000      /* SysAD addr parity error  */
+#define PI_ERR_SYSAD_ADDR_A     0x00002000
+#define PI_ERR_SYSCMD_DATA_B    0x00004000      /* SysCmd data parity error */
+#define PI_ERR_SYSCMD_DATA_A    0x00008000
+#define PI_ERR_SYSCMD_ADDR_B    0x00010000      /* SysCmd addr parity error */
+#define PI_ERR_SYSCMD_ADDR_A    0x00020000
+#define PI_ERR_BAD_SPOOL_B      0x00040000      /* Error spooling to memory */
+#define PI_ERR_BAD_SPOOL_A      0x00080000
+#define PI_ERR_UNCAC_UNCORR_B   0x00100000      /* Uncached uncorrectable   */
+#define PI_ERR_UNCAC_UNCORR_A   0x00200000
+#define PI_ERR_SYSSTATE_TAG_B   0x00400000      /* SysState tag parity error */
+#define PI_ERR_SYSSTATE_TAG_A   0x00800000
+#define PI_ERR_MD_UNCORR        0x01000000      /* Must be cleared in MD    */
+
+#define PI_ERR_CLEAR_ALL_A      0x00aaaaaa
+#define PI_ERR_CLEAR_ALL_B      0x00555555
+
+
+/*
+ * The following three macros define all possible error int pends.
+ */
+
+#define PI_FATAL_ERR_CPU_A      (PI_ERR_SYSSTATE_TAG_A  | \
+                                 PI_ERR_BAD_SPOOL_A     | \
+                                 PI_ERR_SYSCMD_ADDR_A   | \
+                                 PI_ERR_SYSCMD_DATA_A   | \
+                                 PI_ERR_SYSAD_ADDR_A    | \
+                                 PI_ERR_SYSAD_DATA_A    | \
+                                 PI_ERR_SYSSTATE_A)
+
+#define PI_MISC_ERR_CPU_A       (PI_ERR_UNCAC_UNCORR_A  | \
+                                 PI_ERR_WRB_WERR_A      | \
+                                 PI_ERR_WRB_TERR_A      | \
+                                 PI_ERR_SPUR_MSG_A      | \
+                                 PI_ERR_SPOOL_CMP_A)
+
+#define PI_FATAL_ERR_CPU_B      (PI_ERR_SYSSTATE_TAG_B  | \
+                                 PI_ERR_BAD_SPOOL_B     | \
+                                 PI_ERR_SYSCMD_ADDR_B   | \
+                                 PI_ERR_SYSCMD_DATA_B   | \
+                                 PI_ERR_SYSAD_ADDR_B    | \
+                                 PI_ERR_SYSAD_DATA_B    | \
+                                 PI_ERR_SYSSTATE_B)
+
+#define PI_MISC_ERR_CPU_B       (PI_ERR_UNCAC_UNCORR_B  | \
+                                 PI_ERR_WRB_WERR_B      | \
+                                 PI_ERR_WRB_TERR_B      | \
+                                 PI_ERR_SPUR_MSG_B      | \
+                                 PI_ERR_SPOOL_CMP_B)
+
+#define PI_ERR_GENERIC  (PI_ERR_MD_UNCORR)
+
+/*
+ * Error types for PI_ERR_STATUS0_[AB] and error stack:
+ * Use the write types if WRBRRB is 1 else use the read types
+ */
+
+/* Fields in PI_ERR_STATUS0_[AB] */
+#define PI_ERR_ST0_TYPE_MASK    0x0000000000000007
+#define PI_ERR_ST0_TYPE_SHFT    0
+#define PI_ERR_ST0_REQNUM_MASK  0x0000000000000038
+#define PI_ERR_ST0_REQNUM_SHFT  3
+#define PI_ERR_ST0_SUPPL_MASK   0x000000000001ffc0
+#define PI_ERR_ST0_SUPPL_SHFT   6
+#define PI_ERR_ST0_CMD_MASK     0x0000000001fe0000
+#define PI_ERR_ST0_CMD_SHFT     17
+#define PI_ERR_ST0_ADDR_MASK    0x3ffffffffe000000
+#define PI_ERR_ST0_ADDR_SHFT    25
+#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000
+#define PI_ERR_ST0_OVERRUN_SHFT 62
+#define PI_ERR_ST0_VALID_MASK   0x8000000000000000
+#define PI_ERR_ST0_VALID_SHFT   63
+
+/* Fields in PI_ERR_STATUS1_[AB] */
+#define PI_ERR_ST1_SPOOL_MASK   0x00000000001fffff
+#define PI_ERR_ST1_SPOOL_SHFT   0
+#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000
+#define PI_ERR_ST1_TOUTCNT_SHFT 21
+#define PI_ERR_ST1_INVCNT_MASK  0x0000007fe0000000
+#define PI_ERR_ST1_INVCNT_SHFT  29
+#define PI_ERR_ST1_CRBNUM_MASK  0x0000038000000000
+#define PI_ERR_ST1_CRBNUM_SHFT  39
+#define PI_ERR_ST1_WRBRRB_MASK  0x0000040000000000
+#define PI_ERR_ST1_WRBRRB_SHFT  42
+#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000
+#define PI_ERR_ST1_CRBSTAT_SHFT 43
+#define PI_ERR_ST1_MSGSRC_MASK  0xffe0000000000000
+#define PI_ERR_ST1_MSGSRC_SHFT  53
+
+/* Fields in the error stack */
+#define PI_ERR_STK_TYPE_MASK    0x0000000000000003
+#define PI_ERR_STK_TYPE_SHFT    0
+#define PI_ERR_STK_SUPPL_MASK   0x0000000000000038
+#define PI_ERR_STK_SUPPL_SHFT   3
+#define PI_ERR_STK_REQNUM_MASK  0x00000000000001c0
+#define PI_ERR_STK_REQNUM_SHFT  6
+#define PI_ERR_STK_CRBNUM_MASK  0x0000000000000e00
+#define PI_ERR_STK_CRBNUM_SHFT  9
+#define PI_ERR_STK_WRBRRB_MASK  0x0000000000001000
+#define PI_ERR_STK_WRBRRB_SHFT  12
+#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000
+#define PI_ERR_STK_CRBSTAT_SHFT 13
+#define PI_ERR_STK_CMD_MASK     0x000000007f800000
+#define PI_ERR_STK_CMD_SHFT     23
+#define PI_ERR_STK_ADDR_MASK    0xffffffff80000000
+#define PI_ERR_STK_ADDR_SHFT    31
+
+/* Error type in the error status or stack on Read CRBs */
+#define PI_ERR_RD_PRERR         1
+#define PI_ERR_RD_DERR          2
+#define PI_ERR_RD_TERR          3
+
+/* Error type in the error status or stack on Write CRBs */
+#define PI_ERR_WR_WERR          0
+#define PI_ERR_WR_PWERR         1
+#define PI_ERR_WR_TERR          3
+
+/* Read or Write CRB in error status or stack */
+#define PI_ERR_RRB      0
+#define PI_ERR_WRB      1
+#define PI_ERR_ANY_CRB  2
+
+/* Address masks in the error status and error stack are not the same */
+#define ERR_STK_ADDR_SHFT       7
+#define ERR_STAT0_ADDR_SHFT     3
+
+#define PI_MIN_STACK_SIZE 4096  /* For figuring out the size to set */
+#define PI_STACK_SIZE_SHFT      12      /* 4k */
+
+#define ERR_STACK_SIZE_BYTES(_sz) \
+       ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
+
+#ifndef __ASSEMBLY__
+/*
+ * format of error stack and error status registers.
+ */
+
+struct err_stack_format {
+        u64     sk_addr    : 33,   /* address */
+                sk_cmd     :  8,   /* message command */
+                sk_crb_sts : 10,   /* status from RRB or WRB */
+                sk_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+                sk_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+                sk_t5_req  :  3,   /* RRB T5 request number */
+                sk_suppl   :  3,   /* lowest 3 bit of supplemental */
+                sk_err_type:  3;   /* error type        */
+};
+
+typedef union pi_err_stack {
+        u64     pi_stk_word;
+        struct  err_stack_format pi_stk_fmt;
+} pi_err_stack_t;
+
+struct err_status0_format {
+        u64     s0_valid   :  1,   /* Valid */
+                s0_ovr_run :  1,   /* Overrun, spooled to memory */
+                s0_addr    : 37,   /* address */
+                s0_cmd     :  8,   /* message command */
+                s0_supl    : 11,   /* message supplemental field */
+                s0_t5_req  :  3,   /* RRB T5 request number */
+                s0_err_type:  3;   /* error type */
+};
+
+typedef union pi_err_stat0 {
+        u64     pi_stat0_word;
+        struct err_status0_format pi_stat0_fmt;
+} pi_err_stat0_t;
+
+struct err_status1_format {
+        u64     s1_src     : 11,   /* message source */
+                s1_crb_sts : 10,   /* status from RRB or WRB */
+                s1_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
+                s1_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
+                s1_inval_cnt:10,   /* signed invalidate counter RRB */
+                s1_to_cnt  :  8,   /* crb timeout counter */
+                s1_spl_cnt : 21;   /* number spooled to memory */
+};
+
+typedef union pi_err_stat1 {
+        u64     pi_stat1_word;
+        struct err_status1_format pi_stat1_fmt;
+} pi_err_stat1_t;
+
+typedef u64     rtc_time_t;
+
+#endif /* !__ASSEMBLY__ */
+
+
+/* Bits in PI_SYSAD_ERRCHK_EN */
+#define PI_SYSAD_ERRCHK_ECCGEN  0x01    /* Enable ECC generation            */
+#define PI_SYSAD_ERRCHK_QUALGEN 0x02    /* Enable data quality signal gen.  */
+#define PI_SYSAD_ERRCHK_SADP    0x04    /* Enable SysAD parity checking     */
+#define PI_SYSAD_ERRCHK_CMDP    0x08    /* Enable SysCmd parity checking    */
+#define PI_SYSAD_ERRCHK_STATE   0x10    /* Enable SysState parity checking  */
+#define PI_SYSAD_ERRCHK_QUAL    0x20    /* Enable data quality checking     */
+#define PI_SYSAD_CHECK_ALL      0x3f    /* Generate and check all signals.  */
+
+/* Interrupt pending bits on R10000 */
+
+#define HUB_IP_PEND0            0x0400
+#define HUB_IP_PEND1_CC         0x0800
+#define HUB_IP_RT               0x1000
+#define HUB_IP_PROF             0x2000
+#define HUB_IP_ERROR            0x4000
+#define HUB_IP_MASK             0x7c00
+
+/* PI_RT_LOCAL_CTRL mask and shift definitions */
+
+#define PRLC_USE_INT_SHFT       16
+#define PRLC_USE_INT_MASK       (UINT64_CAST 1 << 16)
+#define PRLC_USE_INT            (UINT64_CAST 1 << 16)
+#define PRLC_GCLK_SHFT          15
+#define PRLC_GCLK_MASK          (UINT64_CAST 1 << 15)
+#define PRLC_GCLK               (UINT64_CAST 1 << 15)
+#define PRLC_GCLK_COUNT_SHFT    8
+#define PRLC_GCLK_COUNT_MASK    (UINT64_CAST 0x7f << 8)
+#define PRLC_MAX_COUNT_SHFT     1
+#define PRLC_MAX_COUNT_MASK     (UINT64_CAST 0x7f << 1)
+#define PRLC_GCLK_EN_SHFT       0
+#define PRLC_GCLK_EN_MASK       (UINT64_CAST 1)
+#define PRLC_GCLK_EN            (UINT64_CAST 1)
+
+/* PI_RT_FILTER_CTRL mask and shift definitions */
+
+#if 0
+/*
+ * XXX - This register's definition has changed, but it's only implemented
+ * in Hub 2.
+ */
+#define PRFC_DROP_COUNT_SHFT    27
+#define PRFC_DROP_COUNT_MASK    (UINT64_CAST 0x3ff << 27)
+#define PRFC_DROP_CTR_SHFT      18
+#define PRFC_DROP_CTR_MASK      (UINT64_CAST 0x1ff << 18)
+#define PRFC_MASK_ENABLE_SHFT   10
+#define PRFC_MASK_ENABLE_MASK   (UINT64_CAST 0x7f << 10)
+#define PRFC_MASK_CTR_SHFT      2
+#define PRFC_MASK_CTR_MASK      (UINT64_CAST 0xff << 2)
+#define PRFC_OFFSET_SHFT        0
+#define PRFC_OFFSET_MASK        (UINT64_CAST 3)
+#endif /* 0 */
+
+
+/*
+ * Bits for NACK_CNT_A/B and NACK_CMP
+ */
+#define PI_NACK_CNT_EN_SHFT     20
+#define PI_NACK_CNT_EN_MASK     0x100000
+#define PI_NACK_CNT_MASK        0x0fffff
+#define PI_NACK_CNT_MAX         0x0fffff
+
+#endif /* _ASM_SN_SN0_HUBPI_H */
diff --git a/include/asm-mips/sn/sn0/ip27.h b/include/asm-mips/sn/sn0/ip27.h
new file mode 100644
index 000000000000..ade0e974dd78
--- /dev/null
+++ b/include/asm-mips/sn/sn0/ip27.h
@@ -0,0 +1,92 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/IP27.h>.
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999 by Ralf Baechle
+ */
+#ifndef _ASM_SN_SN0_IP27_H
+#define _ASM_SN_SN0_IP27_H
+
+#include <asm/mipsregs.h>
+
+/*
+ * Simple definitions for the masks which remove SW bits from pte.
+ */
+
+#define TLBLO_HWBITSHIFT        0               /* Shift value, for masking */
+
+#ifndef __ASSEMBLY__
+
+#define CAUSE_BERRINTR          IE_IRQ5
+
+#define ECCF_CACHE_ERR  0
+#define ECCF_TAGLO      1
+#define ECCF_ECC        2
+#define ECCF_ERROREPC   3
+#define ECCF_PADDR      4
+#define ECCF_SIZE       (5 * sizeof(long))
+
+#endif /* !__ASSEMBLY__ */
+
+#ifdef __ASSEMBLY__
+
+/*
+ * KL_GET_CPUNUM (similar to EV_GET_SPNUM for EVEREST platform) reads
+ * the processor number of the calling processor.  The proc parameters
+ * must be a register.
+ */
+#define KL_GET_CPUNUM(proc)                             \
+        dli     proc, LOCAL_HUB(0);                     \
+        ld      proc, PI_CPU_NUM(proc)
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * R10000 status register interrupt bit mask usage for IP27.
+ */
+#define SRB_SWTIMO      IE_SW0          /* 0x0100 */
+#define SRB_NET         IE_SW1          /* 0x0200 */
+#define SRB_DEV0        IE_IRQ0         /* 0x0400 */
+#define SRB_DEV1        IE_IRQ1         /* 0x0800 */
+#define SRB_TIMOCLK     IE_IRQ2         /* 0x1000 */
+#define SRB_PROFCLK     IE_IRQ3         /* 0x2000 */
+#define SRB_ERR         IE_IRQ4         /* 0x4000 */
+#define SRB_SCHEDCLK    IE_IRQ5         /* 0x8000 */
+
+#define SR_IBIT_HI      SRB_DEV0
+#define SR_IBIT_PROF    SRB_PROFCLK
+
+#define SRB_SWTIMO_IDX          0
+#define SRB_NET_IDX             1
+#define SRB_DEV0_IDX            2
+#define SRB_DEV1_IDX            3
+#define SRB_TIMOCLK_IDX         4
+#define SRB_PROFCLK_IDX         5
+#define SRB_ERR_IDX             6
+#define SRB_SCHEDCLK_IDX        7
+
+#define NUM_CAUSE_INTRS         8
+
+#define SCACHE_LINESIZE 128
+#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1)
+
+#include <asm/sn/addrs.h>
+
+#define LED_CYCLE_MASK  0x0f
+#define LED_CYCLE_SHFT  4
+
+#define SEND_NMI(_nasid, _slice)        \
+          REMOTE_HUB_S((_nasid),  (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
+
+/* Sanity hazzard ...  Below all the Origin hacks are following.  */
+
+#define SN00_BRIDGE             0x9200000008000000
+#define SN00I_BRIDGE0           0x920000000b000000
+#define SN00I_BRIDGE1           0x920000000e000000
+#define SN00I_BRIDGE2           0x920000000f000000
+
+#endif /* _ASM_SN_SN0_IP27_H */
diff --git a/include/asm-mips/sn/sn0/sn0_fru.h b/include/asm-mips/sn/sn0/sn0_fru.h
new file mode 100644
index 000000000000..82c6377c275a
--- /dev/null
+++ b/include/asm-mips/sn/sn0/sn0_fru.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Derived from IRIX <sys/SN/SN0/sn0_fru.h>
+ *
+ * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
+ */
+#ifndef _ASM_SN_SN0_SN0_FRU_H
+#define _ASM_SN_SN0_SN0_FRU_H
+
+#define MAX_DIMMS                       8        /* max # of dimm banks */
+#define MAX_PCIDEV                      8        /* max # of pci devices on a pci bus */
+
+typedef unsigned char confidence_t;
+
+typedef struct kf_mem_s {
+        confidence_t km_confidence; /* confidence level that the memory is bad
+                                     * is this necessary ?
+                                     */
+        confidence_t km_dimm[MAX_DIMMS];
+                                    /* confidence level that dimm[i] is bad
+                                     *I think this is the right number
+                                     */
+
+} kf_mem_t;
+
+typedef struct kf_cpu_s {
+        confidence_t    kc_confidence; /* confidence level that cpu is bad */
+        confidence_t    kc_icache; /* confidence level that instr. cache is bad */
+        confidence_t    kc_dcache; /* confidence level that data   cache is bad */
+        confidence_t    kc_scache; /* confidence level that sec.   cache is bad */
+        confidence_t    kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
+} kf_cpu_t;
+
+typedef struct kf_pci_bus_s {
+        confidence_t    kpb_belief;     /* confidence level  that the  pci bus is bad */
+        confidence_t    kpb_pcidev_belief[MAX_PCIDEV];
+                                        /* confidence level that the pci dev is bad */
+} kf_pci_bus_t;
+
+#endif /* _ASM_SN_SN0_SN0_FRU_H */