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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-mips/sibyte
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-mips/sibyte')
-rw-r--r--include/asm-mips/sibyte/board.h69
-rw-r--r--include/asm-mips/sibyte/carmel.h60
-rw-r--r--include/asm-mips/sibyte/sb1250.h63
-rw-r--r--include/asm-mips/sibyte/sb1250_defs.h242
-rw-r--r--include/asm-mips/sibyte/sb1250_dma.h594
-rw-r--r--include/asm-mips/sibyte/sb1250_genbus.h276
-rw-r--r--include/asm-mips/sibyte/sb1250_int.h247
-rw-r--r--include/asm-mips/sibyte/sb1250_l2c.h128
-rw-r--r--include/asm-mips/sibyte/sb1250_ldt.h425
-rw-r--r--include/asm-mips/sibyte/sb1250_mac.h643
-rw-r--r--include/asm-mips/sibyte/sb1250_mc.h548
-rw-r--r--include/asm-mips/sibyte/sb1250_regs.h836
-rw-r--r--include/asm-mips/sibyte/sb1250_scd.h582
-rw-r--r--include/asm-mips/sibyte/sb1250_smbus.h170
-rw-r--r--include/asm-mips/sibyte/sb1250_syncser.h148
-rw-r--r--include/asm-mips/sibyte/sb1250_uart.h354
-rw-r--r--include/asm-mips/sibyte/sentosa.h41
-rw-r--r--include/asm-mips/sibyte/swarm.h71
-rw-r--r--include/asm-mips/sibyte/trace_prof.h110
19 files changed, 5607 insertions, 0 deletions
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
new file mode 100644
index 000000000000..d7b11b6c7c32
--- /dev/null
+++ b/include/asm-mips/sibyte/board.h
@@ -0,0 +1,69 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#ifndef _SIBYTE_BOARD_H
20#define _SIBYTE_BOARD_H
21
22#include <linux/config.h>
23
24#ifdef CONFIG_SIBYTE_BOARD
25
26#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_PTSWARM) || \
27 defined(CONFIG_SIBYTE_CRHONE) || defined(CONFIG_SIBYTE_CRHINE) || \
28 defined(CONFIG_SIBYTE_LITTLESUR)
29#include <asm/sibyte/swarm.h>
30#endif
31
32#if defined(CONFIG_SIBYTE_SENTOSA) || defined(CONFIG_SIBYTE_RHONE)
33#include <asm/sibyte/sentosa.h>
34#endif
35
36#ifdef CONFIG_SIBYTE_CARMEL
37#include <asm/sibyte/carmel.h>
38#endif
39
40#ifdef __ASSEMBLY__
41
42#ifdef LEDS_PHYS
43#define setleds(t0,t1,c0,c1,c2,c3) \
44 li t0, (LEDS_PHYS|0xa0000000); \
45 li t1, c0; \
46 sb t1, 0x18(t0); \
47 li t1, c1; \
48 sb t1, 0x10(t0); \
49 li t1, c2; \
50 sb t1, 0x08(t0); \
51 li t1, c3; \
52 sb t1, 0x00(t0)
53#else
54#define setleds(t0,t1,c0,c1,c2,c3)
55#endif /* LEDS_PHYS */
56
57#else
58
59#ifdef LEDS_PHYS
60extern void setleds(char *str);
61#else
62#define setleds(s) do { } while (0)
63#endif /* LEDS_PHYS */
64
65#endif /* __ASSEMBLY__ */
66
67#endif /* CONFIG_SIBYTE_BOARD */
68
69#endif /* _SIBYTE_BOARD_H */
diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h
new file mode 100644
index 000000000000..7ac5da13ce8a
--- /dev/null
+++ b/include/asm-mips/sibyte/carmel.h
@@ -0,0 +1,60 @@
1/*
2 * Copyright (C) 2002 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#ifndef __ASM_SIBYTE_CARMEL_H
19#define __ASM_SIBYTE_CARMEL_H
20
21#include <linux/config.h>
22
23#include <asm/sibyte/sb1250.h>
24#include <asm/sibyte/sb1250_int.h>
25
26#define SIBYTE_BOARD_NAME "Carmel"
27
28#define GPIO_PHY_INTERRUPT 2
29#define GPIO_NONMASKABLE_INT 3
30#define GPIO_CF_INSERTED 6
31#define GPIO_MONTEREY_RESET 7
32#define GPIO_QUADUART_INT 8
33#define GPIO_CF_INT 9
34#define GPIO_FPGA_CCLK 10
35#define GPIO_FPGA_DOUT 11
36#define GPIO_FPGA_DIN 12
37#define GPIO_FPGA_PGM 13
38#define GPIO_FPGA_DONE 14
39#define GPIO_FPGA_INIT 15
40
41#define LEDS_CS 2
42#define LEDS_PHYS 0x100C0000
43#define MLEDS_CS 3
44#define MLEDS_PHYS 0x100A0000
45#define UART_CS 4
46#define UART_PHYS 0x100D0000
47#define ARAVALI_CS 5
48#define ARAVALI_PHYS 0x11000000
49#define IDE_CS 6
50#define IDE_PHYS 0x100B0000
51#define ARAVALI2_CS 7
52#define ARAVALI2_PHYS 0x100E0000
53
54#if defined(CONFIG_SIBYTE_CARMEL)
55#define K_GPIO_GB_IDE 9
56#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE)
57#endif
58
59
60#endif /* __ASM_SIBYTE_CARMEL_H */
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h
new file mode 100644
index 000000000000..d62da4e2dd36
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250.h
@@ -0,0 +1,63 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#ifndef _ASM_SIBYTE_SB1250_H
20#define _ASM_SIBYTE_SB1250_H
21
22/*
23 * yymmddpp: year, month, day, patch.
24 * should sync with Makefile EXTRAVERSION
25 */
26#define SIBYTE_RELEASE 0x02111403
27
28#define SB1250_NR_IRQS 64
29
30#define SB1250_DUART_MINOR_BASE 64
31
32#ifndef __ASSEMBLY__
33
34#include <asm/addrspace.h>
35
36/* For revision/pass information */
37#include <asm/sibyte/sb1250_scd.h>
38extern unsigned int sb1_pass;
39extern unsigned int soc_pass;
40extern unsigned int soc_type;
41extern unsigned int periph_rev;
42extern unsigned int zbbus_mhz;
43
44extern void sb1250_time_init(void);
45extern unsigned long sb1250_gettimeoffset(void);
46extern void sb1250_mask_irq(int cpu, int irq);
47extern void sb1250_unmask_irq(int cpu, int irq);
48extern void sb1250_smp_finish(void);
49extern void prom_printf(char *fmt, ...);
50
51#define AT_spin \
52 __asm__ __volatile__ ( \
53 ".set noat\n" \
54 "li $at, 0\n" \
55 "1: beqz $at, 1b\n" \
56 ".set at\n" \
57 )
58
59#endif
60
61#define IOADDR(a) (IO_BASE + (a))
62
63#endif
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
new file mode 100644
index 000000000000..96088fb074a4
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_defs.h
@@ -0,0 +1,242 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * Global constants and macros File: sb1250_defs.h
5 *
6 * This file contains macros and definitions used by the other
7 * include files.
8 *
9 * SB1250 specification level: User's manual 1/02/02
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34#ifndef _SB1250_DEFS_H
35#define _SB1250_DEFS_H
36
37/*
38 * These headers require ANSI C89 string concatenation, and GCC or other
39 * 'long long' (64-bit integer) support.
40 */
41#if !defined(__STDC__) && !defined(_MSC_VER)
42#error SiByte headers require ANSI C89 support
43#endif
44
45
46/* *********************************************************************
47 * Macros for feature tests, used to enable include file features
48 * for chip features only present in certain chip revisions.
49 *
50 * SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
51 * which is to be exposed by the headers. If undefined, it defaults to
52 * "all features."
53 *
54 * Use like:
55 *
56 * #define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_112x_PASS1
57 *
58 * Generate defines only for that revision of chip.
59 *
60 * #if SIBYTE_HDR_FEATURE(chip,pass)
61 *
62 * True if header features for that revision or later of
63 * that particular chip type are enabled in SIBYTE_HDR_FEATURES.
64 * (Use this to bracket #defines for features present in a given
65 * revision and later.)
66 *
67 * Note that there is no implied ordering between chip types.
68 *
69 * Note also that 'chip' and 'pass' must textually exactly
70 * match the defines below. So, for example,
71 * SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
72 * SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
73 *
74 * #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
75 *
76 * Same as SIBYTE_HDR_FEATURE, but true for the named revision
77 * and earlier revisions of the named chip type.
78 *
79 * #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)
80 *
81 * Same as SIBYTE_HDR_FEATURE, but only true for the named
82 * revision of the named chip type. (Note that this CANNOT
83 * be used to verify that you're compiling only for that
84 * particular chip/revision. It will be true any time this
85 * chip/revision is included in SIBYTE_HDR_FEATURES.)
86 *
87 * #if SIBYTE_HDR_FEATURE_CHIP(chip)
88 *
89 * True if header features for (any revision of) that chip type
90 * are enabled in SIBYTE_HDR_FEATURES. (Use this to bracket
91 * #defines for features specific to a given chip type.)
92 *
93 * Mask values currently include room for additional revisions of each
94 * chip type, but can be renumbered at will. Note that they MUST fit
95 * into 31 bits and may not include C type constructs, for safe use in
96 * CPP conditionals. Bit positions within chip types DO indicate
97 * ordering, so be careful when adding support for new minor revs.
98 ********************************************************************* */
99
100#define SIBYTE_HDR_FMASK_1250_ALL 0x00000ff
101#define SIBYTE_HDR_FMASK_1250_PASS1 0x0000001
102#define SIBYTE_HDR_FMASK_1250_PASS2 0x0000002
103#define SIBYTE_HDR_FMASK_1250_PASS3 0x0000004
104
105#define SIBYTE_HDR_FMASK_112x_ALL 0x0000f00
106#define SIBYTE_HDR_FMASK_112x_PASS1 0x0000100
107
108/* Bit mask for chip/revision. (use _ALL for all revisions of a chip). */
109#define SIBYTE_HDR_FMASK(chip, pass) \
110 (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
111#define SIBYTE_HDR_FMASK_ALLREVS(chip) \
112 (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
113
114#define SIBYTE_HDR_FMASK_ALL \
115 (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
116
117#ifndef SIBYTE_HDR_FEATURES
118#define SIBYTE_HDR_FEATURES SIBYTE_HDR_FMASK_ALL
119#endif
120
121
122/* Bit mask for revisions of chip exclusively before the named revision. */
123#define SIBYTE_HDR_FMASK_BEFORE(chip, pass) \
124 ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
125
126/* Bit mask for revisions of chip exclusively after the named revision. */
127#define SIBYTE_HDR_FMASK_AFTER(chip, pass) \
128 (~(SIBYTE_HDR_FMASK(chip, pass) \
129 | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
130
131
132/* True if header features enabled for (any revision of) that chip type. */
133#define SIBYTE_HDR_FEATURE_CHIP(chip) \
134 (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
135
136/* True if header features enabled for that rev or later, inclusive. */
137#define SIBYTE_HDR_FEATURE(chip, pass) \
138 (!! ((SIBYTE_HDR_FMASK(chip, pass) \
139 | SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES))
140
141/* True if header features enabled for exactly that rev. */
142#define SIBYTE_HDR_FEATURE_EXACT(chip, pass) \
143 (!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES))
144
145/* True if header features enabled for that rev or before, inclusive. */
146#define SIBYTE_HDR_FEATURE_UP_TO(chip, pass) \
147 (!! ((SIBYTE_HDR_FMASK(chip, pass) \
148 | SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES))
149
150
151/* *********************************************************************
152 * Naming schemes for constants in these files:
153 *
154 * M_xxx MASK constant (identifies bits in a register).
155 * For multi-bit fields, all bits in the field will
156 * be set.
157 *
158 * K_xxx "Code" constant (value for data in a multi-bit
159 * field). The value is right justified.
160 *
161 * V_xxx "Value" constant. This is the same as the
162 * corresponding "K_xxx" constant, except it is
163 * shifted to the correct position in the register.
164 *
165 * S_xxx SHIFT constant. This is the number of bits that
166 * a field value (code) needs to be shifted
167 * (towards the left) to put the value in the right
168 * position for the register.
169 *
170 * A_xxx ADDRESS constant. This will be a physical
171 * address. Use the PHYS_TO_K1 macro to generate
172 * a K1SEG address.
173 *
174 * R_xxx RELATIVE offset constant. This is an offset from
175 * an A_xxx constant (usually the first register in
176 * a group).
177 *
178 * G_xxx(X) GET value. This macro obtains a multi-bit field
179 * from a register, masks it, and shifts it to
180 * the bottom of the register (retrieving a K_xxx
181 * value, for example).
182 *
183 * V_xxx(X) VALUE. This macro computes the value of a
184 * K_xxx constant shifted to the correct position
185 * in the register.
186 ********************************************************************* */
187
188
189
190
191/*
192 * Cast to 64-bit number. Presumably the syntax is different in
193 * assembly language.
194 *
195 * Note: you'll need to define uint32_t and uint64_t in your headers.
196 */
197
198#if !defined(__ASSEMBLER__)
199#define _SB_MAKE64(x) ((uint64_t)(x))
200#define _SB_MAKE32(x) ((uint32_t)(x))
201#else
202#define _SB_MAKE64(x) (x)
203#define _SB_MAKE32(x) (x)
204#endif
205
206
207/*
208 * Make a mask for 1 bit at position 'n'
209 */
210
211#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
212#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
213
214/*
215 * Make a mask for 'v' bits at position 'n'
216 */
217
218#define _SB_MAKEMASK(v,n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
219#define _SB_MAKEMASK_32(v,n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
220
221/*
222 * Make a value at 'v' at bit position 'n'
223 */
224
225#define _SB_MAKEVALUE(v,n) (_SB_MAKE64(v) << _SB_MAKE64(n))
226#define _SB_MAKEVALUE_32(v,n) (_SB_MAKE32(v) << _SB_MAKE32(n))
227
228#define _SB_GETVALUE(v,n,m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
229#define _SB_GETVALUE_32(v,n,m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
230
231/*
232 * Macros to read/write on-chip registers
233 * XXX should we do the PHYS_TO_K1 here?
234 */
235
236
237#if defined(__mips64) && !defined(__ASSEMBLER__)
238#define SBWRITECSR(csr,val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
239#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
240#endif /* __ASSEMBLER__ */
241
242#endif
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
new file mode 100644
index 000000000000..f1b08d32338d
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_dma.h
@@ -0,0 +1,594 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * DMA definitions File: sb1250_dma.h
5 *
6 * This module contains constants and macros useful for
7 * programming the SB1250's DMA controllers, both the data mover
8 * and the Ethernet DMA.
9 *
10 * SB1250 specification level: User's manual 1/02/02
11 *
12 * Author: Mitch Lichtenberg
13 *
14 *********************************************************************
15 *
16 * Copyright 2000,2001,2002,2003
17 * Broadcom Corporation. All rights reserved.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 ********************************************************************* */
34
35
36#ifndef _SB1250_DMA_H
37#define _SB1250_DMA_H
38
39
40#include "sb1250_defs.h"
41
42/* *********************************************************************
43 * DMA Registers
44 ********************************************************************* */
45
46/*
47 * Ethernet and Serial DMA Configuration Register 0 (Table 7-4)
48 * Registers: DMA_CONFIG0_MAC_x_RX_CH_0
49 * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
50 * Registers: DMA_CONFIG0_SER_x_RX
51 * Registers: DMA_CONFIG0_SER_x_TX
52 */
53
54
55#define M_DMA_DROP _SB_MAKEMASK1(0)
56
57#define M_DMA_CHAIN_SEL _SB_MAKEMASK1(1)
58#define M_DMA_RESERVED1 _SB_MAKEMASK1(2)
59
60#define S_DMA_DESC_TYPE _SB_MAKE64(1)
61#define M_DMA_DESC_TYPE _SB_MAKE64(2,S_DMA_DESC_TYPE)
62#define V_DMA_DESC_TYPE(x) _SB_MAKEVALUE(x,S_DMA_DESC_TYPE)
63#define G_DMA_DESC_TYPE(x) _SB_GETVALUE(x,S_DMA_DESC_TYPE,M_DMA_DESC_TYPE)
64
65#define K_DMA_DESC_TYPE_RING_AL 0
66#define K_DMA_DESC_TYPE_CHAIN_AL 1
67
68#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
69#define K_DMA_DESC_TYPE_RING_UAL_WI 2
70#define K_DMA_DESC_TYPE_RING_UAL_RMW 3
71#endif /* 1250 PASS3 || 112x PASS1 */
72
73#define M_DMA_EOP_INT_EN _SB_MAKEMASK1(3)
74#define M_DMA_HWM_INT_EN _SB_MAKEMASK1(4)
75#define M_DMA_LWM_INT_EN _SB_MAKEMASK1(5)
76#define M_DMA_TBX_EN _SB_MAKEMASK1(6)
77#define M_DMA_TDX_EN _SB_MAKEMASK1(7)
78
79#define S_DMA_INT_PKTCNT _SB_MAKE64(8)
80#define M_DMA_INT_PKTCNT _SB_MAKEMASK(8,S_DMA_INT_PKTCNT)
81#define V_DMA_INT_PKTCNT(x) _SB_MAKEVALUE(x,S_DMA_INT_PKTCNT)
82#define G_DMA_INT_PKTCNT(x) _SB_GETVALUE(x,S_DMA_INT_PKTCNT,M_DMA_INT_PKTCNT)
83
84#define S_DMA_RINGSZ _SB_MAKE64(16)
85#define M_DMA_RINGSZ _SB_MAKEMASK(16,S_DMA_RINGSZ)
86#define V_DMA_RINGSZ(x) _SB_MAKEVALUE(x,S_DMA_RINGSZ)
87#define G_DMA_RINGSZ(x) _SB_GETVALUE(x,S_DMA_RINGSZ,M_DMA_RINGSZ)
88
89#define S_DMA_HIGH_WATERMARK _SB_MAKE64(32)
90#define M_DMA_HIGH_WATERMARK _SB_MAKEMASK(16,S_DMA_HIGH_WATERMARK)
91#define V_DMA_HIGH_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_HIGH_WATERMARK)
92#define G_DMA_HIGH_WATERMARK(x) _SB_GETVALUE(x,S_DMA_HIGH_WATERMARK,M_DMA_HIGH_WATERMARK)
93
94#define S_DMA_LOW_WATERMARK _SB_MAKE64(48)
95#define M_DMA_LOW_WATERMARK _SB_MAKEMASK(16,S_DMA_LOW_WATERMARK)
96#define V_DMA_LOW_WATERMARK(x) _SB_MAKEVALUE(x,S_DMA_LOW_WATERMARK)
97#define G_DMA_LOW_WATERMARK(x) _SB_GETVALUE(x,S_DMA_LOW_WATERMARK,M_DMA_LOW_WATERMARK)
98
99/*
100 * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
101 * Registers: DMA_CONFIG1_MAC_x_RX_CH_0
102 * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
103 * Registers: DMA_CONFIG1_SER_x_RX
104 * Registers: DMA_CONFIG1_SER_x_TX
105 */
106
107#define M_DMA_HDR_CF_EN _SB_MAKEMASK1(0)
108#define M_DMA_ASIC_XFR_EN _SB_MAKEMASK1(1)
109#define M_DMA_PRE_ADDR_EN _SB_MAKEMASK1(2)
110#define M_DMA_FLOW_CTL_EN _SB_MAKEMASK1(3)
111#define M_DMA_NO_DSCR_UPDT _SB_MAKEMASK1(4)
112#define M_DMA_L2CA _SB_MAKEMASK1(5)
113
114#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
115#define M_DMA_RX_XTRA_STATUS _SB_MAKEMASK1(6)
116#define M_DMA_TX_CPU_PAUSE _SB_MAKEMASK1(6)
117#define M_DMA_TX_FC_PAUSE_EN _SB_MAKEMASK1(7)
118#endif /* 1250 PASS3 || 112x PASS1 */
119
120#define M_DMA_MBZ1 _SB_MAKEMASK(6,15)
121
122#define S_DMA_HDR_SIZE _SB_MAKE64(21)
123#define M_DMA_HDR_SIZE _SB_MAKEMASK(9,S_DMA_HDR_SIZE)
124#define V_DMA_HDR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_HDR_SIZE)
125#define G_DMA_HDR_SIZE(x) _SB_GETVALUE(x,S_DMA_HDR_SIZE,M_DMA_HDR_SIZE)
126
127#define M_DMA_MBZ2 _SB_MAKEMASK(5,32)
128
129#define S_DMA_ASICXFR_SIZE _SB_MAKE64(37)
130#define M_DMA_ASICXFR_SIZE _SB_MAKEMASK(9,S_DMA_ASICXFR_SIZE)
131#define V_DMA_ASICXFR_SIZE(x) _SB_MAKEVALUE(x,S_DMA_ASICXFR_SIZE)
132#define G_DMA_ASICXFR_SIZE(x) _SB_GETVALUE(x,S_DMA_ASICXFR_SIZE,M_DMA_ASICXFR_SIZE)
133
134#define S_DMA_INT_TIMEOUT _SB_MAKE64(48)
135#define M_DMA_INT_TIMEOUT _SB_MAKEMASK(16,S_DMA_INT_TIMEOUT)
136#define V_DMA_INT_TIMEOUT(x) _SB_MAKEVALUE(x,S_DMA_INT_TIMEOUT)
137#define G_DMA_INT_TIMEOUT(x) _SB_GETVALUE(x,S_DMA_INT_TIMEOUT,M_DMA_INT_TIMEOUT)
138
139/*
140 * Ethernet and Serial DMA Descriptor base address (Table 7-6)
141 */
142
143#define M_DMA_DSCRBASE_MBZ _SB_MAKEMASK(4,0)
144
145
146/*
147 * ASIC Mode Base Address (Table 7-7)
148 */
149
150#define M_DMA_ASIC_BASE_MBZ _SB_MAKEMASK(20,0)
151
152/*
153 * DMA Descriptor Count Registers (Table 7-8)
154 */
155
156/* No bitfields */
157
158
159/*
160 * Current Descriptor Address Register (Table 7-11)
161 */
162
163#define S_DMA_CURDSCR_ADDR _SB_MAKE64(0)
164#define M_DMA_CURDSCR_ADDR _SB_MAKEMASK(40,S_DMA_CURDSCR_ADDR)
165#define S_DMA_CURDSCR_COUNT _SB_MAKE64(40)
166#define M_DMA_CURDSCR_COUNT _SB_MAKEMASK(16,S_DMA_CURDSCR_COUNT)
167
168#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
169#define M_DMA_TX_CH_PAUSE_ON _SB_MAKEMASK1(56)
170#endif /* 1250 PASS3 || 112x PASS1 */
171
172/*
173 * Receive Packet Drop Registers
174 */
175#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
176#define S_DMA_OODLOST_RX _SB_MAKE64(0)
177#define M_DMA_OODLOST_RX _SB_MAKEMASK(16,S_DMA_OODLOST_RX)
178#define G_DMA_OODLOST_RX(x) _SB_GETVALUE(x,S_DMA_OODLOST_RX,M_DMA_OODLOST_RX)
179
180#define S_DMA_EOP_COUNT_RX _SB_MAKE64(16)
181#define M_DMA_EOP_COUNT_RX _SB_MAKEMASK(8,S_DMA_EOP_COUNT_RX)
182#define G_DMA_EOP_COUNT_RX(x) _SB_GETVALUE(x,S_DMA_EOP_COUNT_RX,M_DMA_EOP_COUNT_RX)
183#endif /* 1250 PASS3 || 112x PASS1 */
184
185/* *********************************************************************
186 * DMA Descriptors
187 ********************************************************************* */
188
189/*
190 * Descriptor doubleword "A" (Table 7-12)
191 */
192
193#define S_DMA_DSCRA_OFFSET _SB_MAKE64(0)
194#define M_DMA_DSCRA_OFFSET _SB_MAKEMASK(5,S_DMA_DSCRA_OFFSET)
195#define V_DMA_DSCRA_OFFSET(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_OFFSET)
196#define G_DMA_DSCRA_OFFSET(x) _SB_GETVALUE(x,S_DMA_DSCRA_OFFSET,M_DMA_DSCRA_OFFSET)
197
198/* Note: Don't shift the address over, just mask it with the mask below */
199#define S_DMA_DSCRA_A_ADDR _SB_MAKE64(5)
200#define M_DMA_DSCRA_A_ADDR _SB_MAKEMASK(35,S_DMA_DSCRA_A_ADDR)
201
202#define M_DMA_DSCRA_A_ADDR_OFFSET (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
203
204#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
205#define S_DMA_DSCRA_A_ADDR_UA _SB_MAKE64(0)
206#define M_DMA_DSCRA_A_ADDR_UA _SB_MAKEMASK(40,S_DMA_DSCRA_A_ADDR_UA)
207#endif /* 1250 PASS3 || 112x PASS1 */
208
209#define S_DMA_DSCRA_A_SIZE _SB_MAKE64(40)
210#define M_DMA_DSCRA_A_SIZE _SB_MAKEMASK(9,S_DMA_DSCRA_A_SIZE)
211#define V_DMA_DSCRA_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_A_SIZE)
212#define G_DMA_DSCRA_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRA_A_SIZE,M_DMA_DSCRA_A_SIZE)
213
214#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
215#define S_DMA_DSCRA_DSCR_CNT _SB_MAKE64(40)
216#define M_DMA_DSCRA_DSCR_CNT _SB_MAKEMASK(8,S_DMA_DSCRA_DSCR_CNT)
217#define G_DMA_DSCRA_DSCR_CNT(x) _SB_GETVALUE(x,S_DMA_DSCRA_DSCR_CNT,M_DMA_DSCRA_DSCR_CNT)
218#endif /* 1250 PASS3 || 112x PASS1 */
219
220#define M_DMA_DSCRA_INTERRUPT _SB_MAKEMASK1(49)
221#define M_DMA_DSCRA_OFFSETB _SB_MAKEMASK1(50)
222
223#define S_DMA_DSCRA_STATUS _SB_MAKE64(51)
224#define M_DMA_DSCRA_STATUS _SB_MAKEMASK(13,S_DMA_DSCRA_STATUS)
225#define V_DMA_DSCRA_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRA_STATUS)
226#define G_DMA_DSCRA_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRA_STATUS,M_DMA_DSCRA_STATUS)
227
228/*
229 * Descriptor doubleword "B" (Table 7-13)
230 */
231
232
233#define S_DMA_DSCRB_OPTIONS _SB_MAKE64(0)
234#define M_DMA_DSCRB_OPTIONS _SB_MAKEMASK(4,S_DMA_DSCRB_OPTIONS)
235#define V_DMA_DSCRB_OPTIONS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_OPTIONS)
236#define G_DMA_DSCRB_OPTIONS(x) _SB_GETVALUE(x,S_DMA_DSCRB_OPTIONS,M_DMA_DSCRB_OPTIONS)
237
238#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
239#define S_DMA_DSCRB_A_SIZE _SB_MAKE64(8)
240#define M_DMA_DSCRB_A_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_A_SIZE)
241#define V_DMA_DSCRB_A_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_A_SIZE)
242#define G_DMA_DSCRB_A_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_A_SIZE,M_DMA_DSCRB_A_SIZE)
243#endif /* 1250 PASS3 || 112x PASS1 */
244
245#define R_DMA_DSCRB_ADDR _SB_MAKE64(0x10)
246
247/* Note: Don't shift the address over, just mask it with the mask below */
248#define S_DMA_DSCRB_B_ADDR _SB_MAKE64(5)
249#define M_DMA_DSCRB_B_ADDR _SB_MAKEMASK(35,S_DMA_DSCRB_B_ADDR)
250
251#define S_DMA_DSCRB_B_SIZE _SB_MAKE64(40)
252#define M_DMA_DSCRB_B_SIZE _SB_MAKEMASK(9,S_DMA_DSCRB_B_SIZE)
253#define V_DMA_DSCRB_B_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_B_SIZE)
254#define G_DMA_DSCRB_B_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_B_SIZE,M_DMA_DSCRB_B_SIZE)
255
256#define M_DMA_DSCRB_B_VALID _SB_MAKEMASK1(49)
257
258#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
259#define S_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKE64(48)
260#define M_DMA_DSCRB_PKT_SIZE_MSB _SB_MAKEMASK(2,S_DMA_DSCRB_PKT_SIZE_MSB)
261#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB)
262#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE_MSB,M_DMA_DSCRB_PKT_SIZE_MSB)
263#endif /* 1250 PASS3 || 112x PASS1 */
264
265#define S_DMA_DSCRB_PKT_SIZE _SB_MAKE64(50)
266#define M_DMA_DSCRB_PKT_SIZE _SB_MAKEMASK(14,S_DMA_DSCRB_PKT_SIZE)
267#define V_DMA_DSCRB_PKT_SIZE(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_PKT_SIZE)
268#define G_DMA_DSCRB_PKT_SIZE(x) _SB_GETVALUE(x,S_DMA_DSCRB_PKT_SIZE,M_DMA_DSCRB_PKT_SIZE)
269
270/*
271 * from pass2 some bits in dscr_b are also used for rx status
272 */
273#define S_DMA_DSCRB_STATUS _SB_MAKE64(0)
274#define M_DMA_DSCRB_STATUS _SB_MAKEMASK(1,S_DMA_DSCRB_STATUS)
275#define V_DMA_DSCRB_STATUS(x) _SB_MAKEVALUE(x,S_DMA_DSCRB_STATUS)
276#define G_DMA_DSCRB_STATUS(x) _SB_GETVALUE(x,S_DMA_DSCRB_STATUS,M_DMA_DSCRB_STATUS)
277
278/*
279 * Ethernet Descriptor Status Bits (Table 7-15)
280 */
281
282#define M_DMA_ETHRX_BADIP4CS _SB_MAKEMASK1(51)
283#define M_DMA_ETHRX_DSCRERR _SB_MAKEMASK1(52)
284
285#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
286/* Note: BADTCPCS is actually in DSCR_B options field */
287#define M_DMA_ETHRX_BADTCPCS _SB_MAKEMASK1(0)
288#endif /* 1250 PASS2 || 112x PASS1 */
289
290#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
291#define M_DMA_ETH_VLAN_FLAG _SB_MAKEMASK1(1)
292#define M_DMA_ETH_CRC_FLAG _SB_MAKEMASK1(2)
293#endif /* 1250 PASS3 || 112x PASS1 */
294
295#define S_DMA_ETHRX_RXCH 53
296#define M_DMA_ETHRX_RXCH _SB_MAKEMASK(2,S_DMA_ETHRX_RXCH)
297#define V_DMA_ETHRX_RXCH(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_RXCH)
298#define G_DMA_ETHRX_RXCH(x) _SB_GETVALUE(x,S_DMA_ETHRX_RXCH,M_DMA_ETHRX_RXCH)
299
300#define S_DMA_ETHRX_PKTTYPE 55
301#define M_DMA_ETHRX_PKTTYPE _SB_MAKEMASK(3,S_DMA_ETHRX_PKTTYPE)
302#define V_DMA_ETHRX_PKTTYPE(x) _SB_MAKEVALUE(x,S_DMA_ETHRX_PKTTYPE)
303#define G_DMA_ETHRX_PKTTYPE(x) _SB_GETVALUE(x,S_DMA_ETHRX_PKTTYPE,M_DMA_ETHRX_PKTTYPE)
304
305#define K_DMA_ETHRX_PKTTYPE_IPV4 0
306#define K_DMA_ETHRX_PKTTYPE_ARPV4 1
307#define K_DMA_ETHRX_PKTTYPE_802 2
308#define K_DMA_ETHRX_PKTTYPE_OTHER 3
309#define K_DMA_ETHRX_PKTTYPE_USER0 4
310#define K_DMA_ETHRX_PKTTYPE_USER1 5
311#define K_DMA_ETHRX_PKTTYPE_USER2 6
312#define K_DMA_ETHRX_PKTTYPE_USER3 7
313
314#define M_DMA_ETHRX_MATCH_HASH _SB_MAKEMASK1(58)
315#define M_DMA_ETHRX_MATCH_EXACT _SB_MAKEMASK1(59)
316#define M_DMA_ETHRX_BCAST _SB_MAKEMASK1(60)
317#define M_DMA_ETHRX_MCAST _SB_MAKEMASK1(61)
318#define M_DMA_ETHRX_BAD _SB_MAKEMASK1(62)
319#define M_DMA_ETHRX_SOP _SB_MAKEMASK1(63)
320
321/*
322 * Ethernet Transmit Status Bits (Table 7-16)
323 */
324
325#define M_DMA_ETHTX_SOP _SB_MAKEMASK1(63)
326
327/*
328 * Ethernet Transmit Options (Table 7-17)
329 */
330
331#define K_DMA_ETHTX_NOTSOP _SB_MAKE64(0x00)
332#define K_DMA_ETHTX_APPENDCRC _SB_MAKE64(0x01)
333#define K_DMA_ETHTX_REPLACECRC _SB_MAKE64(0x02)
334#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
335#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
336#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
337#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
338#define K_DMA_ETHTX_NOMODS _SB_MAKE64(0x07)
339#define K_DMA_ETHTX_RESERVED1 _SB_MAKE64(0x08)
340#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
341#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
342#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
343#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
344#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
345#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
346#define K_DMA_ETHTX_RESERVED2 _SB_MAKE64(0x0F)
347
348/*
349 * Serial Receive Options (Table 7-18)
350 */
351#define M_DMA_SERRX_CRC_ERROR _SB_MAKEMASK1(56)
352#define M_DMA_SERRX_ABORT _SB_MAKEMASK1(57)
353#define M_DMA_SERRX_OCTET_ERROR _SB_MAKEMASK1(58)
354#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
355#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
356#define M_DMA_SERRX_OVERRUN_ERROR _SB_MAKEMASK1(61)
357#define M_DMA_SERRX_GOOD _SB_MAKEMASK1(62)
358#define M_DMA_SERRX_SOP _SB_MAKEMASK1(63)
359
360/*
361 * Serial Transmit Status Bits (Table 7-20)
362 */
363
364#define M_DMA_SERTX_FLAG _SB_MAKEMASK1(63)
365
366/*
367 * Serial Transmit Options (Table 7-21)
368 */
369
370#define K_DMA_SERTX_RESERVED _SB_MAKEMASK1(0)
371#define K_DMA_SERTX_APPENDCRC _SB_MAKEMASK1(1)
372#define K_DMA_SERTX_APPENDPAD _SB_MAKEMASK1(2)
373#define K_DMA_SERTX_ABORT _SB_MAKEMASK1(3)
374
375
376/* *********************************************************************
377 * Data Mover Registers
378 ********************************************************************* */
379
380/*
381 * Data Mover Descriptor Base Address Register (Table 7-22)
382 * Register: DM_DSCR_BASE_0
383 * Register: DM_DSCR_BASE_1
384 * Register: DM_DSCR_BASE_2
385 * Register: DM_DSCR_BASE_3
386 */
387
388#define M_DM_DSCR_BASE_MBZ _SB_MAKEMASK(4,0)
389
390/* Note: Just mask the base address and then OR it in. */
391#define S_DM_DSCR_BASE_ADDR _SB_MAKE64(4)
392#define M_DM_DSCR_BASE_ADDR _SB_MAKEMASK(36,S_DM_DSCR_BASE_ADDR)
393
394#define S_DM_DSCR_BASE_RINGSZ _SB_MAKE64(40)
395#define M_DM_DSCR_BASE_RINGSZ _SB_MAKEMASK(16,S_DM_DSCR_BASE_RINGSZ)
396#define V_DM_DSCR_BASE_RINGSZ(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_RINGSZ)
397#define G_DM_DSCR_BASE_RINGSZ(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_RINGSZ,M_DM_DSCR_BASE_RINGSZ)
398
399#define S_DM_DSCR_BASE_PRIORITY _SB_MAKE64(56)
400#define M_DM_DSCR_BASE_PRIORITY _SB_MAKEMASK(3,S_DM_DSCR_BASE_PRIORITY)
401#define V_DM_DSCR_BASE_PRIORITY(x) _SB_MAKEVALUE(x,S_DM_DSCR_BASE_PRIORITY)
402#define G_DM_DSCR_BASE_PRIORITY(x) _SB_GETVALUE(x,S_DM_DSCR_BASE_PRIORITY,M_DM_DSCR_BASE_PRIORITY)
403
404#define K_DM_DSCR_BASE_PRIORITY_1 0
405#define K_DM_DSCR_BASE_PRIORITY_2 1
406#define K_DM_DSCR_BASE_PRIORITY_4 2
407#define K_DM_DSCR_BASE_PRIORITY_8 3
408#define K_DM_DSCR_BASE_PRIORITY_16 4
409
410#define M_DM_DSCR_BASE_ACTIVE _SB_MAKEMASK1(59)
411#define M_DM_DSCR_BASE_INTERRUPT _SB_MAKEMASK1(60)
412#define M_DM_DSCR_BASE_RESET _SB_MAKEMASK1(61) /* write register */
413#define M_DM_DSCR_BASE_ERROR _SB_MAKEMASK1(61) /* read register */
414#define M_DM_DSCR_BASE_ABORT _SB_MAKEMASK1(62)
415#define M_DM_DSCR_BASE_ENABL _SB_MAKEMASK1(63)
416
417/*
418 * Data Mover Descriptor Count Register (Table 7-25)
419 */
420
421/* no bitfields */
422
423/*
424 * Data Mover Current Descriptor Address (Table 7-24)
425 * Register: DM_CUR_DSCR_ADDR_0
426 * Register: DM_CUR_DSCR_ADDR_1
427 * Register: DM_CUR_DSCR_ADDR_2
428 * Register: DM_CUR_DSCR_ADDR_3
429 */
430
431#define S_DM_CUR_DSCR_DSCR_ADDR _SB_MAKE64(0)
432#define M_DM_CUR_DSCR_DSCR_ADDR _SB_MAKEMASK(40,S_DM_CUR_DSCR_DSCR_ADDR)
433
434#define S_DM_CUR_DSCR_DSCR_COUNT _SB_MAKE64(48)
435#define M_DM_CUR_DSCR_DSCR_COUNT _SB_MAKEMASK(16,S_DM_CUR_DSCR_DSCR_COUNT)
436#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT)
437#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r,S_DM_CUR_DSCR_DSCR_COUNT,\
438 M_DM_CUR_DSCR_DSCR_COUNT)
439
440
441#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
442/*
443 * Data Mover Channel Partial Result Registers
444 * Register: DM_PARTIAL_0
445 * Register: DM_PARTIAL_1
446 * Register: DM_PARTIAL_2
447 * Register: DM_PARTIAL_3
448 */
449#define S_DM_PARTIAL_CRC_PARTIAL _SB_MAKE64(0)
450#define M_DM_PARTIAL_CRC_PARTIAL _SB_MAKEMASK(32,S_DM_PARTIAL_CRC_PARTIAL)
451#define V_DM_PARTIAL_CRC_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_CRC_PARTIAL)
452#define G_DM_PARTIAL_CRC_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_CRC_PARTIAL,\
453 M_DM_PARTIAL_CRC_PARTIAL)
454
455#define S_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKE64(32)
456#define M_DM_PARTIAL_TCPCS_PARTIAL _SB_MAKEMASK(16,S_DM_PARTIAL_TCPCS_PARTIAL)
457#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL)
458#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r,S_DM_PARTIAL_TCPCS_PARTIAL,\
459 M_DM_PARTIAL_TCPCS_PARTIAL)
460
461#define M_DM_PARTIAL_ODD_BYTE _SB_MAKEMASK1(48)
462#endif /* 1250 PASS3 || 112x PASS1 */
463
464
465#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
466/*
467 * Data Mover CRC Definition Registers
468 * Register: CRC_DEF_0
469 * Register: CRC_DEF_1
470 */
471#define S_CRC_DEF_CRC_INIT _SB_MAKE64(0)
472#define M_CRC_DEF_CRC_INIT _SB_MAKEMASK(32,S_CRC_DEF_CRC_INIT)
473#define V_CRC_DEF_CRC_INIT(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_INIT)
474#define G_CRC_DEF_CRC_INIT(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_INIT,\
475 M_CRC_DEF_CRC_INIT)
476
477#define S_CRC_DEF_CRC_POLY _SB_MAKE64(32)
478#define M_CRC_DEF_CRC_POLY _SB_MAKEMASK(32,S_CRC_DEF_CRC_POLY)
479#define V_CRC_DEF_CRC_POLY(r) _SB_MAKEVALUE(r,S_CRC_DEF_CRC_POLY)
480#define G_CRC_DEF_CRC_POLY(r) _SB_GETVALUE(r,S_CRC_DEF_CRC_POLY,\
481 M_CRC_DEF_CRC_POLY)
482#endif /* 1250 PASS3 || 112x PASS1 */
483
484
485#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
486/*
487 * Data Mover CRC/Checksum Definition Registers
488 * Register: CTCP_DEF_0
489 * Register: CTCP_DEF_1
490 */
491#define S_CTCP_DEF_CRC_TXOR _SB_MAKE64(0)
492#define M_CTCP_DEF_CRC_TXOR _SB_MAKEMASK(32,S_CTCP_DEF_CRC_TXOR)
493#define V_CTCP_DEF_CRC_TXOR(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_TXOR)
494#define G_CTCP_DEF_CRC_TXOR(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_TXOR,\
495 M_CTCP_DEF_CRC_TXOR)
496
497#define S_CTCP_DEF_TCPCS_INIT _SB_MAKE64(32)
498#define M_CTCP_DEF_TCPCS_INIT _SB_MAKEMASK(16,S_CTCP_DEF_TCPCS_INIT)
499#define V_CTCP_DEF_TCPCS_INIT(r) _SB_MAKEVALUE(r,S_CTCP_DEF_TCPCS_INIT)
500#define G_CTCP_DEF_TCPCS_INIT(r) _SB_GETVALUE(r,S_CTCP_DEF_TCPCS_INIT,\
501 M_CTCP_DEF_TCPCS_INIT)
502
503#define S_CTCP_DEF_CRC_WIDTH _SB_MAKE64(48)
504#define M_CTCP_DEF_CRC_WIDTH _SB_MAKEMASK(2,S_CTCP_DEF_CRC_WIDTH)
505#define V_CTCP_DEF_CRC_WIDTH(r) _SB_MAKEVALUE(r,S_CTCP_DEF_CRC_WIDTH)
506#define G_CTCP_DEF_CRC_WIDTH(r) _SB_GETVALUE(r,S_CTCP_DEF_CRC_WIDTH,\
507 M_CTCP_DEF_CRC_WIDTH)
508
509#define K_CTCP_DEF_CRC_WIDTH_4 0
510#define K_CTCP_DEF_CRC_WIDTH_2 1
511#define K_CTCP_DEF_CRC_WIDTH_1 2
512
513#define M_CTCP_DEF_CRC_BIT_ORDER _SB_MAKEMASK1(50)
514#endif /* 1250 PASS3 || 112x PASS1 */
515
516
517/*
518 * Data Mover Descriptor Doubleword "A" (Table 7-26)
519 */
520
521#define S_DM_DSCRA_DST_ADDR _SB_MAKE64(0)
522#define M_DM_DSCRA_DST_ADDR _SB_MAKEMASK(40,S_DM_DSCRA_DST_ADDR)
523
524#define M_DM_DSCRA_UN_DEST _SB_MAKEMASK1(40)
525#define M_DM_DSCRA_UN_SRC _SB_MAKEMASK1(41)
526#define M_DM_DSCRA_INTERRUPT _SB_MAKEMASK1(42)
527#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
528#define M_DM_DSCRA_THROTTLE _SB_MAKEMASK1(43)
529#endif /* up to 1250 PASS1 */
530
531#define S_DM_DSCRA_DIR_DEST _SB_MAKE64(44)
532#define M_DM_DSCRA_DIR_DEST _SB_MAKEMASK(2,S_DM_DSCRA_DIR_DEST)
533#define V_DM_DSCRA_DIR_DEST(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_DEST)
534#define G_DM_DSCRA_DIR_DEST(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_DEST,M_DM_DSCRA_DIR_DEST)
535
536#define K_DM_DSCRA_DIR_DEST_INCR 0
537#define K_DM_DSCRA_DIR_DEST_DECR 1
538#define K_DM_DSCRA_DIR_DEST_CONST 2
539
540#define V_DM_DSCRA_DIR_DEST_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR,S_DM_DSCRA_DIR_DEST)
541#define V_DM_DSCRA_DIR_DEST_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR,S_DM_DSCRA_DIR_DEST)
542#define V_DM_DSCRA_DIR_DEST_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST,S_DM_DSCRA_DIR_DEST)
543
544#define S_DM_DSCRA_DIR_SRC _SB_MAKE64(46)
545#define M_DM_DSCRA_DIR_SRC _SB_MAKEMASK(2,S_DM_DSCRA_DIR_SRC)
546#define V_DM_DSCRA_DIR_SRC(x) _SB_MAKEVALUE(x,S_DM_DSCRA_DIR_SRC)
547#define G_DM_DSCRA_DIR_SRC(x) _SB_GETVALUE(x,S_DM_DSCRA_DIR_SRC,M_DM_DSCRA_DIR_SRC)
548
549#define K_DM_DSCRA_DIR_SRC_INCR 0
550#define K_DM_DSCRA_DIR_SRC_DECR 1
551#define K_DM_DSCRA_DIR_SRC_CONST 2
552
553#define V_DM_DSCRA_DIR_SRC_INCR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR,S_DM_DSCRA_DIR_SRC)
554#define V_DM_DSCRA_DIR_SRC_DECR _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR,S_DM_DSCRA_DIR_SRC)
555#define V_DM_DSCRA_DIR_SRC_CONST _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST,S_DM_DSCRA_DIR_SRC)
556
557
558#define M_DM_DSCRA_ZERO_MEM _SB_MAKEMASK1(48)
559#define M_DM_DSCRA_PREFETCH _SB_MAKEMASK1(49)
560#define M_DM_DSCRA_L2C_DEST _SB_MAKEMASK1(50)
561#define M_DM_DSCRA_L2C_SRC _SB_MAKEMASK1(51)
562
563#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
564#define M_DM_DSCRA_RD_BKOFF _SB_MAKEMASK1(52)
565#define M_DM_DSCRA_WR_BKOFF _SB_MAKEMASK1(53)
566#endif /* 1250 PASS2 || 112x PASS1 */
567
568#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
569#define M_DM_DSCRA_TCPCS_EN _SB_MAKEMASK1(54)
570#define M_DM_DSCRA_TCPCS_RES _SB_MAKEMASK1(55)
571#define M_DM_DSCRA_TCPCS_AP _SB_MAKEMASK1(56)
572#define M_DM_DSCRA_CRC_EN _SB_MAKEMASK1(57)
573#define M_DM_DSCRA_CRC_RES _SB_MAKEMASK1(58)
574#define M_DM_DSCRA_CRC_AP _SB_MAKEMASK1(59)
575#define M_DM_DSCRA_CRC_DFN _SB_MAKEMASK1(60)
576#define M_DM_DSCRA_CRC_XBIT _SB_MAKEMASK1(61)
577#endif /* 1250 PASS3 || 112x PASS1 */
578
579#define M_DM_DSCRA_RESERVED2 _SB_MAKEMASK(3,61)
580
581/*
582 * Data Mover Descriptor Doubleword "B" (Table 7-25)
583 */
584
585#define S_DM_DSCRB_SRC_ADDR _SB_MAKE64(0)
586#define M_DM_DSCRB_SRC_ADDR _SB_MAKEMASK(40,S_DM_DSCRB_SRC_ADDR)
587
588#define S_DM_DSCRB_SRC_LENGTH _SB_MAKE64(40)
589#define M_DM_DSCRB_SRC_LENGTH _SB_MAKEMASK(20,S_DM_DSCRB_SRC_LENGTH)
590#define V_DM_DSCRB_SRC_LENGTH(x) _SB_MAKEVALUE(x,S_DM_DSCRB_SRC_LENGTH)
591#define G_DM_DSCRB_SRC_LENGTH(x) _SB_GETVALUE(x,S_DM_DSCRB_SRC_LENGTH,M_DM_DSCRB_SRC_LENGTH)
592
593
594#endif
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h
new file mode 100644
index 000000000000..0d9dfac3d7db
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_genbus.h
@@ -0,0 +1,276 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * Generic Bus Constants File: sb1250_genbus.h
5 *
6 * This module contains constants and macros useful for
7 * manipulating the SB1250's Generic Bus interface
8 *
9 * SB1250 specification level: User's manual 1/02/02
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34
35#ifndef _SB1250_GENBUS_H
36#define _SB1250_GENBUS_H
37
38#include "sb1250_defs.h"
39
40/*
41 * Generic Bus Region Configuration Registers (Table 11-4)
42 */
43
44#define S_IO_RDY_ACTIVE 0
45#define M_IO_RDY_ACTIVE _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
46
47#define S_IO_ENA_RDY 1
48#define M_IO_ENA_RDY _SB_MAKEMASK1(S_IO_ENA_RDY)
49
50#define S_IO_WIDTH_SEL 2
51#define M_IO_WIDTH_SEL _SB_MAKEMASK(2,S_IO_WIDTH_SEL)
52#define K_IO_WIDTH_SEL_1 0
53#define K_IO_WIDTH_SEL_2 1
54#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
55#define K_IO_WIDTH_SEL_1L 2
56#endif /* 1250 PASS2 || 112x PASS1 */
57#define K_IO_WIDTH_SEL_4 3
58#define V_IO_WIDTH_SEL(x) _SB_MAKEVALUE(x,S_IO_WIDTH_SEL)
59#define G_IO_WIDTH_SEL(x) _SB_GETVALUE(x,S_IO_WIDTH_SEL,M_IO_WIDTH_SEL)
60
61#define S_IO_PARITY_ENA 4
62#define M_IO_PARITY_ENA _SB_MAKEMASK1(S_IO_PARITY_ENA)
63#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
64#define S_IO_BURST_EN 5
65#define M_IO_BURST_EN _SB_MAKEMASK1(S_IO_BURST_EN)
66#endif /* 1250 PASS2 || 112x PASS1 */
67#define S_IO_PARITY_ODD 6
68#define M_IO_PARITY_ODD _SB_MAKEMASK1(S_IO_PARITY_ODD)
69#define S_IO_NONMUX 7
70#define M_IO_NONMUX _SB_MAKEMASK1(S_IO_NONMUX)
71
72#define S_IO_TIMEOUT 8
73#define M_IO_TIMEOUT _SB_MAKEMASK(8,S_IO_TIMEOUT)
74#define V_IO_TIMEOUT(x) _SB_MAKEVALUE(x,S_IO_TIMEOUT)
75#define G_IO_TIMEOUT(x) _SB_GETVALUE(x,S_IO_TIMEOUT,M_IO_TIMEOUT)
76
77/*
78 * Generic Bus Region Size register (Table 11-5)
79 */
80
81#define S_IO_MULT_SIZE 0
82#define M_IO_MULT_SIZE _SB_MAKEMASK(12,S_IO_MULT_SIZE)
83#define V_IO_MULT_SIZE(x) _SB_MAKEVALUE(x,S_IO_MULT_SIZE)
84#define G_IO_MULT_SIZE(x) _SB_GETVALUE(x,S_IO_MULT_SIZE,M_IO_MULT_SIZE)
85
86#define S_IO_REGSIZE 16 /* # bits to shift size for this reg */
87
88/*
89 * Generic Bus Region Address (Table 11-6)
90 */
91
92#define S_IO_START_ADDR 0
93#define M_IO_START_ADDR _SB_MAKEMASK(14,S_IO_START_ADDR)
94#define V_IO_START_ADDR(x) _SB_MAKEVALUE(x,S_IO_START_ADDR)
95#define G_IO_START_ADDR(x) _SB_GETVALUE(x,S_IO_START_ADDR,M_IO_START_ADDR)
96
97#define S_IO_ADDRBASE 16 /* # bits to shift addr for this reg */
98
99/*
100 * Generic Bus Region 0 Timing Registers (Table 11-7)
101 */
102
103#define S_IO_ALE_WIDTH 0
104#define M_IO_ALE_WIDTH _SB_MAKEMASK(3,S_IO_ALE_WIDTH)
105#define V_IO_ALE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_ALE_WIDTH)
106#define G_IO_ALE_WIDTH(x) _SB_GETVALUE(x,S_IO_ALE_WIDTH,M_IO_ALE_WIDTH)
107
108#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
109#define M_IO_EARLY_CS _SB_MAKEMASK1(3)
110#endif /* 1250 PASS2 || 112x PASS1 */
111
112#define S_IO_ALE_TO_CS 4
113#define M_IO_ALE_TO_CS _SB_MAKEMASK(2,S_IO_ALE_TO_CS)
114#define V_IO_ALE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_CS)
115#define G_IO_ALE_TO_CS(x) _SB_GETVALUE(x,S_IO_ALE_TO_CS,M_IO_ALE_TO_CS)
116
117#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
118#define S_IO_BURST_WIDTH _SB_MAKE64(6)
119#define M_IO_BURST_WIDTH _SB_MAKEMASK(2,S_IO_BURST_WIDTH)
120#define V_IO_BURST_WIDTH(x) _SB_MAKEVALUE(x,S_IO_BURST_WIDTH)
121#define G_IO_BURST_WIDTH(x) _SB_GETVALUE(x,S_IO_BURST_WIDTH,M_IO_BURST_WIDTH)
122#endif /* 1250 PASS2 || 112x PASS1 */
123
124#define S_IO_CS_WIDTH 8
125#define M_IO_CS_WIDTH _SB_MAKEMASK(5,S_IO_CS_WIDTH)
126#define V_IO_CS_WIDTH(x) _SB_MAKEVALUE(x,S_IO_CS_WIDTH)
127#define G_IO_CS_WIDTH(x) _SB_GETVALUE(x,S_IO_CS_WIDTH,M_IO_CS_WIDTH)
128
129#define S_IO_RDY_SMPLE 13
130#define M_IO_RDY_SMPLE _SB_MAKEMASK(3,S_IO_RDY_SMPLE)
131#define V_IO_RDY_SMPLE(x) _SB_MAKEVALUE(x,S_IO_RDY_SMPLE)
132#define G_IO_RDY_SMPLE(x) _SB_GETVALUE(x,S_IO_RDY_SMPLE,M_IO_RDY_SMPLE)
133
134
135/*
136 * Generic Bus Timing 1 Registers (Table 11-8)
137 */
138
139#define S_IO_ALE_TO_WRITE 0
140#define M_IO_ALE_TO_WRITE _SB_MAKEMASK(3,S_IO_ALE_TO_WRITE)
141#define V_IO_ALE_TO_WRITE(x) _SB_MAKEVALUE(x,S_IO_ALE_TO_WRITE)
142#define G_IO_ALE_TO_WRITE(x) _SB_GETVALUE(x,S_IO_ALE_TO_WRITE,M_IO_ALE_TO_WRITE)
143
144#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
145#define M_IO_RDY_SYNC _SB_MAKEMASK1(3)
146#endif /* 1250 PASS2 || 112x PASS1 */
147
148#define S_IO_WRITE_WIDTH 4
149#define M_IO_WRITE_WIDTH _SB_MAKEMASK(4,S_IO_WRITE_WIDTH)
150#define V_IO_WRITE_WIDTH(x) _SB_MAKEVALUE(x,S_IO_WRITE_WIDTH)
151#define G_IO_WRITE_WIDTH(x) _SB_GETVALUE(x,S_IO_WRITE_WIDTH,M_IO_WRITE_WIDTH)
152
153#define S_IO_IDLE_CYCLE 8
154#define M_IO_IDLE_CYCLE _SB_MAKEMASK(4,S_IO_IDLE_CYCLE)
155#define V_IO_IDLE_CYCLE(x) _SB_MAKEVALUE(x,S_IO_IDLE_CYCLE)
156#define G_IO_IDLE_CYCLE(x) _SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE)
157
158#define S_IO_OE_TO_CS 12
159#define M_IO_OE_TO_CS _SB_MAKEMASK(2,S_IO_OE_TO_CS)
160#define V_IO_OE_TO_CS(x) _SB_MAKEVALUE(x,S_IO_OE_TO_CS)
161#define G_IO_OE_TO_CS(x) _SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS)
162
163#define S_IO_CS_TO_OE 14
164#define M_IO_CS_TO_OE _SB_MAKEMASK(2,S_IO_CS_TO_OE)
165#define V_IO_CS_TO_OE(x) _SB_MAKEVALUE(x,S_IO_CS_TO_OE)
166#define G_IO_CS_TO_OE(x) _SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE)
167
168/*
169 * Generic Bus Interrupt Status Register (Table 11-9)
170 */
171
172#define M_IO_CS_ERR_INT _SB_MAKEMASK(0,8)
173#define M_IO_CS0_ERR_INT _SB_MAKEMASK1(0)
174#define M_IO_CS1_ERR_INT _SB_MAKEMASK1(1)
175#define M_IO_CS2_ERR_INT _SB_MAKEMASK1(2)
176#define M_IO_CS3_ERR_INT _SB_MAKEMASK1(3)
177#define M_IO_CS4_ERR_INT _SB_MAKEMASK1(4)
178#define M_IO_CS5_ERR_INT _SB_MAKEMASK1(5)
179#define M_IO_CS6_ERR_INT _SB_MAKEMASK1(6)
180#define M_IO_CS7_ERR_INT _SB_MAKEMASK1(7)
181
182#define M_IO_RD_PAR_INT _SB_MAKEMASK1(9)
183#define M_IO_TIMEOUT_INT _SB_MAKEMASK1(10)
184#define M_IO_ILL_ADDR_INT _SB_MAKEMASK1(11)
185#define M_IO_MULT_CS_INT _SB_MAKEMASK1(12)
186#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
187#define M_IO_COH_ERR _SB_MAKEMASK1(14)
188#endif /* 1250 PASS2 || 112x PASS1 */
189
190/*
191 * PCMCIA configuration register (Table 12-6)
192 */
193
194#define M_PCMCIA_CFG_ATTRMEM _SB_MAKEMASK1(0)
195#define M_PCMCIA_CFG_3VEN _SB_MAKEMASK1(1)
196#define M_PCMCIA_CFG_5VEN _SB_MAKEMASK1(2)
197#define M_PCMCIA_CFG_VPPEN _SB_MAKEMASK1(3)
198#define M_PCMCIA_CFG_RESET _SB_MAKEMASK1(4)
199#define M_PCMCIA_CFG_APWRONEN _SB_MAKEMASK1(5)
200#define M_PCMCIA_CFG_CDMASK _SB_MAKEMASK1(6)
201#define M_PCMCIA_CFG_WPMASK _SB_MAKEMASK1(7)
202#define M_PCMCIA_CFG_RDYMASK _SB_MAKEMASK1(8)
203#define M_PCMCIA_CFG_PWRCTL _SB_MAKEMASK1(9)
204
205/*
206 * PCMCIA status register (Table 12-7)
207 */
208
209#define M_PCMCIA_STATUS_CD1 _SB_MAKEMASK1(0)
210#define M_PCMCIA_STATUS_CD2 _SB_MAKEMASK1(1)
211#define M_PCMCIA_STATUS_VS1 _SB_MAKEMASK1(2)
212#define M_PCMCIA_STATUS_VS2 _SB_MAKEMASK1(3)
213#define M_PCMCIA_STATUS_WP _SB_MAKEMASK1(4)
214#define M_PCMCIA_STATUS_RDY _SB_MAKEMASK1(5)
215#define M_PCMCIA_STATUS_3VEN _SB_MAKEMASK1(6)
216#define M_PCMCIA_STATUS_5VEN _SB_MAKEMASK1(7)
217#define M_PCMCIA_STATUS_CDCHG _SB_MAKEMASK1(8)
218#define M_PCMCIA_STATUS_WPCHG _SB_MAKEMASK1(9)
219#define M_PCMCIA_STATUS_RDYCHG _SB_MAKEMASK1(10)
220
221/*
222 * GPIO Interrupt Type Register (table 13-3)
223 */
224
225#define K_GPIO_INTR_DISABLE 0
226#define K_GPIO_INTR_EDGE 1
227#define K_GPIO_INTR_LEVEL 2
228#define K_GPIO_INTR_SPLIT 3
229
230#define S_GPIO_INTR_TYPEX(n) (((n)/2)*2)
231#define M_GPIO_INTR_TYPEX(n) _SB_MAKEMASK(2,S_GPIO_INTR_TYPEX(n))
232#define V_GPIO_INTR_TYPEX(n,x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPEX(n))
233#define G_GPIO_INTR_TYPEX(n,x) _SB_GETVALUE(x,S_GPIO_INTR_TYPEX(n),M_GPIO_INTR_TYPEX(n))
234
235#define S_GPIO_INTR_TYPE0 0
236#define M_GPIO_INTR_TYPE0 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE0)
237#define V_GPIO_INTR_TYPE0(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE0)
238#define G_GPIO_INTR_TYPE0(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE0,M_GPIO_INTR_TYPE0)
239
240#define S_GPIO_INTR_TYPE2 2
241#define M_GPIO_INTR_TYPE2 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE2)
242#define V_GPIO_INTR_TYPE2(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE2)
243#define G_GPIO_INTR_TYPE2(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE2,M_GPIO_INTR_TYPE2)
244
245#define S_GPIO_INTR_TYPE4 4
246#define M_GPIO_INTR_TYPE4 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE4)
247#define V_GPIO_INTR_TYPE4(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE4)
248#define G_GPIO_INTR_TYPE4(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE4,M_GPIO_INTR_TYPE4)
249
250#define S_GPIO_INTR_TYPE6 6
251#define M_GPIO_INTR_TYPE6 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE6)
252#define V_GPIO_INTR_TYPE6(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE6)
253#define G_GPIO_INTR_TYPE6(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE6,M_GPIO_INTR_TYPE6)
254
255#define S_GPIO_INTR_TYPE8 8
256#define M_GPIO_INTR_TYPE8 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE8)
257#define V_GPIO_INTR_TYPE8(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE8)
258#define G_GPIO_INTR_TYPE8(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE8,M_GPIO_INTR_TYPE8)
259
260#define S_GPIO_INTR_TYPE10 10
261#define M_GPIO_INTR_TYPE10 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE10)
262#define V_GPIO_INTR_TYPE10(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE10)
263#define G_GPIO_INTR_TYPE10(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE10,M_GPIO_INTR_TYPE10)
264
265#define S_GPIO_INTR_TYPE12 12
266#define M_GPIO_INTR_TYPE12 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE12)
267#define V_GPIO_INTR_TYPE12(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE12)
268#define G_GPIO_INTR_TYPE12(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE12,M_GPIO_INTR_TYPE12)
269
270#define S_GPIO_INTR_TYPE14 14
271#define M_GPIO_INTR_TYPE14 _SB_MAKEMASK(2,S_GPIO_INTR_TYPE14)
272#define V_GPIO_INTR_TYPE14(x) _SB_MAKEVALUE(x,S_GPIO_INTR_TYPE14)
273#define G_GPIO_INTR_TYPE14(x) _SB_GETVALUE(x,S_GPIO_INTR_TYPE14,M_GPIO_INTR_TYPE14)
274
275
276#endif
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
new file mode 100644
index 000000000000..c3f74df211f4
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_int.h
@@ -0,0 +1,247 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * Interrupt Mapper definitions File: sb1250_int.h
5 *
6 * This module contains constants for manipulating the SB1250's
7 * interrupt mapper and definitions for the interrupt sources.
8 *
9 * SB1250 specification level: User's manual 1/02/02
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34
35#ifndef _SB1250_INT_H
36#define _SB1250_INT_H
37
38#include "sb1250_defs.h"
39
40/* *********************************************************************
41 * Interrupt Mapper Constants
42 ********************************************************************* */
43
44/*
45 * Interrupt sources (Table 4-8, UM 0.2)
46 *
47 * First, the interrupt numbers.
48 */
49
50#define K_INT_WATCHDOG_TIMER_0 0
51#define K_INT_WATCHDOG_TIMER_1 1
52#define K_INT_TIMER_0 2
53#define K_INT_TIMER_1 3
54#define K_INT_TIMER_2 4
55#define K_INT_TIMER_3 5
56#define K_INT_SMB_0 6
57#define K_INT_SMB_1 7
58#define K_INT_UART_0 8
59#define K_INT_UART_1 9
60#define K_INT_SER_0 10
61#define K_INT_SER_1 11
62#define K_INT_PCMCIA 12
63#define K_INT_ADDR_TRAP 13
64#define K_INT_PERF_CNT 14
65#define K_INT_TRACE_FREEZE 15
66#define K_INT_BAD_ECC 16
67#define K_INT_COR_ECC 17
68#define K_INT_IO_BUS 18
69#define K_INT_MAC_0 19
70#define K_INT_MAC_1 20
71#define K_INT_MAC_2 21
72#define K_INT_DM_CH_0 22
73#define K_INT_DM_CH_1 23
74#define K_INT_DM_CH_2 24
75#define K_INT_DM_CH_3 25
76#define K_INT_MBOX_0 26
77#define K_INT_MBOX_1 27
78#define K_INT_MBOX_2 28
79#define K_INT_MBOX_3 29
80#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
81#define K_INT_CYCLE_CP0_INT 30
82#define K_INT_CYCLE_CP1_INT 31
83#endif /* 1250 PASS2 || 112x PASS1 */
84#define K_INT_GPIO_0 32
85#define K_INT_GPIO_1 33
86#define K_INT_GPIO_2 34
87#define K_INT_GPIO_3 35
88#define K_INT_GPIO_4 36
89#define K_INT_GPIO_5 37
90#define K_INT_GPIO_6 38
91#define K_INT_GPIO_7 39
92#define K_INT_GPIO_8 40
93#define K_INT_GPIO_9 41
94#define K_INT_GPIO_10 42
95#define K_INT_GPIO_11 43
96#define K_INT_GPIO_12 44
97#define K_INT_GPIO_13 45
98#define K_INT_GPIO_14 46
99#define K_INT_GPIO_15 47
100#define K_INT_LDT_FATAL 48
101#define K_INT_LDT_NONFATAL 49
102#define K_INT_LDT_SMI 50
103#define K_INT_LDT_NMI 51
104#define K_INT_LDT_INIT 52
105#define K_INT_LDT_STARTUP 53
106#define K_INT_LDT_EXT 54
107#define K_INT_PCI_ERROR 55
108#define K_INT_PCI_INTA 56
109#define K_INT_PCI_INTB 57
110#define K_INT_PCI_INTC 58
111#define K_INT_PCI_INTD 59
112#define K_INT_SPARE_2 60
113#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
114#define K_INT_MAC_0_CH1 61
115#define K_INT_MAC_1_CH1 62
116#define K_INT_MAC_2_CH1 63
117#endif /* 1250 PASS2 || 112x PASS1 */
118
119/*
120 * Mask values for each interrupt
121 */
122
123#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
124#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
125#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0)
126#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1)
127#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2)
128#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3)
129#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0)
130#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1)
131#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0)
132#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1)
133#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)
134#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1)
135#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA)
136#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP)
137#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT)
138#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
139#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC)
140#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC)
141#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)
142#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0)
143#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1)
144#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2)
145#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)
146#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)
147#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2)
148#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3)
149#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)
150#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
151#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
152#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
153#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
154#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
155#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
156#endif /* 1250 PASS2 || 112x PASS1 */
157#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
158#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
159#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
160#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3)
161#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)
162#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5)
163#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6)
164#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7)
165#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)
166#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9)
167#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10)
168#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)
169#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)
170#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13)
171#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14)
172#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15)
173#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL)
174#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
175#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI)
176#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI)
177#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT)
178#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP)
179#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT)
180#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR)
181#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA)
182#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB)
183#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
184#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
185#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
186#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
187#define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1)
188#define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1)
189#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1)
190#endif /* 1250 PASS2 || 112x PASS1 */
191
192/*
193 * Interrupt mappings
194 */
195
196#define K_INT_MAP_I0 0 /* interrupt pins on processor */
197#define K_INT_MAP_I1 1
198#define K_INT_MAP_I2 2
199#define K_INT_MAP_I3 3
200#define K_INT_MAP_I4 4
201#define K_INT_MAP_I5 5
202#define K_INT_MAP_NMI 6 /* nonmaskable */
203#define K_INT_MAP_DINT 7 /* debug interrupt */
204
205/*
206 * LDT Interrupt Set Register (table 4-5)
207 */
208
209#define S_INT_LDT_INTMSG 0
210#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG)
211#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG)
212#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG)
213
214#define K_INT_LDT_INTMSG_FIXED 0
215#define K_INT_LDT_INTMSG_ARBITRATED 1
216#define K_INT_LDT_INTMSG_SMI 2
217#define K_INT_LDT_INTMSG_NMI 3
218#define K_INT_LDT_INTMSG_INIT 4
219#define K_INT_LDT_INTMSG_STARTUP 5
220#define K_INT_LDT_INTMSG_EXTINT 6
221#define K_INT_LDT_INTMSG_RESERVED 7
222
223#define M_INT_LDT_EDGETRIGGER 0
224#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3)
225
226#define M_INT_LDT_PHYSICALDEST 0
227#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
228
229#define S_INT_LDT_INTDEST 5
230#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST)
231#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST)
232#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST)
233
234#define S_INT_LDT_VECTOR 13
235#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR)
236#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR)
237#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR)
238
239/*
240 * Vector format (Table 4-6)
241 */
242
243#define M_LDTVECT_RAISEINT 0x00
244#define M_LDTVECT_RAISEMBOX 0x40
245
246
247#endif
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h
new file mode 100644
index 000000000000..799db828d963
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_l2c.h
@@ -0,0 +1,128 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * L2 Cache constants and macros File: sb1250_l2c.h
5 *
6 * This module contains constants useful for manipulating the
7 * level 2 cache.
8 *
9 * SB1250 specification level: User's manual 1/02/02
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34
35#ifndef _SB1250_L2C_H
36#define _SB1250_L2C_H
37
38#include "sb1250_defs.h"
39
40/*
41 * Level 2 Cache Tag register (Table 5-3)
42 */
43
44#define S_L2C_TAG_MBZ 0
45#define M_L2C_TAG_MBZ _SB_MAKEMASK(5,S_L2C_TAG_MBZ)
46
47#define S_L2C_TAG_INDEX 5
48#define M_L2C_TAG_INDEX _SB_MAKEMASK(12,S_L2C_TAG_INDEX)
49#define V_L2C_TAG_INDEX(x) _SB_MAKEVALUE(x,S_L2C_TAG_INDEX)
50#define G_L2C_TAG_INDEX(x) _SB_GETVALUE(x,S_L2C_TAG_INDEX,M_L2C_TAG_INDEX)
51
52#define S_L2C_TAG_TAG 17
53#define M_L2C_TAG_TAG _SB_MAKEMASK(23,S_L2C_TAG_TAG)
54#define V_L2C_TAG_TAG(x) _SB_MAKEVALUE(x,S_L2C_TAG_TAG)
55#define G_L2C_TAG_TAG(x) _SB_GETVALUE(x,S_L2C_TAG_TAG,M_L2C_TAG_TAG)
56
57#define S_L2C_TAG_ECC 40
58#define M_L2C_TAG_ECC _SB_MAKEMASK(6,S_L2C_TAG_ECC)
59#define V_L2C_TAG_ECC(x) _SB_MAKEVALUE(x,S_L2C_TAG_ECC)
60#define G_L2C_TAG_ECC(x) _SB_GETVALUE(x,S_L2C_TAG_ECC,M_L2C_TAG_ECC)
61
62#define S_L2C_TAG_WAY 46
63#define M_L2C_TAG_WAY _SB_MAKEMASK(2,S_L2C_TAG_WAY)
64#define V_L2C_TAG_WAY(x) _SB_MAKEVALUE(x,S_L2C_TAG_WAY)
65#define G_L2C_TAG_WAY(x) _SB_GETVALUE(x,S_L2C_TAG_WAY,M_L2C_TAG_WAY)
66
67#define M_L2C_TAG_DIRTY _SB_MAKEMASK1(48)
68#define M_L2C_TAG_VALID _SB_MAKEMASK1(49)
69
70/*
71 * Format of level 2 cache management address (table 5-2)
72 */
73
74#define S_L2C_MGMT_INDEX 5
75#define M_L2C_MGMT_INDEX _SB_MAKEMASK(12,S_L2C_MGMT_INDEX)
76#define V_L2C_MGMT_INDEX(x) _SB_MAKEVALUE(x,S_L2C_MGMT_INDEX)
77#define G_L2C_MGMT_INDEX(x) _SB_GETVALUE(x,S_L2C_MGMT_INDEX,M_L2C_MGMT_INDEX)
78
79#define S_L2C_MGMT_QUADRANT 15
80#define M_L2C_MGMT_QUADRANT _SB_MAKEMASK(2,S_L2C_MGMT_QUADRANT)
81#define V_L2C_MGMT_QUADRANT(x) _SB_MAKEVALUE(x,S_L2C_MGMT_QUADRANT)
82#define G_L2C_MGMT_QUADRANT(x) _SB_GETVALUE(x,S_L2C_MGMT_QUADRANT,M_L2C_MGMT_QUADRANT)
83
84#define S_L2C_MGMT_HALF 16
85#define M_L2C_MGMT_HALF _SB_MAKEMASK(1,S_L2C_MGMT_HALF)
86
87#define S_L2C_MGMT_WAY 17
88#define M_L2C_MGMT_WAY _SB_MAKEMASK(2,S_L2C_MGMT_WAY)
89#define V_L2C_MGMT_WAY(x) _SB_MAKEVALUE(x,S_L2C_MGMT_WAY)
90#define G_L2C_MGMT_WAY(x) _SB_GETVALUE(x,S_L2C_MGMT_WAY,M_L2C_MGMT_WAY)
91
92#define S_L2C_MGMT_TAG 21
93#define M_L2C_MGMT_TAG _SB_MAKEMASK(6,S_L2C_MGMT_TAG)
94#define V_L2C_MGMT_TAG(x) _SB_MAKEVALUE(x,S_L2C_MGMT_TAG)
95#define G_L2C_MGMT_TAG(x) _SB_GETVALUE(x,S_L2C_MGMT_TAG,M_L2C_MGMT_TAG)
96
97#define M_L2C_MGMT_DIRTY _SB_MAKEMASK1(19)
98#define M_L2C_MGMT_VALID _SB_MAKEMASK1(20)
99
100#define A_L2C_MGMT_TAG_BASE 0x00D0000000
101
102#define L2C_ENTRIES_PER_WAY 4096
103#define L2C_NUM_WAYS 4
104
105
106#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
107/*
108 * L2 Read Misc. register (A_L2_READ_MISC)
109 */
110#define S_L2C_MISC_NO_WAY 10
111#define M_L2C_MISC_NO_WAY _SB_MAKEMASK(4,S_L2C_MISC_NO_WAY)
112#define V_L2C_MISC_NO_WAY(x) _SB_MAKEVALUE(x,S_L2C_MISC_NO_WAY)
113#define G_L2C_MISC_NO_WAY(x) _SB_GETVALUE(x,S_L2C_MISC_NO_WAY,M_L2C_MISC_NO_WAY)
114
115#define M_L2C_MISC_ECC_CLEANUP_DIS _SB_MAKEMASK1(9)
116#define M_L2C_MISC_MC_PRIO_LOW _SB_MAKEMASK1(8)
117#define M_L2C_MISC_SOFT_DISABLE_T _SB_MAKEMASK1(7)
118#define M_L2C_MISC_SOFT_DISABLE_B _SB_MAKEMASK1(6)
119#define M_L2C_MISC_SOFT_DISABLE_R _SB_MAKEMASK1(5)
120#define M_L2C_MISC_SOFT_DISABLE_L _SB_MAKEMASK1(4)
121#define M_L2C_MISC_SCACHE_DISABLE_T _SB_MAKEMASK1(3)
122#define M_L2C_MISC_SCACHE_DISABLE_B _SB_MAKEMASK1(2)
123#define M_L2C_MISC_SCACHE_DISABLE_R _SB_MAKEMASK1(1)
124#define M_L2C_MISC_SCACHE_DISABLE_L _SB_MAKEMASK1(0)
125#endif /* 1250 PASS3 || 112x PASS1 */
126
127
128#endif
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h
new file mode 100644
index 000000000000..d8753885df17
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_ldt.h
@@ -0,0 +1,425 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * LDT constants File: sb1250_ldt.h
5 *
6 * This module contains constants and macros to describe
7 * the LDT interface on the SB1250.
8 *
9 * SB1250 specification level: User's manual 1/02/02
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34
35#ifndef _SB1250_LDT_H
36#define _SB1250_LDT_H
37
38#include "sb1250_defs.h"
39
40#define K_LDT_VENDOR_SIBYTE 0x166D
41#define K_LDT_DEVICE_SB1250 0x0002
42
43/*
44 * LDT Interface Type 1 (bridge) configuration header
45 */
46
47#define R_LDT_TYPE1_DEVICEID 0x0000
48#define R_LDT_TYPE1_CMDSTATUS 0x0004
49#define R_LDT_TYPE1_CLASSREV 0x0008
50#define R_LDT_TYPE1_DEVHDR 0x000C
51#define R_LDT_TYPE1_BAR0 0x0010 /* not used */
52#define R_LDT_TYPE1_BAR1 0x0014 /* not used */
53
54#define R_LDT_TYPE1_BUSID 0x0018 /* bus ID register */
55#define R_LDT_TYPE1_SECSTATUS 0x001C /* secondary status / I/O base/limit */
56#define R_LDT_TYPE1_MEMLIMIT 0x0020
57#define R_LDT_TYPE1_PREFETCH 0x0024
58#define R_LDT_TYPE1_PREF_BASE 0x0028
59#define R_LDT_TYPE1_PREF_LIMIT 0x002C
60#define R_LDT_TYPE1_IOLIMIT 0x0030
61#define R_LDT_TYPE1_CAPPTR 0x0034
62#define R_LDT_TYPE1_ROMADDR 0x0038
63#define R_LDT_TYPE1_BRCTL 0x003C
64#define R_LDT_TYPE1_CMD 0x0040
65#define R_LDT_TYPE1_LINKCTRL 0x0044
66#define R_LDT_TYPE1_LINKFREQ 0x0048
67#define R_LDT_TYPE1_RESERVED1 0x004C
68#define R_LDT_TYPE1_SRICMD 0x0050
69#define R_LDT_TYPE1_SRITXNUM 0x0054
70#define R_LDT_TYPE1_SRIRXNUM 0x0058
71#define R_LDT_TYPE1_ERRSTATUS 0x0068
72#define R_LDT_TYPE1_SRICTRL 0x006C
73#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
74#define R_LDT_TYPE1_ADDSTATUS 0x0070
75#endif /* 1250 PASS2 || 112x PASS1 */
76#define R_LDT_TYPE1_TXBUFCNT 0x00C8
77#define R_LDT_TYPE1_EXPCRC 0x00DC
78#define R_LDT_TYPE1_RXCRC 0x00F0
79
80
81/*
82 * LDT Device ID register
83 */
84
85#define S_LDT_DEVICEID_VENDOR 0
86#define M_LDT_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_LDT_DEVICEID_VENDOR)
87#define V_LDT_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_VENDOR)
88#define G_LDT_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_VENDOR,M_LDT_DEVICEID_VENDOR)
89
90#define S_LDT_DEVICEID_DEVICEID 16
91#define M_LDT_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_LDT_DEVICEID_DEVICEID)
92#define V_LDT_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_LDT_DEVICEID_DEVICEID)
93#define G_LDT_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_LDT_DEVICEID_DEVICEID,M_LDT_DEVICEID_DEVICEID)
94
95
96/*
97 * LDT Command Register (Table 8-13)
98 */
99
100#define M_LDT_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0)
101#define M_LDT_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1)
102#define M_LDT_CMD_MASTER_EN _SB_MAKEMASK1_32(2)
103#define M_LDT_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3)
104#define M_LDT_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4)
105#define M_LDT_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5)
106#define M_LDT_CMD_PARERRRESP _SB_MAKEMASK1_32(6)
107#define M_LDT_CMD_WAITCYCCTRL _SB_MAKEMASK1_32(7)
108#define M_LDT_CMD_SERR_EN _SB_MAKEMASK1_32(8)
109#define M_LDT_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9)
110
111/*
112 * LDT class and revision registers
113 */
114
115#define S_LDT_CLASSREV_REV 0
116#define M_LDT_CLASSREV_REV _SB_MAKEMASK_32(8,S_LDT_CLASSREV_REV)
117#define V_LDT_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_REV)
118#define G_LDT_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_REV,M_LDT_CLASSREV_REV)
119
120#define S_LDT_CLASSREV_CLASS 8
121#define M_LDT_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_LDT_CLASSREV_CLASS)
122#define V_LDT_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_LDT_CLASSREV_CLASS)
123#define G_LDT_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_LDT_CLASSREV_CLASS,M_LDT_CLASSREV_CLASS)
124
125#define K_LDT_REV 0x01
126#define K_LDT_CLASS 0x060000
127
128/*
129 * Device Header (offset 0x0C)
130 */
131
132#define S_LDT_DEVHDR_CLINESZ 0
133#define M_LDT_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_LDT_DEVHDR_CLINESZ)
134#define V_LDT_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_CLINESZ)
135#define G_LDT_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_CLINESZ,M_LDT_DEVHDR_CLINESZ)
136
137#define S_LDT_DEVHDR_LATTMR 8
138#define M_LDT_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_LDT_DEVHDR_LATTMR)
139#define V_LDT_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_LATTMR)
140#define G_LDT_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_LATTMR,M_LDT_DEVHDR_LATTMR)
141
142#define S_LDT_DEVHDR_HDRTYPE 16
143#define M_LDT_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_LDT_DEVHDR_HDRTYPE)
144#define V_LDT_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_HDRTYPE)
145#define G_LDT_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_HDRTYPE,M_LDT_DEVHDR_HDRTYPE)
146
147#define K_LDT_DEVHDR_HDRTYPE_TYPE1 1
148
149#define S_LDT_DEVHDR_BIST 24
150#define M_LDT_DEVHDR_BIST _SB_MAKEMASK_32(8,S_LDT_DEVHDR_BIST)
151#define V_LDT_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_LDT_DEVHDR_BIST)
152#define G_LDT_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_LDT_DEVHDR_BIST,M_LDT_DEVHDR_BIST)
153
154
155
156/*
157 * LDT Status Register (Table 8-14). Note that these constants
158 * assume you've read the command and status register
159 * together (32-bit read at offset 0x04)
160 *
161 * These bits also apply to the secondary status
162 * register (Table 8-15), offset 0x1C
163 */
164
165#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
166#define M_LDT_STATUS_VGAEN _SB_MAKEMASK1_32(3)
167#endif /* 1250 PASS2 || 112x PASS1 */
168#define M_LDT_STATUS_CAPLIST _SB_MAKEMASK1_32(20)
169#define M_LDT_STATUS_66MHZCAP _SB_MAKEMASK1_32(21)
170#define M_LDT_STATUS_RESERVED2 _SB_MAKEMASK1_32(22)
171#define M_LDT_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23)
172#define M_LDT_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24)
173
174#define S_LDT_STATUS_DEVSELTIMING 25
175#define M_LDT_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_LDT_STATUS_DEVSELTIMING)
176#define V_LDT_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_LDT_STATUS_DEVSELTIMING)
177#define G_LDT_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_LDT_STATUS_DEVSELTIMING,M_LDT_STATUS_DEVSELTIMING)
178
179#define M_LDT_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27)
180#define M_LDT_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28)
181#define M_LDT_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29)
182#define M_LDT_STATUS_SIGDSERR _SB_MAKEMASK1_32(30)
183#define M_LDT_STATUS_DETPARERR _SB_MAKEMASK1_32(31)
184
185/*
186 * Bridge Control Register (Table 8-16). Note that these
187 * constants assume you've read the register as a 32-bit
188 * read (offset 0x3C)
189 */
190
191#define M_LDT_BRCTL_PARERRRESP_EN _SB_MAKEMASK1_32(16)
192#define M_LDT_BRCTL_SERR_EN _SB_MAKEMASK1_32(17)
193#define M_LDT_BRCTL_ISA_EN _SB_MAKEMASK1_32(18)
194#define M_LDT_BRCTL_VGA_EN _SB_MAKEMASK1_32(19)
195#define M_LDT_BRCTL_MSTRABORTMODE _SB_MAKEMASK1_32(21)
196#define M_LDT_BRCTL_SECBUSRESET _SB_MAKEMASK1_32(22)
197#define M_LDT_BRCTL_FASTB2B_EN _SB_MAKEMASK1_32(23)
198#define M_LDT_BRCTL_PRIDISCARD _SB_MAKEMASK1_32(24)
199#define M_LDT_BRCTL_SECDISCARD _SB_MAKEMASK1_32(25)
200#define M_LDT_BRCTL_DISCARDSTAT _SB_MAKEMASK1_32(26)
201#define M_LDT_BRCTL_DISCARDSERR_EN _SB_MAKEMASK1_32(27)
202
203/*
204 * LDT Command Register (Table 8-17). Note that these constants
205 * assume you've read the command and status register together
206 * 32-bit read at offset 0x40
207 */
208
209#define M_LDT_CMD_WARMRESET _SB_MAKEMASK1_32(16)
210#define M_LDT_CMD_DOUBLEENDED _SB_MAKEMASK1_32(17)
211
212#define S_LDT_CMD_CAPTYPE 29
213#define M_LDT_CMD_CAPTYPE _SB_MAKEMASK_32(3,S_LDT_CMD_CAPTYPE)
214#define V_LDT_CMD_CAPTYPE(x) _SB_MAKEVALUE_32(x,S_LDT_CMD_CAPTYPE)
215#define G_LDT_CMD_CAPTYPE(x) _SB_GETVALUE_32(x,S_LDT_CMD_CAPTYPE,M_LDT_CMD_CAPTYPE)
216
217/*
218 * LDT link control register (Table 8-18), and (Table 8-19)
219 */
220
221#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN _SB_MAKEMASK1_32(1)
222#define M_LDT_LINKCTRL_CRCSTARTTEST _SB_MAKEMASK1_32(2)
223#define M_LDT_LINKCTRL_CRCFORCEERR _SB_MAKEMASK1_32(3)
224#define M_LDT_LINKCTRL_LINKFAIL _SB_MAKEMASK1_32(4)
225#define M_LDT_LINKCTRL_INITDONE _SB_MAKEMASK1_32(5)
226#define M_LDT_LINKCTRL_EOC _SB_MAKEMASK1_32(6)
227#define M_LDT_LINKCTRL_XMITOFF _SB_MAKEMASK1_32(7)
228
229#define S_LDT_LINKCTRL_CRCERR 8
230#define M_LDT_LINKCTRL_CRCERR _SB_MAKEMASK_32(4,S_LDT_LINKCTRL_CRCERR)
231#define V_LDT_LINKCTRL_CRCERR(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_CRCERR)
232#define G_LDT_LINKCTRL_CRCERR(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_CRCERR,M_LDT_LINKCTRL_CRCERR)
233
234#define S_LDT_LINKCTRL_MAXIN 16
235#define M_LDT_LINKCTRL_MAXIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXIN)
236#define V_LDT_LINKCTRL_MAXIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXIN)
237#define G_LDT_LINKCTRL_MAXIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXIN,M_LDT_LINKCTRL_MAXIN)
238
239#define M_LDT_LINKCTRL_DWFCLN _SB_MAKEMASK1_32(19)
240
241#define S_LDT_LINKCTRL_MAXOUT 20
242#define M_LDT_LINKCTRL_MAXOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_MAXOUT)
243#define V_LDT_LINKCTRL_MAXOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_MAXOUT)
244#define G_LDT_LINKCTRL_MAXOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_MAXOUT,M_LDT_LINKCTRL_MAXOUT)
245
246#define M_LDT_LINKCTRL_DWFCOUT _SB_MAKEMASK1_32(23)
247
248#define S_LDT_LINKCTRL_WIDTHIN 24
249#define M_LDT_LINKCTRL_WIDTHIN _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHIN)
250#define V_LDT_LINKCTRL_WIDTHIN(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN)
251#define G_LDT_LINKCTRL_WIDTHIN(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHIN,M_LDT_LINKCTRL_WIDTHIN)
252
253#define M_LDT_LINKCTRL_DWFCLIN_EN _SB_MAKEMASK1_32(27)
254
255#define S_LDT_LINKCTRL_WIDTHOUT 28
256#define M_LDT_LINKCTRL_WIDTHOUT _SB_MAKEMASK_32(3,S_LDT_LINKCTRL_WIDTHOUT)
257#define V_LDT_LINKCTRL_WIDTHOUT(x) _SB_MAKEVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT)
258#define G_LDT_LINKCTRL_WIDTHOUT(x) _SB_GETVALUE_32(x,S_LDT_LINKCTRL_WIDTHOUT,M_LDT_LINKCTRL_WIDTHOUT)
259
260#define M_LDT_LINKCTRL_DWFCOUT_EN _SB_MAKEMASK1_32(31)
261
262/*
263 * LDT Link frequency register (Table 8-20) offset 0x48
264 */
265
266#define S_LDT_LINKFREQ_FREQ 8
267#define M_LDT_LINKFREQ_FREQ _SB_MAKEMASK_32(4,S_LDT_LINKFREQ_FREQ)
268#define V_LDT_LINKFREQ_FREQ(x) _SB_MAKEVALUE_32(x,S_LDT_LINKFREQ_FREQ)
269#define G_LDT_LINKFREQ_FREQ(x) _SB_GETVALUE_32(x,S_LDT_LINKFREQ_FREQ,M_LDT_LINKFREQ_FREQ)
270
271#define K_LDT_LINKFREQ_200MHZ 0
272#define K_LDT_LINKFREQ_300MHZ 1
273#define K_LDT_LINKFREQ_400MHZ 2
274#define K_LDT_LINKFREQ_500MHZ 3
275#define K_LDT_LINKFREQ_600MHZ 4
276#define K_LDT_LINKFREQ_800MHZ 5
277#define K_LDT_LINKFREQ_1000MHZ 6
278
279/*
280 * LDT SRI Command Register (Table 8-21). Note that these constants
281 * assume you've read the command and status register together
282 * 32-bit read at offset 0x50
283 */
284
285#define M_LDT_SRICMD_SIPREADY _SB_MAKEMASK1_32(16)
286#define M_LDT_SRICMD_SYNCPTRCTL _SB_MAKEMASK1_32(17)
287#define M_LDT_SRICMD_REDUCESYNCZERO _SB_MAKEMASK1_32(18)
288#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
289#define M_LDT_SRICMD_DISSTARVATIONCNT _SB_MAKEMASK1_32(19) /* PASS1 */
290#endif /* up to 1250 PASS1 */
291#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
292#define M_LDT_SRICMD_DISMULTTXVLD _SB_MAKEMASK1_32(19)
293#define M_LDT_SRICMD_EXPENDIAN _SB_MAKEMASK1_32(26)
294#endif /* 1250 PASS2 || 112x PASS1 */
295
296
297#define S_LDT_SRICMD_RXMARGIN 20
298#define M_LDT_SRICMD_RXMARGIN _SB_MAKEMASK_32(5,S_LDT_SRICMD_RXMARGIN)
299#define V_LDT_SRICMD_RXMARGIN(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_RXMARGIN)
300#define G_LDT_SRICMD_RXMARGIN(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_RXMARGIN,M_LDT_SRICMD_RXMARGIN)
301
302#define M_LDT_SRICMD_LDTPLLCOMPAT _SB_MAKEMASK1_32(25)
303
304#define S_LDT_SRICMD_TXINITIALOFFSET 28
305#define M_LDT_SRICMD_TXINITIALOFFSET _SB_MAKEMASK_32(3,S_LDT_SRICMD_TXINITIALOFFSET)
306#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET)
307#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x,S_LDT_SRICMD_TXINITIALOFFSET,M_LDT_SRICMD_TXINITIALOFFSET)
308
309#define M_LDT_SRICMD_LINKFREQDIRECT _SB_MAKEMASK1_32(31)
310
311/*
312 * LDT Error control and status register (Table 8-22) (Table 8-23)
313 */
314
315#define M_LDT_ERRCTL_PROTFATAL_EN _SB_MAKEMASK1_32(0)
316#define M_LDT_ERRCTL_PROTNONFATAL_EN _SB_MAKEMASK1_32(1)
317#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN _SB_MAKEMASK1_32(2)
318#define M_LDT_ERRCTL_OVFFATAL_EN _SB_MAKEMASK1_32(3)
319#define M_LDT_ERRCTL_OVFNONFATAL_EN _SB_MAKEMASK1_32(4)
320#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN _SB_MAKEMASK1_32(5)
321#define M_LDT_ERRCTL_EOCNXAFATAL_EN _SB_MAKEMASK1_32(6)
322#define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7)
323#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
324#define M_LDT_ERRCTL_CRCFATAL_EN _SB_MAKEMASK1_32(9)
325#define M_LDT_ERRCTL_CRCNONFATAL_EN _SB_MAKEMASK1_32(10)
326#define M_LDT_ERRCTL_SERRFATAL_EN _SB_MAKEMASK1_32(11)
327#define M_LDT_ERRCTL_SRCTAGFATAL_EN _SB_MAKEMASK1_32(12)
328#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13)
329#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
330#define M_LDT_ERRCTL_MAPNXAFATAL_EN _SB_MAKEMASK1_32(15)
331#define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16)
332#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
333
334#define M_LDT_ERRCTL_PROTOERR _SB_MAKEMASK1_32(24)
335#define M_LDT_ERRCTL_OVFERR _SB_MAKEMASK1_32(25)
336#define M_LDT_ERRCTL_EOCNXAERR _SB_MAKEMASK1_32(26)
337#define M_LDT_ERRCTL_SRCTAGERR _SB_MAKEMASK1_32(27)
338#define M_LDT_ERRCTL_MAPNXAERR _SB_MAKEMASK1_32(28)
339
340/*
341 * SRI Control register (Table 8-24, 8-25) Offset 0x6C
342 */
343
344#define S_LDT_SRICTRL_NEEDRESP 0
345#define M_LDT_SRICTRL_NEEDRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDRESP)
346#define V_LDT_SRICTRL_NEEDRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDRESP)
347#define G_LDT_SRICTRL_NEEDRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDRESP,M_LDT_SRICTRL_NEEDRESP)
348
349#define S_LDT_SRICTRL_NEEDNPREQ 2
350#define M_LDT_SRICTRL_NEEDNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDNPREQ)
351#define V_LDT_SRICTRL_NEEDNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ)
352#define G_LDT_SRICTRL_NEEDNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDNPREQ,M_LDT_SRICTRL_NEEDNPREQ)
353
354#define S_LDT_SRICTRL_NEEDPREQ 4
355#define M_LDT_SRICTRL_NEEDPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_NEEDPREQ)
356#define V_LDT_SRICTRL_NEEDPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ)
357#define G_LDT_SRICTRL_NEEDPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_NEEDPREQ,M_LDT_SRICTRL_NEEDPREQ)
358
359#define S_LDT_SRICTRL_WANTRESP 8
360#define M_LDT_SRICTRL_WANTRESP _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTRESP)
361#define V_LDT_SRICTRL_WANTRESP(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTRESP)
362#define G_LDT_SRICTRL_WANTRESP(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTRESP,M_LDT_SRICTRL_WANTRESP)
363
364#define S_LDT_SRICTRL_WANTNPREQ 10
365#define M_LDT_SRICTRL_WANTNPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTNPREQ)
366#define V_LDT_SRICTRL_WANTNPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ)
367#define G_LDT_SRICTRL_WANTNPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTNPREQ,M_LDT_SRICTRL_WANTNPREQ)
368
369#define S_LDT_SRICTRL_WANTPREQ 12
370#define M_LDT_SRICTRL_WANTPREQ _SB_MAKEMASK_32(2,S_LDT_SRICTRL_WANTPREQ)
371#define V_LDT_SRICTRL_WANTPREQ(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_WANTPREQ)
372#define G_LDT_SRICTRL_WANTPREQ(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_WANTPREQ,M_LDT_SRICTRL_WANTPREQ)
373
374#define S_LDT_SRICTRL_BUFRELSPACE 16
375#define M_LDT_SRICTRL_BUFRELSPACE _SB_MAKEMASK_32(4,S_LDT_SRICTRL_BUFRELSPACE)
376#define V_LDT_SRICTRL_BUFRELSPACE(x) _SB_MAKEVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE)
377#define G_LDT_SRICTRL_BUFRELSPACE(x) _SB_GETVALUE_32(x,S_LDT_SRICTRL_BUFRELSPACE,M_LDT_SRICTRL_BUFRELSPACE)
378
379/*
380 * LDT SRI Transmit Buffer Count register (Table 8-26)
381 */
382
383#define S_LDT_TXBUFCNT_PCMD 0
384#define M_LDT_TXBUFCNT_PCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PCMD)
385#define V_LDT_TXBUFCNT_PCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PCMD)
386#define G_LDT_TXBUFCNT_PCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PCMD,M_LDT_TXBUFCNT_PCMD)
387
388#define S_LDT_TXBUFCNT_PDATA 4
389#define M_LDT_TXBUFCNT_PDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_PDATA)
390#define V_LDT_TXBUFCNT_PDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_PDATA)
391#define G_LDT_TXBUFCNT_PDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_PDATA,M_LDT_TXBUFCNT_PDATA)
392
393#define S_LDT_TXBUFCNT_NPCMD 8
394#define M_LDT_TXBUFCNT_NPCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPCMD)
395#define V_LDT_TXBUFCNT_NPCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPCMD)
396#define G_LDT_TXBUFCNT_NPCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPCMD,M_LDT_TXBUFCNT_NPCMD)
397
398#define S_LDT_TXBUFCNT_NPDATA 12
399#define M_LDT_TXBUFCNT_NPDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_NPDATA)
400#define V_LDT_TXBUFCNT_NPDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_NPDATA)
401#define G_LDT_TXBUFCNT_NPDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_NPDATA,M_LDT_TXBUFCNT_NPDATA)
402
403#define S_LDT_TXBUFCNT_RCMD 16
404#define M_LDT_TXBUFCNT_RCMD _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RCMD)
405#define V_LDT_TXBUFCNT_RCMD(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RCMD)
406#define G_LDT_TXBUFCNT_RCMD(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RCMD,M_LDT_TXBUFCNT_RCMD)
407
408#define S_LDT_TXBUFCNT_RDATA 20
409#define M_LDT_TXBUFCNT_RDATA _SB_MAKEMASK_32(4,S_LDT_TXBUFCNT_RDATA)
410#define V_LDT_TXBUFCNT_RDATA(x) _SB_MAKEVALUE_32(x,S_LDT_TXBUFCNT_RDATA)
411#define G_LDT_TXBUFCNT_RDATA(x) _SB_GETVALUE_32(x,S_LDT_TXBUFCNT_RDATA,M_LDT_TXBUFCNT_RDATA)
412
413#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
414/*
415 * Additional Status Register
416 */
417
418#define S_LDT_ADDSTATUS_TGTDONE 0
419#define M_LDT_ADDSTATUS_TGTDONE _SB_MAKEMASK_32(8,S_LDT_ADDSTATUS_TGTDONE)
420#define V_LDT_ADDSTATUS_TGTDONE(x) _SB_MAKEVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE)
421#define G_LDT_ADDSTATUS_TGTDONE(x) _SB_GETVALUE_32(x,S_LDT_ADDSTATUS_TGTDONE,M_LDT_ADDSTATUS_TGTDONE)
422#endif /* 1250 PASS2 || 112x PASS1 */
423
424#endif
425
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
new file mode 100644
index 000000000000..81f603f03a98
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_mac.h
@@ -0,0 +1,643 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * MAC constants and macros File: sb1250_mac.h
5 *
6 * This module contains constants and macros for the SB1250's
7 * ethernet controllers.
8 *
9 * SB1250 specification level: User's manual 1/02/02
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34
35#ifndef _SB1250_MAC_H
36#define _SB1250_MAC_H
37
38#include "sb1250_defs.h"
39
40/* *********************************************************************
41 * Ethernet MAC Registers
42 ********************************************************************* */
43
44/*
45 * MAC Configuration Register (Table 9-13)
46 * Register: MAC_CFG_0
47 * Register: MAC_CFG_1
48 * Register: MAC_CFG_2
49 */
50
51
52#define M_MAC_RESERVED0 _SB_MAKEMASK1(0)
53#define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1)
54#define M_MAC_RETRY_EN _SB_MAKEMASK1(2)
55#define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3)
56#define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4)
57#define M_MAC_BURST_EN _SB_MAKEMASK1(5)
58
59#define S_MAC_TX_PAUSE _SB_MAKE64(6)
60#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE)
61#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE)
62
63#define K_MAC_TX_PAUSE_CNT_512 0
64#define K_MAC_TX_PAUSE_CNT_1K 1
65#define K_MAC_TX_PAUSE_CNT_2K 2
66#define K_MAC_TX_PAUSE_CNT_4K 3
67#define K_MAC_TX_PAUSE_CNT_8K 4
68#define K_MAC_TX_PAUSE_CNT_16K 5
69#define K_MAC_TX_PAUSE_CNT_32K 6
70#define K_MAC_TX_PAUSE_CNT_64K 7
71
72#define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512)
73#define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K)
74#define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K)
75#define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K)
76#define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K)
77#define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K)
78#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K)
79#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K)
80
81#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9)
82
83#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17)
84#define M_MAC_RESERVED2 _SB_MAKEMASK1(18)
85#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19)
86#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20)
87#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21)
88#define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22)
89#define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23)
90#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24)
91#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25)
92
93#define M_MAC_RESERVED3 _SB_MAKEMASK(6,26)
94
95#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32)
96#define M_MAC_HDX_EN _SB_MAKEMASK1(33)
97
98#define S_MAC_SPEED_SEL _SB_MAKE64(34)
99#define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL)
100#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL)
101#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL)
102
103#define K_MAC_SPEED_SEL_10MBPS 0
104#define K_MAC_SPEED_SEL_100MBPS 1
105#define K_MAC_SPEED_SEL_1000MBPS 2
106#define K_MAC_SPEED_SEL_RESERVED 3
107
108#define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS)
109#define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS)
110#define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS)
111#define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED)
112
113#define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36)
114#define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37)
115#define M_MAC_FAST_SYNC _SB_MAKEMASK1(38)
116#define M_MAC_SS_EN _SB_MAKEMASK1(39)
117
118#define S_MAC_BYPASS_CFG _SB_MAKE64(40)
119#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG)
120#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG)
121#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG)
122
123#define K_MAC_BYPASS_GMII 0
124#define K_MAC_BYPASS_ENCODED 1
125#define K_MAC_BYPASS_SOP 2
126#define K_MAC_BYPASS_EOP 3
127
128#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42)
129#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43)
130
131#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
132#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44)
133#endif /* 1250 PASS2 || 112x PASS1 */
134
135#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
136#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45)
137#endif /* 1250 PASS3 || 112x PASS1 */
138
139#define S_MAC_BYPASS_IFG _SB_MAKE64(46)
140#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG)
141#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG)
142#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG)
143
144#define K_MAC_FC_CMD_DISABLED 0
145#define K_MAC_FC_CMD_ENABLED 1
146#define K_MAC_FC_CMD_ENAB_FALSECARR 2
147
148#define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED)
149#define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED)
150#define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR)
151
152#define M_MAC_FC_SEL _SB_MAKEMASK1(54)
153
154#define S_MAC_FC_CMD _SB_MAKE64(55)
155#define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD)
156#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD)
157#define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD)
158
159#define S_MAC_RX_CH_SEL _SB_MAKE64(57)
160#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL)
161#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL)
162#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL)
163
164
165/*
166 * MAC Enable Registers
167 * Register: MAC_ENABLE_0
168 * Register: MAC_ENABLE_1
169 * Register: MAC_ENABLE_2
170 */
171
172#define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0)
173#define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1)
174#define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4)
175#define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5)
176
177#define M_MAC_PORT_RESET _SB_MAKEMASK1(8)
178
179#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10)
180#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11)
181#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12)
182#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13)
183
184/*
185 * MAC DMA Control Register
186 * Register: MAC_TXD_CTL_0
187 * Register: MAC_TXD_CTL_1
188 * Register: MAC_TXD_CTL_2
189 */
190
191#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0)
192#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0)
193#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0)
194#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0)
195
196#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4)
197#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1)
198#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1)
199#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1)
200
201/*
202 * MAC Fifo Threshhold registers (Table 9-14)
203 * Register: MAC_THRSH_CFG_0
204 * Register: MAC_THRSH_CFG_1
205 * Register: MAC_THRSH_CFG_2
206 */
207
208#define S_MAC_TX_WR_THRSH _SB_MAKE64(0)
209#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
210/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
211/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */
212#endif /* up to 1250 PASS1 */
213#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
214#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH)
215#endif /* 1250 PASS2 || 112x PASS1 */
216#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH)
217#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH)
218
219#define S_MAC_TX_RD_THRSH _SB_MAKE64(8)
220#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
221/* XXX: Can't enable, as it has the same name as a pass2+ define below. */
222/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */
223#endif /* up to 1250 PASS1 */
224#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
225#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH)
226#endif /* 1250 PASS2 || 112x PASS1 */
227#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH)
228#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH)
229
230#define S_MAC_TX_RL_THRSH _SB_MAKE64(16)
231#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH)
232#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH)
233#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH)
234
235#define S_MAC_RX_PL_THRSH _SB_MAKE64(24)
236#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH)
237#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH)
238#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH)
239
240#define S_MAC_RX_RD_THRSH _SB_MAKE64(32)
241#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH)
242#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH)
243#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH)
244
245#define S_MAC_RX_RL_THRSH _SB_MAKE64(40)
246#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH)
247#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH)
248#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH)
249
250#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
251#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56)
252#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH)
253#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH)
254#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH)
255#endif /* 1250 PASS2 || 112x PASS1 */
256
257/*
258 * MAC Frame Configuration Registers (Table 9-15)
259 * Register: MAC_FRAME_CFG_0
260 * Register: MAC_FRAME_CFG_1
261 * Register: MAC_FRAME_CFG_2
262 */
263
264/* XXXCGD: ??? Unused in pass2? */
265#define S_MAC_IFG_RX _SB_MAKE64(0)
266#define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX)
267#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX)
268#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX)
269
270#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
271#define S_MAC_PRE_LEN _SB_MAKE64(0)
272#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN)
273#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN)
274#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN)
275#endif /* 1250 PASS3 || 112x PASS1 */
276
277#define S_MAC_IFG_TX _SB_MAKE64(6)
278#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX)
279#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX)
280#define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX)
281
282#define S_MAC_IFG_THRSH _SB_MAKE64(12)
283#define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH)
284#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH)
285#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH)
286
287#define S_MAC_BACKOFF_SEL _SB_MAKE64(18)
288#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL)
289#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL)
290#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL)
291
292#define S_MAC_LFSR_SEED _SB_MAKE64(22)
293#define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED)
294#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED)
295#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED)
296
297#define S_MAC_SLOT_SIZE _SB_MAKE64(30)
298#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE)
299#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE)
300#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE)
301
302#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40)
303#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ)
304#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ)
305#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ)
306
307#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48)
308#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ)
309#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ)
310#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ)
311
312/*
313 * These constants are used to configure the fields within the Frame
314 * Configuration Register.
315 */
316
317#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */
318#define K_MAC_IFG_RX_100 _SB_MAKE64(0)
319#define K_MAC_IFG_RX_1000 _SB_MAKE64(0)
320
321#define K_MAC_IFG_TX_10 _SB_MAKE64(20)
322#define K_MAC_IFG_TX_100 _SB_MAKE64(20)
323#define K_MAC_IFG_TX_1000 _SB_MAKE64(8)
324
325#define K_MAC_IFG_THRSH_10 _SB_MAKE64(4)
326#define K_MAC_IFG_THRSH_100 _SB_MAKE64(4)
327#define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0)
328
329#define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0)
330#define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0)
331#define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0)
332
333#define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10)
334#define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100)
335#define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000)
336
337#define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10)
338#define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100)
339#define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000)
340
341#define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10)
342#define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100)
343#define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000)
344
345#define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10)
346#define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100)
347#define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000)
348
349#define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9)
350#define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64)
351#define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518)
352#define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216)
353
354#define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO)
355#define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT)
356#define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT)
357#define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO)
358
359/*
360 * MAC VLAN Tag Registers (Table 9-16)
361 * Register: MAC_VLANTAG_0
362 * Register: MAC_VLANTAG_1
363 * Register: MAC_VLANTAG_2
364 */
365
366#define S_MAC_VLAN_TAG _SB_MAKE64(0)
367#define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG)
368#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG)
369#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG)
370
371#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
372#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32)
373#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET)
374#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET)
375#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET)
376
377#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40)
378#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET)
379#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET)
380#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET)
381
382#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48)
383#endif /* 1250 PASS3 || 112x PASS1 */
384
385/*
386 * MAC Status Registers (Table 9-17)
387 * Also used for the MAC Interrupt Mask Register (Table 9-18)
388 * Register: MAC_STATUS_0
389 * Register: MAC_STATUS_1
390 * Register: MAC_STATUS_2
391 * Register: MAC_INT_MASK_0
392 * Register: MAC_INT_MASK_1
393 * Register: MAC_INT_MASK_2
394 */
395
396/*
397 * Use these constants to shift the appropriate channel
398 * into the CH0 position so the same tests can be used
399 * on each channel.
400 */
401
402#define S_MAC_RX_CH0 _SB_MAKE64(0)
403#define S_MAC_RX_CH1 _SB_MAKE64(8)
404#define S_MAC_TX_CH0 _SB_MAKE64(16)
405#define S_MAC_TX_CH1 _SB_MAKE64(24)
406
407#define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */
408#define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */
409
410/*
411 * These are the same as RX channel 0. The idea here
412 * is that you'll use one of the "S_" things above
413 * and pass just the six bits to a DMA-channel-specific ISR
414 */
415#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0)
416#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0)
417#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1)
418#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2)
419#define M_MAC_INT_HWM _SB_MAKEMASK1(3)
420#define M_MAC_INT_LWM _SB_MAKEMASK1(4)
421#define M_MAC_INT_DSCR _SB_MAKEMASK1(5)
422#define M_MAC_INT_ERR _SB_MAKEMASK1(6)
423#define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */
424#define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */
425
426/*
427 * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see
428 * also DMA_TX/DMA_RX in sb_regs.h).
429 */
430#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
431
432#define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx))
433#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx))
434#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx))
435#define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx))
436#define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx))
437#define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx))
438#define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx))
439#define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx))
440#define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx))
441#define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx))
442#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40)
443
444
445#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40)
446#define M_MAC_RX_OVRFL _SB_MAKEMASK1(41)
447#define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42)
448#define M_MAC_TX_OVRFL _SB_MAKEMASK1(43)
449#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44)
450#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45)
451#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46)
452#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
453#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */
454#endif /* 1250 PASS2 || 112x PASS1 */
455
456#define S_MAC_COUNTER_ADDR _SB_MAKE64(47)
457#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR)
458#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR)
459#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR)
460
461#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
462#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52)
463#endif /* 1250 PASS3 || 112x PASS1 */
464
465/*
466 * MAC Fifo Pointer Registers (Table 9-19) [Debug register]
467 * Register: MAC_FIFO_PTRS_0
468 * Register: MAC_FIFO_PTRS_1
469 * Register: MAC_FIFO_PTRS_2
470 */
471
472#define S_MAC_TX_WRPTR _SB_MAKE64(0)
473#define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR)
474#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR)
475#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR)
476
477#define S_MAC_TX_RDPTR _SB_MAKE64(8)
478#define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR)
479#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR)
480#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR)
481
482#define S_MAC_RX_WRPTR _SB_MAKE64(16)
483#define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR)
484#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR)
485#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR)
486
487#define S_MAC_RX_RDPTR _SB_MAKE64(24)
488#define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR)
489#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR)
490#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR)
491
492/*
493 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register]
494 * Register: MAC_EOPCNT_0
495 * Register: MAC_EOPCNT_1
496 * Register: MAC_EOPCNT_2
497 */
498
499#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0)
500#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER)
501#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER)
502#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER)
503
504#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8)
505#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER)
506#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER)
507#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER)
508
509/*
510 * MAC Recieve Address Filter Exact Match Registers (Table 9-21)
511 * Registers: MAC_ADDR0_0 through MAC_ADDR7_0
512 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1
513 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2
514 */
515
516/* No bitfields */
517
518/*
519 * MAC Receive Address Filter Mask Registers
520 * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1
521 * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1
522 * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1
523 */
524
525/* No bitfields */
526
527/*
528 * MAC Recieve Address Filter Hash Match Registers (Table 9-22)
529 * Registers: MAC_HASH0_0 through MAC_HASH7_0
530 * Registers: MAC_HASH0_1 through MAC_HASH7_1
531 * Registers: MAC_HASH0_2 through MAC_HASH7_2
532 */
533
534/* No bitfields */
535
536/*
537 * MAC Transmit Source Address Registers (Table 9-23)
538 * Register: MAC_ETHERNET_ADDR_0
539 * Register: MAC_ETHERNET_ADDR_1
540 * Register: MAC_ETHERNET_ADDR_2
541 */
542
543/* No bitfields */
544
545/*
546 * MAC Packet Type Configuration Register
547 * Register: MAC_TYPE_CFG_0
548 * Register: MAC_TYPE_CFG_1
549 * Register: MAC_TYPE_CFG_2
550 */
551
552#define S_TYPECFG_TYPESIZE _SB_MAKE64(16)
553
554#define S_TYPECFG_TYPE0 _SB_MAKE64(0)
555#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0)
556#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0)
557#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0)
558
559#define S_TYPECFG_TYPE1 _SB_MAKE64(0)
560#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1)
561#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1)
562#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1)
563
564#define S_TYPECFG_TYPE2 _SB_MAKE64(0)
565#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2)
566#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2)
567#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2)
568
569#define S_TYPECFG_TYPE3 _SB_MAKE64(0)
570#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3)
571#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3)
572#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3)
573
574/*
575 * MAC Receive Address Filter Control Registers (Table 9-24)
576 * Register: MAC_ADFILTER_CFG_0
577 * Register: MAC_ADFILTER_CFG_1
578 * Register: MAC_ADFILTER_CFG_2
579 */
580
581#define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0)
582#define M_MAC_UCAST_EN _SB_MAKEMASK1(1)
583#define M_MAC_UCAST_INV _SB_MAKEMASK1(2)
584#define M_MAC_MCAST_EN _SB_MAKEMASK1(3)
585#define M_MAC_MCAST_INV _SB_MAKEMASK1(4)
586#define M_MAC_BCAST_EN _SB_MAKEMASK1(5)
587#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6)
588#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
589#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7)
590#endif /* 1250 PASS2 || 112x PASS1 */
591
592#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8)
593#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET)
594#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET)
595#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET)
596
597#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
598#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16)
599#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET)
600#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET)
601#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET)
602
603#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24)
604#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET)
605#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET)
606#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET)
607
608#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32)
609#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33)
610
611#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34)
612#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL)
613#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL)
614#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL)
615#endif /* 1250 PASS3 || 112x PASS1 */
616
617/*
618 * MAC Receive Channel Select Registers (Table 9-25)
619 */
620
621/* no bitfields */
622
623/*
624 * MAC MII Management Interface Registers (Table 9-26)
625 * Register: MAC_MDIO_0
626 * Register: MAC_MDIO_1
627 * Register: MAC_MDIO_2
628 */
629
630#define S_MAC_MDC 0
631#define S_MAC_MDIO_DIR 1
632#define S_MAC_MDIO_OUT 2
633#define S_MAC_GENC 3
634#define S_MAC_MDIO_IN 4
635
636#define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC)
637#define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR)
638#define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR)
639#define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT)
640#define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC)
641#define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN)
642
643#endif
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
new file mode 100644
index 000000000000..93a48334b874
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_mc.h
@@ -0,0 +1,548 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * Memory Controller constants File: sb1250_mc.h
5 *
6 * This module contains constants and macros useful for
7 * programming the memory controller.
8 *
9 * SB1250 specification level: User's manual 1/02/02
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34
35#ifndef _SB1250_MC_H
36#define _SB1250_MC_H
37
38#include "sb1250_defs.h"
39
40/*
41 * Memory Channel Config Register (table 6-14)
42 */
43
44#define S_MC_RESERVED0 0
45#define M_MC_RESERVED0 _SB_MAKEMASK(8,S_MC_RESERVED0)
46
47#define S_MC_CHANNEL_SEL 8
48#define M_MC_CHANNEL_SEL _SB_MAKEMASK(8,S_MC_CHANNEL_SEL)
49#define V_MC_CHANNEL_SEL(x) _SB_MAKEVALUE(x,S_MC_CHANNEL_SEL)
50#define G_MC_CHANNEL_SEL(x) _SB_GETVALUE(x,S_MC_CHANNEL_SEL,M_MC_CHANNEL_SEL)
51
52#define S_MC_BANK0_MAP 16
53#define M_MC_BANK0_MAP _SB_MAKEMASK(4,S_MC_BANK0_MAP)
54#define V_MC_BANK0_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK0_MAP)
55#define G_MC_BANK0_MAP(x) _SB_GETVALUE(x,S_MC_BANK0_MAP,M_MC_BANK0_MAP)
56
57#define K_MC_BANK0_MAP_DEFAULT 0x00
58#define V_MC_BANK0_MAP_DEFAULT V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
59
60#define S_MC_BANK1_MAP 20
61#define M_MC_BANK1_MAP _SB_MAKEMASK(4,S_MC_BANK1_MAP)
62#define V_MC_BANK1_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK1_MAP)
63#define G_MC_BANK1_MAP(x) _SB_GETVALUE(x,S_MC_BANK1_MAP,M_MC_BANK1_MAP)
64
65#define K_MC_BANK1_MAP_DEFAULT 0x08
66#define V_MC_BANK1_MAP_DEFAULT V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
67
68#define S_MC_BANK2_MAP 24
69#define M_MC_BANK2_MAP _SB_MAKEMASK(4,S_MC_BANK2_MAP)
70#define V_MC_BANK2_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK2_MAP)
71#define G_MC_BANK2_MAP(x) _SB_GETVALUE(x,S_MC_BANK2_MAP,M_MC_BANK2_MAP)
72
73#define K_MC_BANK2_MAP_DEFAULT 0x09
74#define V_MC_BANK2_MAP_DEFAULT V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
75
76#define S_MC_BANK3_MAP 28
77#define M_MC_BANK3_MAP _SB_MAKEMASK(4,S_MC_BANK3_MAP)
78#define V_MC_BANK3_MAP(x) _SB_MAKEVALUE(x,S_MC_BANK3_MAP)
79#define G_MC_BANK3_MAP(x) _SB_GETVALUE(x,S_MC_BANK3_MAP,M_MC_BANK3_MAP)
80
81#define K_MC_BANK3_MAP_DEFAULT 0x0C
82#define V_MC_BANK3_MAP_DEFAULT V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
83
84#define M_MC_RESERVED1 _SB_MAKEMASK(8,32)
85
86#define S_MC_QUEUE_SIZE 40
87#define M_MC_QUEUE_SIZE _SB_MAKEMASK(4,S_MC_QUEUE_SIZE)
88#define V_MC_QUEUE_SIZE(x) _SB_MAKEVALUE(x,S_MC_QUEUE_SIZE)
89#define G_MC_QUEUE_SIZE(x) _SB_GETVALUE(x,S_MC_QUEUE_SIZE,M_MC_QUEUE_SIZE)
90#define V_MC_QUEUE_SIZE_DEFAULT V_MC_QUEUE_SIZE(0x0A)
91
92#define S_MC_AGE_LIMIT 44
93#define M_MC_AGE_LIMIT _SB_MAKEMASK(4,S_MC_AGE_LIMIT)
94#define V_MC_AGE_LIMIT(x) _SB_MAKEVALUE(x,S_MC_AGE_LIMIT)
95#define G_MC_AGE_LIMIT(x) _SB_GETVALUE(x,S_MC_AGE_LIMIT,M_MC_AGE_LIMIT)
96#define V_MC_AGE_LIMIT_DEFAULT V_MC_AGE_LIMIT(8)
97
98#define S_MC_WR_LIMIT 48
99#define M_MC_WR_LIMIT _SB_MAKEMASK(4,S_MC_WR_LIMIT)
100#define V_MC_WR_LIMIT(x) _SB_MAKEVALUE(x,S_MC_WR_LIMIT)
101#define G_MC_WR_LIMIT(x) _SB_GETVALUE(x,S_MC_WR_LIMIT,M_MC_WR_LIMIT)
102#define V_MC_WR_LIMIT_DEFAULT V_MC_WR_LIMIT(5)
103
104#define M_MC_IOB1HIGHPRIORITY _SB_MAKEMASK1(52)
105
106#define M_MC_RESERVED2 _SB_MAKEMASK(3,53)
107
108#define S_MC_CS_MODE 56
109#define M_MC_CS_MODE _SB_MAKEMASK(4,S_MC_CS_MODE)
110#define V_MC_CS_MODE(x) _SB_MAKEVALUE(x,S_MC_CS_MODE)
111#define G_MC_CS_MODE(x) _SB_GETVALUE(x,S_MC_CS_MODE,M_MC_CS_MODE)
112
113#define K_MC_CS_MODE_MSB_CS 0
114#define K_MC_CS_MODE_INTLV_CS 15
115#define K_MC_CS_MODE_MIXED_CS_10 12
116#define K_MC_CS_MODE_MIXED_CS_30 6
117#define K_MC_CS_MODE_MIXED_CS_32 3
118
119#define V_MC_CS_MODE_MSB_CS V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
120#define V_MC_CS_MODE_INTLV_CS V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
121#define V_MC_CS_MODE_MIXED_CS_10 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
122#define V_MC_CS_MODE_MIXED_CS_30 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
123#define V_MC_CS_MODE_MIXED_CS_32 V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
124
125#define M_MC_ECC_DISABLE _SB_MAKEMASK1(60)
126#define M_MC_BERR_DISABLE _SB_MAKEMASK1(61)
127#define M_MC_FORCE_SEQ _SB_MAKEMASK1(62)
128#define M_MC_DEBUG _SB_MAKEMASK1(63)
129
130#define V_MC_CONFIG_DEFAULT V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
131 V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
132 V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \
133 M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
134
135
136/*
137 * Memory clock config register (Table 6-15)
138 *
139 * Note: this field has been updated to be consistent with the errata to 0.2
140 */
141
142#define S_MC_CLK_RATIO 0
143#define M_MC_CLK_RATIO _SB_MAKEMASK(4,S_MC_CLK_RATIO)
144#define V_MC_CLK_RATIO(x) _SB_MAKEVALUE(x,S_MC_CLK_RATIO)
145#define G_MC_CLK_RATIO(x) _SB_GETVALUE(x,S_MC_CLK_RATIO,M_MC_CLK_RATIO)
146
147#define K_MC_CLK_RATIO_2X 4
148#define K_MC_CLK_RATIO_25X 5
149#define K_MC_CLK_RATIO_3X 6
150#define K_MC_CLK_RATIO_35X 7
151#define K_MC_CLK_RATIO_4X 8
152#define K_MC_CLK_RATIO_45X 9
153
154#define V_MC_CLK_RATIO_2X V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
155#define V_MC_CLK_RATIO_25X V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
156#define V_MC_CLK_RATIO_3X V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
157#define V_MC_CLK_RATIO_35X V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
158#define V_MC_CLK_RATIO_4X V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
159#define V_MC_CLK_RATIO_45X V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
160#define V_MC_CLK_RATIO_DEFAULT V_MC_CLK_RATIO_25X
161
162#define S_MC_REF_RATE 8
163#define M_MC_REF_RATE _SB_MAKEMASK(8,S_MC_REF_RATE)
164#define V_MC_REF_RATE(x) _SB_MAKEVALUE(x,S_MC_REF_RATE)
165#define G_MC_REF_RATE(x) _SB_GETVALUE(x,S_MC_REF_RATE,M_MC_REF_RATE)
166
167#define K_MC_REF_RATE_100MHz 0x62
168#define K_MC_REF_RATE_133MHz 0x81
169#define K_MC_REF_RATE_200MHz 0xC4
170
171#define V_MC_REF_RATE_100MHz V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
172#define V_MC_REF_RATE_133MHz V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
173#define V_MC_REF_RATE_200MHz V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
174#define V_MC_REF_RATE_DEFAULT V_MC_REF_RATE_100MHz
175
176#define S_MC_CLOCK_DRIVE 16
177#define M_MC_CLOCK_DRIVE _SB_MAKEMASK(4,S_MC_CLOCK_DRIVE)
178#define V_MC_CLOCK_DRIVE(x) _SB_MAKEVALUE(x,S_MC_CLOCK_DRIVE)
179#define G_MC_CLOCK_DRIVE(x) _SB_GETVALUE(x,S_MC_CLOCK_DRIVE,M_MC_CLOCK_DRIVE)
180#define V_MC_CLOCK_DRIVE_DEFAULT V_MC_CLOCK_DRIVE(0xF)
181
182#define S_MC_DATA_DRIVE 20
183#define M_MC_DATA_DRIVE _SB_MAKEMASK(4,S_MC_DATA_DRIVE)
184#define V_MC_DATA_DRIVE(x) _SB_MAKEVALUE(x,S_MC_DATA_DRIVE)
185#define G_MC_DATA_DRIVE(x) _SB_GETVALUE(x,S_MC_DATA_DRIVE,M_MC_DATA_DRIVE)
186#define V_MC_DATA_DRIVE_DEFAULT V_MC_DATA_DRIVE(0x0)
187
188#define S_MC_ADDR_DRIVE 24
189#define M_MC_ADDR_DRIVE _SB_MAKEMASK(4,S_MC_ADDR_DRIVE)
190#define V_MC_ADDR_DRIVE(x) _SB_MAKEVALUE(x,S_MC_ADDR_DRIVE)
191#define G_MC_ADDR_DRIVE(x) _SB_GETVALUE(x,S_MC_ADDR_DRIVE,M_MC_ADDR_DRIVE)
192#define V_MC_ADDR_DRIVE_DEFAULT V_MC_ADDR_DRIVE(0x0)
193
194#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
195#define M_MC_REF_DISABLE _SB_MAKEMASK1(30)
196#endif /* 1250 PASS3 || 112x PASS1 */
197
198#define M_MC_DLL_BYPASS _SB_MAKEMASK1(31)
199
200#define S_MC_DQI_SKEW 32
201#define M_MC_DQI_SKEW _SB_MAKEMASK(8,S_MC_DQI_SKEW)
202#define V_MC_DQI_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQI_SKEW)
203#define G_MC_DQI_SKEW(x) _SB_GETVALUE(x,S_MC_DQI_SKEW,M_MC_DQI_SKEW)
204#define V_MC_DQI_SKEW_DEFAULT V_MC_DQI_SKEW(0)
205
206#define S_MC_DQO_SKEW 40
207#define M_MC_DQO_SKEW _SB_MAKEMASK(8,S_MC_DQO_SKEW)
208#define V_MC_DQO_SKEW(x) _SB_MAKEVALUE(x,S_MC_DQO_SKEW)
209#define G_MC_DQO_SKEW(x) _SB_GETVALUE(x,S_MC_DQO_SKEW,M_MC_DQO_SKEW)
210#define V_MC_DQO_SKEW_DEFAULT V_MC_DQO_SKEW(0)
211
212#define S_MC_ADDR_SKEW 48
213#define M_MC_ADDR_SKEW _SB_MAKEMASK(8,S_MC_ADDR_SKEW)
214#define V_MC_ADDR_SKEW(x) _SB_MAKEVALUE(x,S_MC_ADDR_SKEW)
215#define G_MC_ADDR_SKEW(x) _SB_GETVALUE(x,S_MC_ADDR_SKEW,M_MC_ADDR_SKEW)
216#define V_MC_ADDR_SKEW_DEFAULT V_MC_ADDR_SKEW(0x0F)
217
218#define S_MC_DLL_DEFAULT 56
219#define M_MC_DLL_DEFAULT _SB_MAKEMASK(8,S_MC_DLL_DEFAULT)
220#define V_MC_DLL_DEFAULT(x) _SB_MAKEVALUE(x,S_MC_DLL_DEFAULT)
221#define G_MC_DLL_DEFAULT(x) _SB_GETVALUE(x,S_MC_DLL_DEFAULT,M_MC_DLL_DEFAULT)
222#define V_MC_DLL_DEFAULT_DEFAULT V_MC_DLL_DEFAULT(0x10)
223
224#define V_MC_CLKCONFIG_DEFAULT V_MC_DLL_DEFAULT_DEFAULT | \
225 V_MC_ADDR_SKEW_DEFAULT | \
226 V_MC_DQO_SKEW_DEFAULT | \
227 V_MC_DQI_SKEW_DEFAULT | \
228 V_MC_ADDR_DRIVE_DEFAULT | \
229 V_MC_DATA_DRIVE_DEFAULT | \
230 V_MC_CLOCK_DRIVE_DEFAULT | \
231 V_MC_REF_RATE_DEFAULT
232
233
234
235/*
236 * DRAM Command Register (Table 6-13)
237 */
238
239#define S_MC_COMMAND 0
240#define M_MC_COMMAND _SB_MAKEMASK(4,S_MC_COMMAND)
241#define V_MC_COMMAND(x) _SB_MAKEVALUE(x,S_MC_COMMAND)
242#define G_MC_COMMAND(x) _SB_GETVALUE(x,S_MC_COMMAND,M_MC_COMMAND)
243
244#define K_MC_COMMAND_EMRS 0
245#define K_MC_COMMAND_MRS 1
246#define K_MC_COMMAND_PRE 2
247#define K_MC_COMMAND_AR 3
248#define K_MC_COMMAND_SETRFSH 4
249#define K_MC_COMMAND_CLRRFSH 5
250#define K_MC_COMMAND_SETPWRDN 6
251#define K_MC_COMMAND_CLRPWRDN 7
252
253#define V_MC_COMMAND_EMRS V_MC_COMMAND(K_MC_COMMAND_EMRS)
254#define V_MC_COMMAND_MRS V_MC_COMMAND(K_MC_COMMAND_MRS)
255#define V_MC_COMMAND_PRE V_MC_COMMAND(K_MC_COMMAND_PRE)
256#define V_MC_COMMAND_AR V_MC_COMMAND(K_MC_COMMAND_AR)
257#define V_MC_COMMAND_SETRFSH V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
258#define V_MC_COMMAND_CLRRFSH V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
259#define V_MC_COMMAND_SETPWRDN V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
260#define V_MC_COMMAND_CLRPWRDN V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
261
262#define M_MC_CS0 _SB_MAKEMASK1(4)
263#define M_MC_CS1 _SB_MAKEMASK1(5)
264#define M_MC_CS2 _SB_MAKEMASK1(6)
265#define M_MC_CS3 _SB_MAKEMASK1(7)
266
267/*
268 * DRAM Mode Register (Table 6-14)
269 */
270
271#define S_MC_EMODE 0
272#define M_MC_EMODE _SB_MAKEMASK(15,S_MC_EMODE)
273#define V_MC_EMODE(x) _SB_MAKEVALUE(x,S_MC_EMODE)
274#define G_MC_EMODE(x) _SB_GETVALUE(x,S_MC_EMODE,M_MC_EMODE)
275#define V_MC_EMODE_DEFAULT V_MC_EMODE(0)
276
277#define S_MC_MODE 16
278#define M_MC_MODE _SB_MAKEMASK(15,S_MC_MODE)
279#define V_MC_MODE(x) _SB_MAKEVALUE(x,S_MC_MODE)
280#define G_MC_MODE(x) _SB_GETVALUE(x,S_MC_MODE,M_MC_MODE)
281#define V_MC_MODE_DEFAULT V_MC_MODE(0x22)
282
283#define S_MC_DRAM_TYPE 32
284#define M_MC_DRAM_TYPE _SB_MAKEMASK(3,S_MC_DRAM_TYPE)
285#define V_MC_DRAM_TYPE(x) _SB_MAKEVALUE(x,S_MC_DRAM_TYPE)
286#define G_MC_DRAM_TYPE(x) _SB_GETVALUE(x,S_MC_DRAM_TYPE,M_MC_DRAM_TYPE)
287
288#define K_MC_DRAM_TYPE_JEDEC 0
289#define K_MC_DRAM_TYPE_FCRAM 1
290#define K_MC_DRAM_TYPE_SGRAM 2
291
292#define V_MC_DRAM_TYPE_JEDEC V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
293#define V_MC_DRAM_TYPE_FCRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
294#define V_MC_DRAM_TYPE_SGRAM V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)
295
296#define M_MC_EXTERNALDECODE _SB_MAKEMASK1(35)
297
298#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
299#define M_MC_PRE_ON_A8 _SB_MAKEMASK1(36)
300#define M_MC_RAM_WITH_A13 _SB_MAKEMASK1(38)
301#endif /* 1250 PASS3 || 112x PASS1 */
302
303
304
305/*
306 * SDRAM Timing Register (Table 6-15)
307 */
308
309#define M_MC_w2rIDLE_TWOCYCLES _SB_MAKEMASK1(60)
310#define M_MC_r2wIDLE_TWOCYCLES _SB_MAKEMASK1(61)
311#define M_MC_r2rIDLE_TWOCYCLES _SB_MAKEMASK1(62)
312
313#define S_MC_tFIFO 56
314#define M_MC_tFIFO _SB_MAKEMASK(4,S_MC_tFIFO)
315#define V_MC_tFIFO(x) _SB_MAKEVALUE(x,S_MC_tFIFO)
316#define G_MC_tFIFO(x) _SB_GETVALUE(x,S_MC_tFIFO,M_MC_tFIFO)
317#define K_MC_tFIFO_DEFAULT 1
318#define V_MC_tFIFO_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
319
320#define S_MC_tRFC 52
321#define M_MC_tRFC _SB_MAKEMASK(4,S_MC_tRFC)
322#define V_MC_tRFC(x) _SB_MAKEVALUE(x,S_MC_tRFC)
323#define G_MC_tRFC(x) _SB_GETVALUE(x,S_MC_tRFC,M_MC_tRFC)
324#define K_MC_tRFC_DEFAULT 12
325#define V_MC_tRFC_DEFAULT V_MC_tRFC(K_MC_tRFC_DEFAULT)
326
327#define S_MC_tCwCr 40
328#define M_MC_tCwCr _SB_MAKEMASK(4,S_MC_tCwCr)
329#define V_MC_tCwCr(x) _SB_MAKEVALUE(x,S_MC_tCwCr)
330#define G_MC_tCwCr(x) _SB_GETVALUE(x,S_MC_tCwCr,M_MC_tCwCr)
331#define K_MC_tCwCr_DEFAULT 4
332#define V_MC_tCwCr_DEFAULT V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
333
334#define S_MC_tRCr 28
335#define M_MC_tRCr _SB_MAKEMASK(4,S_MC_tRCr)
336#define V_MC_tRCr(x) _SB_MAKEVALUE(x,S_MC_tRCr)
337#define G_MC_tRCr(x) _SB_GETVALUE(x,S_MC_tRCr,M_MC_tRCr)
338#define K_MC_tRCr_DEFAULT 9
339#define V_MC_tRCr_DEFAULT V_MC_tRCr(K_MC_tRCr_DEFAULT)
340
341#define S_MC_tRCw 24
342#define M_MC_tRCw _SB_MAKEMASK(4,S_MC_tRCw)
343#define V_MC_tRCw(x) _SB_MAKEVALUE(x,S_MC_tRCw)
344#define G_MC_tRCw(x) _SB_GETVALUE(x,S_MC_tRCw,M_MC_tRCw)
345#define K_MC_tRCw_DEFAULT 10
346#define V_MC_tRCw_DEFAULT V_MC_tRCw(K_MC_tRCw_DEFAULT)
347
348#define S_MC_tRRD 20
349#define M_MC_tRRD _SB_MAKEMASK(4,S_MC_tRRD)
350#define V_MC_tRRD(x) _SB_MAKEVALUE(x,S_MC_tRRD)
351#define G_MC_tRRD(x) _SB_GETVALUE(x,S_MC_tRRD,M_MC_tRRD)
352#define K_MC_tRRD_DEFAULT 2
353#define V_MC_tRRD_DEFAULT V_MC_tRRD(K_MC_tRRD_DEFAULT)
354
355#define S_MC_tRP 16
356#define M_MC_tRP _SB_MAKEMASK(4,S_MC_tRP)
357#define V_MC_tRP(x) _SB_MAKEVALUE(x,S_MC_tRP)
358#define G_MC_tRP(x) _SB_GETVALUE(x,S_MC_tRP,M_MC_tRP)
359#define K_MC_tRP_DEFAULT 4
360#define V_MC_tRP_DEFAULT V_MC_tRP(K_MC_tRP_DEFAULT)
361
362#define S_MC_tCwD 8
363#define M_MC_tCwD _SB_MAKEMASK(4,S_MC_tCwD)
364#define V_MC_tCwD(x) _SB_MAKEVALUE(x,S_MC_tCwD)
365#define G_MC_tCwD(x) _SB_GETVALUE(x,S_MC_tCwD,M_MC_tCwD)
366#define K_MC_tCwD_DEFAULT 1
367#define V_MC_tCwD_DEFAULT V_MC_tCwD(K_MC_tCwD_DEFAULT)
368
369#define M_tCrDh _SB_MAKEMASK1(7)
370#define M_MC_tCrDh M_tCrDh
371
372#define S_MC_tCrD 4
373#define M_MC_tCrD _SB_MAKEMASK(3,S_MC_tCrD)
374#define V_MC_tCrD(x) _SB_MAKEVALUE(x,S_MC_tCrD)
375#define G_MC_tCrD(x) _SB_GETVALUE(x,S_MC_tCrD,M_MC_tCrD)
376#define K_MC_tCrD_DEFAULT 2
377#define V_MC_tCrD_DEFAULT V_MC_tCrD(K_MC_tCrD_DEFAULT)
378
379#define S_MC_tRCD 0
380#define M_MC_tRCD _SB_MAKEMASK(4,S_MC_tRCD)
381#define V_MC_tRCD(x) _SB_MAKEVALUE(x,S_MC_tRCD)
382#define G_MC_tRCD(x) _SB_GETVALUE(x,S_MC_tRCD,M_MC_tRCD)
383#define K_MC_tRCD_DEFAULT 3
384#define V_MC_tRCD_DEFAULT V_MC_tRCD(K_MC_tRCD_DEFAULT)
385
386#define V_MC_TIMING_DEFAULT V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
387 V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
388 V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
389 V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
390 V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
391 V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
392 V_MC_tRP(K_MC_tRP_DEFAULT) | \
393 V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
394 V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
395 V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
396 M_MC_r2rIDLE_TWOCYCLES
397
398/*
399 * Errata says these are not the default
400 * M_MC_w2rIDLE_TWOCYCLES | \
401 * M_MC_r2wIDLE_TWOCYCLES | \
402 */
403
404
405/*
406 * Chip Select Start Address Register (Table 6-17)
407 */
408
409#define S_MC_CS0_START 0
410#define M_MC_CS0_START _SB_MAKEMASK(16,S_MC_CS0_START)
411#define V_MC_CS0_START(x) _SB_MAKEVALUE(x,S_MC_CS0_START)
412#define G_MC_CS0_START(x) _SB_GETVALUE(x,S_MC_CS0_START,M_MC_CS0_START)
413
414#define S_MC_CS1_START 16
415#define M_MC_CS1_START _SB_MAKEMASK(16,S_MC_CS1_START)
416#define V_MC_CS1_START(x) _SB_MAKEVALUE(x,S_MC_CS1_START)
417#define G_MC_CS1_START(x) _SB_GETVALUE(x,S_MC_CS1_START,M_MC_CS1_START)
418
419#define S_MC_CS2_START 32
420#define M_MC_CS2_START _SB_MAKEMASK(16,S_MC_CS2_START)
421#define V_MC_CS2_START(x) _SB_MAKEVALUE(x,S_MC_CS2_START)
422#define G_MC_CS2_START(x) _SB_GETVALUE(x,S_MC_CS2_START,M_MC_CS2_START)
423
424#define S_MC_CS3_START 48
425#define M_MC_CS3_START _SB_MAKEMASK(16,S_MC_CS3_START)
426#define V_MC_CS3_START(x) _SB_MAKEVALUE(x,S_MC_CS3_START)
427#define G_MC_CS3_START(x) _SB_GETVALUE(x,S_MC_CS3_START,M_MC_CS3_START)
428
429/*
430 * Chip Select End Address Register (Table 6-18)
431 */
432
433#define S_MC_CS0_END 0
434#define M_MC_CS0_END _SB_MAKEMASK(16,S_MC_CS0_END)
435#define V_MC_CS0_END(x) _SB_MAKEVALUE(x,S_MC_CS0_END)
436#define G_MC_CS0_END(x) _SB_GETVALUE(x,S_MC_CS0_END,M_MC_CS0_END)
437
438#define S_MC_CS1_END 16
439#define M_MC_CS1_END _SB_MAKEMASK(16,S_MC_CS1_END)
440#define V_MC_CS1_END(x) _SB_MAKEVALUE(x,S_MC_CS1_END)
441#define G_MC_CS1_END(x) _SB_GETVALUE(x,S_MC_CS1_END,M_MC_CS1_END)
442
443#define S_MC_CS2_END 32
444#define M_MC_CS2_END _SB_MAKEMASK(16,S_MC_CS2_END)
445#define V_MC_CS2_END(x) _SB_MAKEVALUE(x,S_MC_CS2_END)
446#define G_MC_CS2_END(x) _SB_GETVALUE(x,S_MC_CS2_END,M_MC_CS2_END)
447
448#define S_MC_CS3_END 48
449#define M_MC_CS3_END _SB_MAKEMASK(16,S_MC_CS3_END)
450#define V_MC_CS3_END(x) _SB_MAKEVALUE(x,S_MC_CS3_END)
451#define G_MC_CS3_END(x) _SB_GETVALUE(x,S_MC_CS3_END,M_MC_CS3_END)
452
453/*
454 * Chip Select Interleave Register (Table 6-19)
455 */
456
457#define S_MC_INTLV_RESERVED 0
458#define M_MC_INTLV_RESERVED _SB_MAKEMASK(5,S_MC_INTLV_RESERVED)
459
460#define S_MC_INTERLEAVE 7
461#define M_MC_INTERLEAVE _SB_MAKEMASK(18,S_MC_INTERLEAVE)
462#define V_MC_INTERLEAVE(x) _SB_MAKEVALUE(x,S_MC_INTERLEAVE)
463
464#define S_MC_INTLV_MBZ 25
465#define M_MC_INTLV_MBZ _SB_MAKEMASK(39,S_MC_INTLV_MBZ)
466
467/*
468 * Row Address Bits Register (Table 6-20)
469 */
470
471#define S_MC_RAS_RESERVED 0
472#define M_MC_RAS_RESERVED _SB_MAKEMASK(5,S_MC_RAS_RESERVED)
473
474#define S_MC_RAS_SELECT 12
475#define M_MC_RAS_SELECT _SB_MAKEMASK(25,S_MC_RAS_SELECT)
476#define V_MC_RAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_RAS_SELECT)
477
478#define S_MC_RAS_MBZ 37
479#define M_MC_RAS_MBZ _SB_MAKEMASK(27,S_MC_RAS_MBZ)
480
481
482/*
483 * Column Address Bits Register (Table 6-21)
484 */
485
486#define S_MC_CAS_RESERVED 0
487#define M_MC_CAS_RESERVED _SB_MAKEMASK(5,S_MC_CAS_RESERVED)
488
489#define S_MC_CAS_SELECT 5
490#define M_MC_CAS_SELECT _SB_MAKEMASK(18,S_MC_CAS_SELECT)
491#define V_MC_CAS_SELECT(x) _SB_MAKEVALUE(x,S_MC_CAS_SELECT)
492
493#define S_MC_CAS_MBZ 23
494#define M_MC_CAS_MBZ _SB_MAKEMASK(41,S_MC_CAS_MBZ)
495
496
497/*
498 * Bank Address Address Bits Register (Table 6-22)
499 */
500
501#define S_MC_BA_RESERVED 0
502#define M_MC_BA_RESERVED _SB_MAKEMASK(5,S_MC_BA_RESERVED)
503
504#define S_MC_BA_SELECT 5
505#define M_MC_BA_SELECT _SB_MAKEMASK(20,S_MC_BA_SELECT)
506#define V_MC_BA_SELECT(x) _SB_MAKEVALUE(x,S_MC_BA_SELECT)
507
508#define S_MC_BA_MBZ 25
509#define M_MC_BA_MBZ _SB_MAKEMASK(39,S_MC_BA_MBZ)
510
511/*
512 * Chip Select Attribute Register (Table 6-23)
513 */
514
515#define K_MC_CS_ATTR_CLOSED 0
516#define K_MC_CS_ATTR_CASCHECK 1
517#define K_MC_CS_ATTR_HINT 2
518#define K_MC_CS_ATTR_OPEN 3
519
520#define S_MC_CS0_PAGE 0
521#define M_MC_CS0_PAGE _SB_MAKEMASK(2,S_MC_CS0_PAGE)
522#define V_MC_CS0_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS0_PAGE)
523#define G_MC_CS0_PAGE(x) _SB_GETVALUE(x,S_MC_CS0_PAGE,M_MC_CS0_PAGE)
524
525#define S_MC_CS1_PAGE 16
526#define M_MC_CS1_PAGE _SB_MAKEMASK(2,S_MC_CS1_PAGE)
527#define V_MC_CS1_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS1_PAGE)
528#define G_MC_CS1_PAGE(x) _SB_GETVALUE(x,S_MC_CS1_PAGE,M_MC_CS1_PAGE)
529
530#define S_MC_CS2_PAGE 32
531#define M_MC_CS2_PAGE _SB_MAKEMASK(2,S_MC_CS2_PAGE)
532#define V_MC_CS2_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS2_PAGE)
533#define G_MC_CS2_PAGE(x) _SB_GETVALUE(x,S_MC_CS2_PAGE,M_MC_CS2_PAGE)
534
535#define S_MC_CS3_PAGE 48
536#define M_MC_CS3_PAGE _SB_MAKEMASK(2,S_MC_CS3_PAGE)
537#define V_MC_CS3_PAGE(x) _SB_MAKEVALUE(x,S_MC_CS3_PAGE)
538#define G_MC_CS3_PAGE(x) _SB_GETVALUE(x,S_MC_CS3_PAGE,M_MC_CS3_PAGE)
539
540/*
541 * ECC Test ECC Register (Table 6-25)
542 */
543
544#define S_MC_ECC_INVERT 0
545#define M_MC_ECC_INVERT _SB_MAKEMASK(8,S_MC_ECC_INVERT)
546
547
548#endif
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
new file mode 100644
index 000000000000..5d496c6faba6
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_regs.h
@@ -0,0 +1,836 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * Register Definitions File: sb1250_regs.h
5 *
6 * This module contains the addresses of the on-chip peripherals
7 * on the SB1250.
8 *
9 * SB1250 specification level: 01/02/2002
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34
35#ifndef _SB1250_REGS_H
36#define _SB1250_REGS_H
37
38#include "sb1250_defs.h"
39
40
41/* *********************************************************************
42 * Some general notes:
43 *
44 * For the most part, when there is more than one peripheral
45 * of the same type on the SOC, the constants below will be
46 * offsets from the base of each peripheral. For example,
47 * the MAC registers are described as offsets from the first
48 * MAC register, and there will be a MAC_REGISTER() macro
49 * to calculate the base address of a given MAC.
50 *
51 * The information in this file is based on the SB1250 SOC
52 * manual version 0.2, July 2000.
53 ********************************************************************* */
54
55
56/* *********************************************************************
57 * Memory Controller Registers
58 ********************************************************************* */
59
60/*
61 * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
62 * since there is one reg there (but it could get its addr/offset constant).
63 */
64#define A_MC_BASE_0 0x0010051000
65#define A_MC_BASE_1 0x0010052000
66#define MC_REGISTER_SPACING 0x1000
67
68#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
69#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg))
70
71#define R_MC_CONFIG 0x0000000100
72#define R_MC_DRAMCMD 0x0000000120
73#define R_MC_DRAMMODE 0x0000000140
74#define R_MC_TIMING1 0x0000000160
75#define R_MC_TIMING2 0x0000000180
76#define R_MC_CS_START 0x00000001A0
77#define R_MC_CS_END 0x00000001C0
78#define R_MC_CS_INTERLEAVE 0x00000001E0
79#define S_MC_CS_STARTEND 16
80
81#define R_MC_CSX_BASE 0x0000000200
82#define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */
83#define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */
84#define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */
85#define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */
86
87#define R_MC_CS0_ROW 0x0000000200
88#define R_MC_CS0_COL 0x0000000220
89#define R_MC_CS0_BA 0x0000000240
90#define R_MC_CS1_ROW 0x0000000260
91#define R_MC_CS1_COL 0x0000000280
92#define R_MC_CS1_BA 0x00000002A0
93#define R_MC_CS2_ROW 0x00000002C0
94#define R_MC_CS2_COL 0x00000002E0
95#define R_MC_CS2_BA 0x0000000300
96#define R_MC_CS3_ROW 0x0000000320
97#define R_MC_CS3_COL 0x0000000340
98#define R_MC_CS3_BA 0x0000000360
99#define R_MC_CS_ATTR 0x0000000380
100#define R_MC_TEST_DATA 0x0000000400
101#define R_MC_TEST_ECC 0x0000000420
102#define R_MC_MCLK_CFG 0x0000000500
103
104/* *********************************************************************
105 * L2 Cache Control Registers
106 ********************************************************************* */
107
108#define A_L2_READ_TAG 0x0010040018
109#define A_L2_ECC_TAG 0x0010040038
110#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
111#define A_L2_READ_MISC 0x0010040058
112#endif /* 1250 PASS3 || 112x PASS1 */
113#define A_L2_WAY_DISABLE 0x0010041000
114#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
115#define A_L2_MGMT_TAG_BASE 0x00D0000000
116
117#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
118#define A_L2_CACHE_DISABLE 0x0010042000
119#define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
120#define A_L2_MISC_CONFIG 0x0010043000
121#endif /* 1250 PASS2 || 112x PASS1 */
122
123/* Backward-compatibility definitions. */
124/* XXX: discourage people from using these constants. */
125#define A_L2_READ_ADDRESS A_L2_READ_TAG
126#define A_L2_EEC_ADDRESS A_L2_ECC_TAG
127
128
129/* *********************************************************************
130 * PCI Interface Registers
131 ********************************************************************* */
132
133#define A_PCI_TYPE00_HEADER 0x00DE000000
134#define A_PCI_TYPE01_HEADER 0x00DE000800
135
136
137/* *********************************************************************
138 * Ethernet DMA and MACs
139 ********************************************************************* */
140
141#define A_MAC_BASE_0 0x0010064000
142#define A_MAC_BASE_1 0x0010065000
143#if SIBYTE_HDR_FEATURE_CHIP(1250)
144#define A_MAC_BASE_2 0x0010066000
145#endif /* 1250 */
146
147#define MAC_SPACING 0x1000
148#define MAC_DMA_TXRX_SPACING 0x0400
149#define MAC_DMA_CHANNEL_SPACING 0x0100
150#define DMA_RX 0
151#define DMA_TX 1
152#define MAC_NUM_DMACHAN 2 /* channels per direction */
153
154/* XXX: not correct; depends on SOC type. */
155#define MAC_NUM_PORTS 3
156
157#define A_MAC_CHANNEL_BASE(macnum) \
158 (A_MAC_BASE_0 + \
159 MAC_SPACING*(macnum))
160
161#define A_MAC_REGISTER(macnum,reg) \
162 (A_MAC_BASE_0 + \
163 MAC_SPACING*(macnum) + (reg))
164
165
166#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */
167
168#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \
169 ((A_MAC_CHANNEL_BASE(macnum)) + \
170 R_MAC_DMA_CHANNELS + \
171 (MAC_DMA_TXRX_SPACING*(txrx)) + \
172 (MAC_DMA_CHANNEL_SPACING*(chan)))
173
174#define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \
175 (R_MAC_DMA_CHANNELS + \
176 (MAC_DMA_TXRX_SPACING*(txrx)) + \
177 (MAC_DMA_CHANNEL_SPACING*(chan)))
178
179#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \
180 (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \
181 (reg))
182
183#define R_MAC_DMA_REGISTER(txrx,chan,reg) \
184 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \
185 (reg))
186
187/*
188 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
189 */
190
191#define R_MAC_DMA_CONFIG0 0x00000000
192#define R_MAC_DMA_CONFIG1 0x00000008
193#define R_MAC_DMA_DSCR_BASE 0x00000010
194#define R_MAC_DMA_DSCR_CNT 0x00000018
195#define R_MAC_DMA_CUR_DSCRA 0x00000020
196#define R_MAC_DMA_CUR_DSCRB 0x00000028
197#define R_MAC_DMA_CUR_DSCRADDR 0x00000030
198#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
199#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */
200#endif /* 1250 PASS3 || 112x PASS1 */
201
202/*
203 * RMON Counters
204 */
205
206#define R_MAC_RMON_TX_BYTES 0x00000000
207#define R_MAC_RMON_COLLISIONS 0x00000008
208#define R_MAC_RMON_LATE_COL 0x00000010
209#define R_MAC_RMON_EX_COL 0x00000018
210#define R_MAC_RMON_FCS_ERROR 0x00000020
211#define R_MAC_RMON_TX_ABORT 0x00000028
212/* Counter #6 (0x30) now reserved */
213#define R_MAC_RMON_TX_BAD 0x00000038
214#define R_MAC_RMON_TX_GOOD 0x00000040
215#define R_MAC_RMON_TX_RUNT 0x00000048
216#define R_MAC_RMON_TX_OVERSIZE 0x00000050
217#define R_MAC_RMON_RX_BYTES 0x00000080
218#define R_MAC_RMON_RX_MCAST 0x00000088
219#define R_MAC_RMON_RX_BCAST 0x00000090
220#define R_MAC_RMON_RX_BAD 0x00000098
221#define R_MAC_RMON_RX_GOOD 0x000000A0
222#define R_MAC_RMON_RX_RUNT 0x000000A8
223#define R_MAC_RMON_RX_OVERSIZE 0x000000B0
224#define R_MAC_RMON_RX_FCS_ERROR 0x000000B8
225#define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0
226#define R_MAC_RMON_RX_CODE_ERROR 0x000000C8
227#define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0
228
229/* Updated to spec 0.2 */
230#define R_MAC_CFG 0x00000100
231#define R_MAC_THRSH_CFG 0x00000108
232#define R_MAC_VLANTAG 0x00000110
233#define R_MAC_FRAMECFG 0x00000118
234#define R_MAC_EOPCNT 0x00000120
235#define R_MAC_FIFO_PTRS 0x00000130
236#define R_MAC_ADFILTER_CFG 0x00000200
237#define R_MAC_ETHERNET_ADDR 0x00000208
238#define R_MAC_PKT_TYPE 0x00000210
239#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
240#define R_MAC_ADMASK0 0x00000218
241#define R_MAC_ADMASK1 0x00000220
242#endif /* 1250 PASS3 || 112x PASS1 */
243#define R_MAC_HASH_BASE 0x00000240
244#define R_MAC_ADDR_BASE 0x00000280
245#define R_MAC_CHLO0_BASE 0x00000300
246#define R_MAC_CHUP0_BASE 0x00000320
247#define R_MAC_ENABLE 0x00000400
248#define R_MAC_STATUS 0x00000408
249#define R_MAC_INT_MASK 0x00000410
250#define R_MAC_TXD_CTL 0x00000420
251#define R_MAC_MDIO 0x00000428
252#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
253#define R_MAC_STATUS1 0x00000430
254#endif /* 1250 PASS2 || 112x PASS1 */
255#define R_MAC_DEBUG_STATUS 0x00000448
256
257#define MAC_HASH_COUNT 8
258#define MAC_ADDR_COUNT 8
259#define MAC_CHMAP_COUNT 4
260
261
262/* *********************************************************************
263 * DUART Registers
264 ********************************************************************* */
265
266
267#define R_DUART_NUM_PORTS 2
268
269#define A_DUART 0x0010060000
270
271#define A_DUART_REG(r)
272
273#define DUART_CHANREG_SPACING 0x100
274#define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg))
275#define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg))
276
277#define R_DUART_MODE_REG_1 0x100
278#define R_DUART_MODE_REG_2 0x110
279#define R_DUART_STATUS 0x120
280#define R_DUART_CLK_SEL 0x130
281#define R_DUART_CMD 0x150
282#define R_DUART_RX_HOLD 0x160
283#define R_DUART_TX_HOLD 0x170
284
285#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
286#define R_DUART_FULL_CTL 0x140
287#define R_DUART_OPCR_X 0x180
288#define R_DUART_AUXCTL_X 0x190
289#endif /* 1250 PASS2 || 112x PASS1 */
290
291
292/*
293 * The IMR and ISR can't be addressed with A_DUART_CHANREG,
294 * so use this macro instead.
295 */
296
297#define R_DUART_AUX_CTRL 0x310
298#define R_DUART_ISR_A 0x320
299#define R_DUART_IMR_A 0x330
300#define R_DUART_ISR_B 0x340
301#define R_DUART_IMR_B 0x350
302#define R_DUART_OUT_PORT 0x360
303#define R_DUART_OPCR 0x370
304
305#define R_DUART_SET_OPR 0x3B0
306#define R_DUART_CLEAR_OPR 0x3C0
307
308#define DUART_IMRISR_SPACING 0x20
309
310#define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING)
311#define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING)
312
313#define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan))
314#define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan))
315
316
317
318
319/*
320 * These constants are the absolute addresses.
321 */
322
323#define A_DUART_MODE_REG_1_A 0x0010060100
324#define A_DUART_MODE_REG_2_A 0x0010060110
325#define A_DUART_STATUS_A 0x0010060120
326#define A_DUART_CLK_SEL_A 0x0010060130
327#define A_DUART_CMD_A 0x0010060150
328#define A_DUART_RX_HOLD_A 0x0010060160
329#define A_DUART_TX_HOLD_A 0x0010060170
330
331#define A_DUART_MODE_REG_1_B 0x0010060200
332#define A_DUART_MODE_REG_2_B 0x0010060210
333#define A_DUART_STATUS_B 0x0010060220
334#define A_DUART_CLK_SEL_B 0x0010060230
335#define A_DUART_CMD_B 0x0010060250
336#define A_DUART_RX_HOLD_B 0x0010060260
337#define A_DUART_TX_HOLD_B 0x0010060270
338
339#define A_DUART_INPORT_CHNG 0x0010060300
340#define A_DUART_AUX_CTRL 0x0010060310
341#define A_DUART_ISR_A 0x0010060320
342#define A_DUART_IMR_A 0x0010060330
343#define A_DUART_ISR_B 0x0010060340
344#define A_DUART_IMR_B 0x0010060350
345#define A_DUART_OUT_PORT 0x0010060360
346#define A_DUART_OPCR 0x0010060370
347#define A_DUART_IN_PORT 0x0010060380
348#define A_DUART_ISR 0x0010060390
349#define A_DUART_IMR 0x00100603A0
350#define A_DUART_SET_OPR 0x00100603B0
351#define A_DUART_CLEAR_OPR 0x00100603C0
352#define A_DUART_INPORT_CHNG_A 0x00100603D0
353#define A_DUART_INPORT_CHNG_B 0x00100603E0
354
355#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
356#define A_DUART_FULL_CTL_A 0x0010060140
357#define A_DUART_FULL_CTL_B 0x0010060240
358
359#define A_DUART_OPCR_A 0x0010060180
360#define A_DUART_OPCR_B 0x0010060280
361
362#define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0
363#endif /* 1250 PASS2 || 112x PASS1 */
364
365
366/* *********************************************************************
367 * Synchronous Serial Registers
368 ********************************************************************* */
369
370
371#define A_SER_BASE_0 0x0010060400
372#define A_SER_BASE_1 0x0010060800
373#define SER_SPACING 0x400
374
375#define SER_DMA_TXRX_SPACING 0x80
376
377#define SER_NUM_PORTS 2
378
379#define A_SER_CHANNEL_BASE(sernum) \
380 (A_SER_BASE_0 + \
381 SER_SPACING*(sernum))
382
383#define A_SER_REGISTER(sernum,reg) \
384 (A_SER_BASE_0 + \
385 SER_SPACING*(sernum) + (reg))
386
387
388#define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */
389
390#define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \
391 ((A_SER_CHANNEL_BASE(sernum)) + \
392 R_SER_DMA_CHANNELS + \
393 (SER_DMA_TXRX_SPACING*(txrx)))
394
395#define A_SER_DMA_REGISTER(sernum,txrx,reg) \
396 (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \
397 (reg))
398
399
400/*
401 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
402 */
403
404#define R_SER_DMA_CONFIG0 0x00000000
405#define R_SER_DMA_CONFIG1 0x00000008
406#define R_SER_DMA_DSCR_BASE 0x00000010
407#define R_SER_DMA_DSCR_CNT 0x00000018
408#define R_SER_DMA_CUR_DSCRA 0x00000020
409#define R_SER_DMA_CUR_DSCRB 0x00000028
410#define R_SER_DMA_CUR_DSCRADDR 0x00000030
411
412#define R_SER_DMA_CONFIG0_RX 0x00000000
413#define R_SER_DMA_CONFIG1_RX 0x00000008
414#define R_SER_DMA_DSCR_BASE_RX 0x00000010
415#define R_SER_DMA_DSCR_COUNT_RX 0x00000018
416#define R_SER_DMA_CUR_DSCR_A_RX 0x00000020
417#define R_SER_DMA_CUR_DSCR_B_RX 0x00000028
418#define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030
419
420#define R_SER_DMA_CONFIG0_TX 0x00000080
421#define R_SER_DMA_CONFIG1_TX 0x00000088
422#define R_SER_DMA_DSCR_BASE_TX 0x00000090
423#define R_SER_DMA_DSCR_COUNT_TX 0x00000098
424#define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0
425#define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8
426#define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0
427
428#define R_SER_MODE 0x00000100
429#define R_SER_MINFRM_SZ 0x00000108
430#define R_SER_MAXFRM_SZ 0x00000110
431#define R_SER_ADDR 0x00000118
432#define R_SER_USR0_ADDR 0x00000120
433#define R_SER_USR1_ADDR 0x00000128
434#define R_SER_USR2_ADDR 0x00000130
435#define R_SER_USR3_ADDR 0x00000138
436#define R_SER_CMD 0x00000140
437#define R_SER_TX_RD_THRSH 0x00000160
438#define R_SER_TX_WR_THRSH 0x00000168
439#define R_SER_RX_RD_THRSH 0x00000170
440#define R_SER_LINE_MODE 0x00000178
441#define R_SER_DMA_ENABLE 0x00000180
442#define R_SER_INT_MASK 0x00000190
443#define R_SER_STATUS 0x00000188
444#define R_SER_STATUS_DEBUG 0x000001A8
445#define R_SER_RX_TABLE_BASE 0x00000200
446#define SER_RX_TABLE_COUNT 16
447#define R_SER_TX_TABLE_BASE 0x00000300
448#define SER_TX_TABLE_COUNT 16
449
450/* RMON Counters */
451#define R_SER_RMON_TX_BYTE_LO 0x000001C0
452#define R_SER_RMON_TX_BYTE_HI 0x000001C8
453#define R_SER_RMON_RX_BYTE_LO 0x000001D0
454#define R_SER_RMON_RX_BYTE_HI 0x000001D8
455#define R_SER_RMON_TX_UNDERRUN 0x000001E0
456#define R_SER_RMON_RX_OVERFLOW 0x000001E8
457#define R_SER_RMON_RX_ERRORS 0x000001F0
458#define R_SER_RMON_RX_BADADDR 0x000001F8
459
460/* *********************************************************************
461 * Generic Bus Registers
462 ********************************************************************* */
463
464#define IO_EXT_CFG_COUNT 8
465
466#define A_IO_EXT_BASE 0x0010061000
467#define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r))
468
469#define A_IO_EXT_CFG_BASE 0x0010061000
470#define A_IO_EXT_MULT_SIZE_BASE 0x0010061100
471#define A_IO_EXT_START_ADDR_BASE 0x0010061200
472#define A_IO_EXT_TIME_CFG0_BASE 0x0010061600
473#define A_IO_EXT_TIME_CFG1_BASE 0x0010061700
474
475#define IO_EXT_REGISTER_SPACING 8
476#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
477#define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg))
478
479#define R_IO_EXT_CFG 0x0000
480#define R_IO_EXT_MULT_SIZE 0x0100
481#define R_IO_EXT_START_ADDR 0x0200
482#define R_IO_EXT_TIME_CFG0 0x0600
483#define R_IO_EXT_TIME_CFG1 0x0700
484
485
486#define A_IO_INTERRUPT_STATUS 0x0010061A00
487#define A_IO_INTERRUPT_DATA0 0x0010061A10
488#define A_IO_INTERRUPT_DATA1 0x0010061A18
489#define A_IO_INTERRUPT_DATA2 0x0010061A20
490#define A_IO_INTERRUPT_DATA3 0x0010061A28
491#define A_IO_INTERRUPT_ADDR0 0x0010061A30
492#define A_IO_INTERRUPT_ADDR1 0x0010061A40
493#define A_IO_INTERRUPT_PARITY 0x0010061A50
494#define A_IO_PCMCIA_CFG 0x0010061A60
495#define A_IO_PCMCIA_STATUS 0x0010061A70
496#define A_IO_DRIVE_0 0x0010061300
497#define A_IO_DRIVE_1 0x0010061308
498#define A_IO_DRIVE_2 0x0010061310
499#define A_IO_DRIVE_3 0x0010061318
500#define A_IO_DRIVE_BASE A_IO_DRIVE_0
501#define IO_DRIVE_REGISTER_SPACING 8
502#define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING)
503#define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x))
504
505#define R_IO_INTERRUPT_STATUS 0x0A00
506#define R_IO_INTERRUPT_DATA0 0x0A10
507#define R_IO_INTERRUPT_DATA1 0x0A18
508#define R_IO_INTERRUPT_DATA2 0x0A20
509#define R_IO_INTERRUPT_DATA3 0x0A28
510#define R_IO_INTERRUPT_ADDR0 0x0A30
511#define R_IO_INTERRUPT_ADDR1 0x0A40
512#define R_IO_INTERRUPT_PARITY 0x0A50
513#define R_IO_PCMCIA_CFG 0x0A60
514#define R_IO_PCMCIA_STATUS 0x0A70
515
516/* *********************************************************************
517 * GPIO Registers
518 ********************************************************************* */
519
520#define A_GPIO_CLR_EDGE 0x0010061A80
521#define A_GPIO_INT_TYPE 0x0010061A88
522#define A_GPIO_INPUT_INVERT 0x0010061A90
523#define A_GPIO_GLITCH 0x0010061A98
524#define A_GPIO_READ 0x0010061AA0
525#define A_GPIO_DIRECTION 0x0010061AA8
526#define A_GPIO_PIN_CLR 0x0010061AB0
527#define A_GPIO_PIN_SET 0x0010061AB8
528
529#define A_GPIO_BASE 0x0010061A80
530
531#define R_GPIO_CLR_EDGE 0x00
532#define R_GPIO_INT_TYPE 0x08
533#define R_GPIO_INPUT_INVERT 0x10
534#define R_GPIO_GLITCH 0x18
535#define R_GPIO_READ 0x20
536#define R_GPIO_DIRECTION 0x28
537#define R_GPIO_PIN_CLR 0x30
538#define R_GPIO_PIN_SET 0x38
539
540/* *********************************************************************
541 * SMBus Registers
542 ********************************************************************* */
543
544#define A_SMB_XTRA_0 0x0010060000
545#define A_SMB_XTRA_1 0x0010060008
546#define A_SMB_FREQ_0 0x0010060010
547#define A_SMB_FREQ_1 0x0010060018
548#define A_SMB_STATUS_0 0x0010060020
549#define A_SMB_STATUS_1 0x0010060028
550#define A_SMB_CMD_0 0x0010060030
551#define A_SMB_CMD_1 0x0010060038
552#define A_SMB_START_0 0x0010060040
553#define A_SMB_START_1 0x0010060048
554#define A_SMB_DATA_0 0x0010060050
555#define A_SMB_DATA_1 0x0010060058
556#define A_SMB_CONTROL_0 0x0010060060
557#define A_SMB_CONTROL_1 0x0010060068
558#define A_SMB_PEC_0 0x0010060070
559#define A_SMB_PEC_1 0x0010060078
560
561#define A_SMB_0 0x0010060000
562#define A_SMB_1 0x0010060008
563#define SMB_REGISTER_SPACING 0x8
564#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
565#define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg))
566
567#define R_SMB_XTRA 0x0000000000
568#define R_SMB_FREQ 0x0000000010
569#define R_SMB_STATUS 0x0000000020
570#define R_SMB_CMD 0x0000000030
571#define R_SMB_START 0x0000000040
572#define R_SMB_DATA 0x0000000050
573#define R_SMB_CONTROL 0x0000000060
574#define R_SMB_PEC 0x0000000070
575
576/* *********************************************************************
577 * Timer Registers
578 ********************************************************************* */
579
580/*
581 * Watchdog timers
582 */
583
584#define A_SCD_WDOG_0 0x0010020050
585#define A_SCD_WDOG_1 0x0010020150
586#define SCD_WDOG_SPACING 0x100
587#define SCD_NUM_WDOGS 2
588#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
589#define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r))
590
591#define R_SCD_WDOG_INIT 0x0000000000
592#define R_SCD_WDOG_CNT 0x0000000008
593#define R_SCD_WDOG_CFG 0x0000000010
594
595#define A_SCD_WDOG_INIT_0 0x0010020050
596#define A_SCD_WDOG_CNT_0 0x0010020058
597#define A_SCD_WDOG_CFG_0 0x0010020060
598
599#define A_SCD_WDOG_INIT_1 0x0010020150
600#define A_SCD_WDOG_CNT_1 0x0010020158
601#define A_SCD_WDOG_CFG_1 0x0010020160
602
603/*
604 * Generic timers
605 */
606
607#define A_SCD_TIMER_0 0x0010020070
608#define A_SCD_TIMER_1 0x0010020078
609#define A_SCD_TIMER_2 0x0010020170
610#define A_SCD_TIMER_3 0x0010020178
611#define SCD_NUM_TIMERS 4
612#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
613#define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r))
614
615#define R_SCD_TIMER_INIT 0x0000000000
616#define R_SCD_TIMER_CNT 0x0000000010
617#define R_SCD_TIMER_CFG 0x0000000020
618
619#define A_SCD_TIMER_INIT_0 0x0010020070
620#define A_SCD_TIMER_CNT_0 0x0010020080
621#define A_SCD_TIMER_CFG_0 0x0010020090
622
623#define A_SCD_TIMER_INIT_1 0x0010020078
624#define A_SCD_TIMER_CNT_1 0x0010020088
625#define A_SCD_TIMER_CFG_1 0x0010020098
626
627#define A_SCD_TIMER_INIT_2 0x0010020170
628#define A_SCD_TIMER_CNT_2 0x0010020180
629#define A_SCD_TIMER_CFG_2 0x0010020190
630
631#define A_SCD_TIMER_INIT_3 0x0010020178
632#define A_SCD_TIMER_CNT_3 0x0010020188
633#define A_SCD_TIMER_CFG_3 0x0010020198
634
635#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
636#define A_SCD_SCRATCH 0x0010020C10
637
638#define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000
639#define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00
640#define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08
641#endif /* 1250 PASS2 || 112x PASS1 */
642
643
644/* *********************************************************************
645 * System Control Registers
646 ********************************************************************* */
647
648#define A_SCD_SYSTEM_REVISION 0x0010020000
649#define A_SCD_SYSTEM_CFG 0x0010020008
650#define A_SCD_SYSTEM_MANUF 0x0010038000
651
652/* *********************************************************************
653 * System Address Trap Registers
654 ********************************************************************* */
655
656#define A_ADDR_TRAP_INDEX 0x00100200B0
657#define A_ADDR_TRAP_REG 0x00100200B8
658#define A_ADDR_TRAP_UP_0 0x0010020400
659#define A_ADDR_TRAP_UP_1 0x0010020408
660#define A_ADDR_TRAP_UP_2 0x0010020410
661#define A_ADDR_TRAP_UP_3 0x0010020418
662#define A_ADDR_TRAP_DOWN_0 0x0010020420
663#define A_ADDR_TRAP_DOWN_1 0x0010020428
664#define A_ADDR_TRAP_DOWN_2 0x0010020430
665#define A_ADDR_TRAP_DOWN_3 0x0010020438
666#define A_ADDR_TRAP_CFG_0 0x0010020440
667#define A_ADDR_TRAP_CFG_1 0x0010020448
668#define A_ADDR_TRAP_CFG_2 0x0010020450
669#define A_ADDR_TRAP_CFG_3 0x0010020458
670#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
671#define A_ADDR_TRAP_REG_DEBUG 0x0010020460
672#endif /* 1250 PASS2 || 112x PASS1 */
673
674
675/* *********************************************************************
676 * System Interrupt Mapper Registers
677 ********************************************************************* */
678
679#define A_IMR_CPU0_BASE 0x0010020000
680#define A_IMR_CPU1_BASE 0x0010022000
681#define IMR_REGISTER_SPACING 0x2000
682#define IMR_REGISTER_SPACING_SHIFT 13
683
684#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
685#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg))
686
687#define R_IMR_INTERRUPT_DIAG 0x0010
688#define R_IMR_INTERRUPT_MASK 0x0028
689#define R_IMR_INTERRUPT_TRACE 0x0038
690#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040
691#define R_IMR_LDT_INTERRUPT_SET 0x0048
692#define R_IMR_LDT_INTERRUPT 0x0018
693#define R_IMR_LDT_INTERRUPT_CLR 0x0020
694#define R_IMR_MAILBOX_CPU 0x00c0
695#define R_IMR_ALIAS_MAILBOX_CPU 0x1000
696#define R_IMR_MAILBOX_SET_CPU 0x00C8
697#define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008
698#define R_IMR_MAILBOX_CLR_CPU 0x00D0
699#define R_IMR_INTERRUPT_STATUS_BASE 0x0100
700#define R_IMR_INTERRUPT_STATUS_COUNT 7
701#define R_IMR_INTERRUPT_MAP_BASE 0x0200
702#define R_IMR_INTERRUPT_MAP_COUNT 64
703
704/* *********************************************************************
705 * System Performance Counter Registers
706 ********************************************************************* */
707
708#define A_SCD_PERF_CNT_CFG 0x00100204C0
709#define A_SCD_PERF_CNT_0 0x00100204D0
710#define A_SCD_PERF_CNT_1 0x00100204D8
711#define A_SCD_PERF_CNT_2 0x00100204E0
712#define A_SCD_PERF_CNT_3 0x00100204E8
713
714/* *********************************************************************
715 * System Bus Watcher Registers
716 ********************************************************************* */
717
718#define A_SCD_BUS_ERR_STATUS 0x0010020880
719#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
720#define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0
721#endif /* 1250 PASS2 || 112x PASS1 */
722#define A_BUS_ERR_DATA_0 0x00100208A0
723#define A_BUS_ERR_DATA_1 0x00100208A8
724#define A_BUS_ERR_DATA_2 0x00100208B0
725#define A_BUS_ERR_DATA_3 0x00100208B8
726#define A_BUS_L2_ERRORS 0x00100208C0
727#define A_BUS_MEM_IO_ERRORS 0x00100208C8
728
729/* *********************************************************************
730 * System Debug Controller Registers
731 ********************************************************************* */
732
733#define A_SCD_JTAG_BASE 0x0010000000
734
735/* *********************************************************************
736 * System Trace Buffer Registers
737 ********************************************************************* */
738
739#define A_SCD_TRACE_CFG 0x0010020A00
740#define A_SCD_TRACE_READ 0x0010020A08
741#define A_SCD_TRACE_EVENT_0 0x0010020A20
742#define A_SCD_TRACE_EVENT_1 0x0010020A28
743#define A_SCD_TRACE_EVENT_2 0x0010020A30
744#define A_SCD_TRACE_EVENT_3 0x0010020A38
745#define A_SCD_TRACE_SEQUENCE_0 0x0010020A40
746#define A_SCD_TRACE_SEQUENCE_1 0x0010020A48
747#define A_SCD_TRACE_SEQUENCE_2 0x0010020A50
748#define A_SCD_TRACE_SEQUENCE_3 0x0010020A58
749#define A_SCD_TRACE_EVENT_4 0x0010020A60
750#define A_SCD_TRACE_EVENT_5 0x0010020A68
751#define A_SCD_TRACE_EVENT_6 0x0010020A70
752#define A_SCD_TRACE_EVENT_7 0x0010020A78
753#define A_SCD_TRACE_SEQUENCE_4 0x0010020A80
754#define A_SCD_TRACE_SEQUENCE_5 0x0010020A88
755#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90
756#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98
757
758/* *********************************************************************
759 * System Generic DMA Registers
760 ********************************************************************* */
761
762#define A_DM_0 0x0010020B00
763#define A_DM_1 0x0010020B20
764#define A_DM_2 0x0010020B40
765#define A_DM_3 0x0010020B60
766#define DM_REGISTER_SPACING 0x20
767#define DM_NUM_CHANNELS 4
768#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
769#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg))
770
771#define R_DM_DSCR_BASE 0x0000000000
772#define R_DM_DSCR_COUNT 0x0000000008
773#define R_DM_CUR_DSCR_ADDR 0x0000000010
774#define R_DM_DSCR_BASE_DEBUG 0x0000000018
775
776#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
777#define A_DM_PARTIAL_0 0x0010020ba0
778#define A_DM_PARTIAL_1 0x0010020ba8
779#define A_DM_PARTIAL_2 0x0010020bb0
780#define A_DM_PARTIAL_3 0x0010020bb8
781#define DM_PARTIAL_REGISTER_SPACING 0x8
782#define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING))
783#endif /* 1250 PASS3 || 112x PASS1 */
784
785#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
786#define A_DM_CRC_0 0x0010020b80
787#define A_DM_CRC_1 0x0010020b90
788#define DM_CRC_REGISTER_SPACING 0x10
789#define DM_CRC_NUM_CHANNELS 2
790#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))
791#define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg))
792
793#define R_CRC_DEF_0 0x00
794#define R_CTCP_DEF_0 0x08
795#endif /* 1250 PASS3 || 112x PASS1 */
796
797/* *********************************************************************
798 * Physical Address Map
799 ********************************************************************* */
800
801#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000)
802#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024))
803#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000)
804#define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000)
805#define A_PHYS_GENBUS _SB_MAKE64(0x0010090000)
806#define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000)
807#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
808#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000)
809#define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000)
810#define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000)
811#define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000)
812#define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000)
813#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000)
814#define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000)
815#define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000)
816#define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000)
817#define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000)
818#define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000)
819#define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000)
820#define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024))
821#define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000)
822#define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000)
823#define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000)
824#define A_PHYS_RESERVED _SB_MAKE64(0xF200000000)
825#define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000)
826
827#define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000)
828#define PHYS_L2CACHE_NUM_WAYS 4
829#define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000)
830#define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000)
831#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000)
832#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000)
833#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000)
834
835
836#endif
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
new file mode 100644
index 000000000000..22e8041959e2
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_scd.h
@@ -0,0 +1,582 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * SCD Constants and Macros File: sb1250_scd.h
5 *
6 * This module contains constants and macros useful for
7 * manipulating the System Control and Debug module on the 1250.
8 *
9 * SB1250 specification level: User's manual 1/02/02
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34#ifndef _SB1250_SCD_H
35#define _SB1250_SCD_H
36
37#include "sb1250_defs.h"
38
39/* *********************************************************************
40 * System control/debug registers
41 ********************************************************************* */
42
43/*
44 * System Revision Register (Table 4-1)
45 */
46
47#define M_SYS_RESERVED _SB_MAKEMASK(8,0)
48
49#define S_SYS_REVISION _SB_MAKE64(8)
50#define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION)
51#define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION)
52#define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)
53
54#if SIBYTE_HDR_FEATURE_CHIP(1250)
55#define K_SYS_REVISION_BCM1250_PASS1 1
56#define K_SYS_REVISION_BCM1250_PASS2 3
57#define K_SYS_REVISION_BCM1250_A10 11
58#define K_SYS_REVISION_BCM1250_PASS2_2 16
59#define K_SYS_REVISION_BCM1250_B2 17
60#define K_SYS_REVISION_BCM1250_PASS3 32
61#define K_SYS_REVISION_BCM1250_C1 33
62
63/* XXX: discourage people from using these constants. */
64#define K_SYS_REVISION_PASS1 K_SYS_REVISION_BCM1250_PASS1
65#define K_SYS_REVISION_PASS2 K_SYS_REVISION_BCM1250_PASS2
66#define K_SYS_REVISION_PASS2_2 K_SYS_REVISION_BCM1250_PASS2_2
67#define K_SYS_REVISION_PASS3 K_SYS_REVISION_BCM1250_PASS3
68#endif /* 1250 */
69
70#if SIBYTE_HDR_FEATURE_CHIP(112x)
71#define K_SYS_REVISION_BCM112x_A1 32
72#define K_SYS_REVISION_BCM112x_A2 33
73#endif /* 112x */
74
75/* XXX: discourage people from using these constants. */
76#define S_SYS_PART _SB_MAKE64(16)
77#define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART)
78#define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART)
79#define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART)
80
81/* XXX: discourage people from using these constants. */
82#define K_SYS_PART_SB1250 0x1250
83#define K_SYS_PART_BCM1120 0x1121
84#define K_SYS_PART_BCM1125 0x1123
85#define K_SYS_PART_BCM1125H 0x1124
86
87/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field. */
88#define S_SYS_SOC_TYPE _SB_MAKE64(16)
89#define M_SYS_SOC_TYPE _SB_MAKEMASK(4,S_SYS_SOC_TYPE)
90#define V_SYS_SOC_TYPE(x) _SB_MAKEVALUE(x,S_SYS_SOC_TYPE)
91#define G_SYS_SOC_TYPE(x) _SB_GETVALUE(x,S_SYS_SOC_TYPE,M_SYS_SOC_TYPE)
92
93#define K_SYS_SOC_TYPE_BCM1250 0x0
94#define K_SYS_SOC_TYPE_BCM1120 0x1
95#define K_SYS_SOC_TYPE_BCM1250_ALT 0x2 /* 1250pass2 w/ 1/4 L2. */
96#define K_SYS_SOC_TYPE_BCM1125 0x3
97#define K_SYS_SOC_TYPE_BCM1125H 0x4
98#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5 /* 1250pass2 w/ 1/2 L2. */
99
100/*
101 * Calculate correct SOC type given a copy of system revision register.
102 *
103 * (For the assembler version, sysrev and dest may be the same register.
104 * Also, it clobbers AT.)
105 */
106#ifdef __ASSEMBLER__
107#define SYS_SOC_TYPE(dest, sysrev) \
108 .set push ; \
109 .set reorder ; \
110 dsrl dest, sysrev, S_SYS_SOC_TYPE ; \
111 andi dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE); \
112 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ; \
113 beq dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f ; \
114 b 992f ; \
115991: li dest, K_SYS_SOC_TYPE_BCM1250 ; \
116992: \
117 .set pop
118#else
119#define SYS_SOC_TYPE(sysrev) \
120 ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT \
121 || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2) \
122 ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
123#endif
124
125#define S_SYS_WID _SB_MAKE64(32)
126#define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID)
127#define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID)
128#define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)
129
130/* System Manufacturing Register
131* Register: SCD_SYSTEM_MANUF
132*/
133
134/* Wafer ID: bits 31:0 */
135#define S_SYS_WAFERID1_200 _SB_MAKE64(0)
136#define M_SYS_WAFERID1_200 _SB_MAKEMASK(32,S_SYS_WAFERID1_200)
137#define V_SYS_WAFERID1_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID1_200)
138#define G_SYS_WAFERID1_200(x) _SB_GETVALUE(x,S_SYS_WAFERID1_200,M_SYS_WAFERID1_200)
139
140#define S_SYS_BIN _SB_MAKE64(32)
141#define M_SYS_BIN _SB_MAKEMASK(4,S_SYS_BIN)
142#define V_SYS_BIN _SB_MAKEVALUE(x,S_SYS_BIN)
143#define G_SYS_BIN _SB_GETVALUE(x,S_SYS_BIN,M_SYS_BIN)
144
145/* Wafer ID: bits 39:36 */
146#define S_SYS_WAFERID2_200 _SB_MAKE64(36)
147#define M_SYS_WAFERID2_200 _SB_MAKEMASK(4,S_SYS_WAFERID2_200)
148#define V_SYS_WAFERID2_200(x) _SB_MAKEVALUE(x,S_SYS_WAFERID2_200)
149#define G_SYS_WAFERID2_200(x) _SB_GETVALUE(x,S_SYS_WAFERID2_200,M_SYS_WAFERID2_200)
150
151/* Wafer ID: bits 39:0 */
152#define S_SYS_WAFERID_300 _SB_MAKE64(0)
153#define M_SYS_WAFERID_300 _SB_MAKEMASK(40,S_SYS_WAFERID_300)
154#define V_SYS_WAFERID_300(x) _SB_MAKEVALUE(x,S_SYS_WAFERID_300)
155#define G_SYS_WAFERID_300(x) _SB_GETVALUE(x,S_SYS_WAFERID_300,M_SYS_WAFERID_300)
156
157#define S_SYS_XPOS _SB_MAKE64(40)
158#define M_SYS_XPOS _SB_MAKEMASK(6,S_SYS_XPOS)
159#define V_SYS_XPOS(x) _SB_MAKEVALUE(x,S_SYS_XPOS)
160#define G_SYS_XPOS(x) _SB_GETVALUE(x,S_SYS_XPOS,M_SYS_XPOS)
161
162#define S_SYS_YPOS _SB_MAKE64(46)
163#define M_SYS_YPOS _SB_MAKEMASK(6,S_SYS_YPOS)
164#define V_SYS_YPOS(x) _SB_MAKEVALUE(x,S_SYS_YPOS)
165#define G_SYS_YPOS(x) _SB_GETVALUE(x,S_SYS_YPOS,M_SYS_YPOS)
166
167/*
168 * System Config Register (Table 4-2)
169 * Register: SCD_SYSTEM_CFG
170 */
171
172#define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
173#define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
174#define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
175#define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
176
177#define S_SYS_PLL_DIV _SB_MAKE64(7)
178#define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV)
179#define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV)
180#define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV)
181
182#define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
183#define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
184#define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)
185#define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)
186#define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
187
188#define S_SYS_BOOT_MODE _SB_MAKE64(17)
189#define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE)
190#define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE)
191#define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE)
192#define K_SYS_BOOT_MODE_ROM32 0
193#define K_SYS_BOOT_MODE_ROM8 1
194#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
195#define K_SYS_BOOT_MODE_SMBUS_BIG 3
196
197#define M_SYS_PCI_HOST _SB_MAKEMASK1(19)
198#define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)
199#define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)
200#define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
201#define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)
202#define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)
203#define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
204
205#define S_SYS_CONFIG 26
206#define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG)
207#define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG)
208#define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG)
209
210/* The following bits are writeable by JTAG only. */
211
212#define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
213#define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
214
215#define S_SYS_CLKCOUNT 34
216#define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT)
217#define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT)
218#define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT)
219
220#define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
221
222#define S_SYS_PLL_IREF 43
223#define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF)
224
225#define S_SYS_PLL_VCO 45
226#define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO)
227
228#define S_SYS_PLL_VREG 47
229#define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG)
230
231#define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
232#define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
233#define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)
234#define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)
235#define M_SYS_SCD_RESET _SB_MAKEMASK1(53)
236
237/* End of bits writable by JTAG only. */
238
239#define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)
240#define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)
241
242#define M_SYS_UNICPU0 _SB_MAKEMASK1(56)
243#define M_SYS_UNICPU1 _SB_MAKEMASK1(57)
244
245#define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)
246#define M_SYS_EXT_RESET _SB_MAKEMASK1(59)
247#define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)
248
249#define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
250#define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
251
252#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
253#define M_SYS_SW_FLAG _SB_MAKEMASK1(63)
254#endif /* 1250 PASS2 || 112x PASS1 */
255
256
257/*
258 * Mailbox Registers (Table 4-3)
259 * Registers: SCD_MBOX_CPU_x
260 */
261
262#define S_MBOX_INT_3 0
263#define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3)
264#define S_MBOX_INT_2 16
265#define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2)
266#define S_MBOX_INT_1 32
267#define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1)
268#define S_MBOX_INT_0 48
269#define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0)
270
271/*
272 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
273 * Registers: SCD_WDOG_INIT_CNT_x
274 */
275
276#define V_SCD_WDOG_FREQ 1000000
277
278#define S_SCD_WDOG_INIT 0
279#define M_SCD_WDOG_INIT _SB_MAKEMASK(23,S_SCD_WDOG_INIT)
280
281#define S_SCD_WDOG_CNT 0
282#define M_SCD_WDOG_CNT _SB_MAKEMASK(23,S_SCD_WDOG_CNT)
283
284#define S_SCD_WDOG_ENABLE 0
285#define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
286
287#define S_SCD_WDOG_RESET_TYPE 2
288#define M_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(3,S_SCD_WDOG_RESET_TYPE)
289#define V_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x,S_SCD_WDOG_RESET_TYPE)
290#define G_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x,S_SCD_WDOG_RESET_TYPE,M_SCD_WDOG_RESET_TYPE)
291
292#define K_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */
293#define K_SCD_WDOG_RESET_SOFT 1
294#define K_SCD_WDOG_RESET_CPU0 3
295#define K_SCD_WDOG_RESET_CPU1 5
296#define K_SCD_WDOG_RESET_BOTH_CPUS 7
297
298/* This feature is present in 1250 C0 and later, but *not* in 112x A revs. */
299#if SIBYTE_HDR_FEATURE(1250, PASS3)
300#define S_SCD_WDOG_HAS_RESET 8
301#define M_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
302#endif
303
304
305/*
306 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
307 */
308
309#define V_SCD_TIMER_FREQ 1000000
310
311#define S_SCD_TIMER_INIT 0
312#define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT)
313#define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
314#define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
315
316#define S_SCD_TIMER_CNT 0
317#define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT)
318#define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
319#define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)
320
321#define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
322#define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
323#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
324
325/*
326 * System Performance Counters
327 */
328
329#define S_SPC_CFG_SRC0 0
330#define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
331#define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
332#define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0)
333
334#define S_SPC_CFG_SRC1 8
335#define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1)
336#define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1)
337#define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1)
338
339#define S_SPC_CFG_SRC2 16
340#define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2)
341#define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2)
342#define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2)
343
344#define S_SPC_CFG_SRC3 24
345#define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3)
346#define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3)
347#define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3)
348
349#define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
350#define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
351
352
353/*
354 * Bus Watcher
355 */
356
357#define S_SCD_BERR_TID 8
358#define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID)
359#define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID)
360#define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID)
361
362#define S_SCD_BERR_RID 18
363#define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID)
364#define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID)
365#define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID)
366
367#define S_SCD_BERR_DCODE 22
368#define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE)
369#define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE)
370#define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE)
371
372#define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
373
374
375#define S_SCD_L2ECC_CORR_D 0
376#define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D)
377#define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D)
378#define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D)
379
380#define S_SCD_L2ECC_BAD_D 8
381#define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D)
382#define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D)
383#define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D)
384
385#define S_SCD_L2ECC_CORR_T 16
386#define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T)
387#define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T)
388#define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T)
389
390#define S_SCD_L2ECC_BAD_T 24
391#define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T)
392#define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T)
393#define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T)
394
395#define S_SCD_MEM_ECC_CORR 0
396#define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR)
397#define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR)
398#define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR)
399
400#define S_SCD_MEM_ECC_BAD 8
401#define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD)
402#define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD)
403#define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD)
404
405#define S_SCD_MEM_BUSERR 16
406#define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR)
407#define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR)
408#define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR)
409
410
411/*
412 * Address Trap Registers
413 */
414
415#define M_ATRAP_INDEX _SB_MAKEMASK(4,0)
416#define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0)
417
418#define S_ATRAP_CFG_CNT 0
419#define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT)
420#define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT)
421#define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT)
422
423#define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
424#define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
425#define M_ATRAP_CFG_INV _SB_MAKEMASK1(5)
426#define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
427#define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
428
429#define S_ATRAP_CFG_AGENTID 8
430#define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID)
431#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID)
432#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID)
433
434#define K_BUS_AGENT_CPU0 0
435#define K_BUS_AGENT_CPU1 1
436#define K_BUS_AGENT_IOB0 2
437#define K_BUS_AGENT_IOB1 3
438#define K_BUS_AGENT_SCD 4
439#define K_BUS_AGENT_RESERVED 5
440#define K_BUS_AGENT_L2C 6
441#define K_BUS_AGENT_MC 7
442
443#define S_ATRAP_CFG_CATTR 12
444#define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR)
445#define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR)
446#define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR)
447
448#define K_ATRAP_CFG_CATTR_IGNORE 0
449#define K_ATRAP_CFG_CATTR_UNC 1
450#define K_ATRAP_CFG_CATTR_CACHEABLE 2
451#define K_ATRAP_CFG_CATTR_NONCOH 3
452#define K_ATRAP_CFG_CATTR_COHERENT 4
453#define K_ATRAP_CFG_CATTR_NOTUNC 5
454#define K_ATRAP_CFG_CATTR_NOTNONCOH 6
455#define K_ATRAP_CFG_CATTR_NOTCOHERENT 7
456
457/*
458 * Trace Buffer Config register
459 */
460
461#define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
462#define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
463#define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
464#define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
465#define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
466#define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
467#define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
468#define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
469#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
470#define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8)
471#endif /* 1250 PASS2 || 112x PASS1 */
472
473#define S_SCD_TRACE_CFG_CUR_ADDR 10
474#define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR)
475#define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
476#define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
477
478/*
479 * Trace Event registers
480 */
481
482#define S_SCD_TREVT_ADDR_MATCH 0
483#define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH)
484#define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH)
485#define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH)
486
487#define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
488#define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
489#define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6)
490#define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7)
491#define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9)
492#define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10)
493#define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
494
495#define S_SCD_TREVT_REQID 12
496#define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID)
497#define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID)
498#define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID)
499
500#define S_SCD_TREVT_RESPID 16
501#define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID)
502#define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID)
503#define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID)
504
505#define S_SCD_TREVT_DATAID 20
506#define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID)
507#define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID)
508#define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID)
509
510#define S_SCD_TREVT_COUNT 24
511#define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT)
512#define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT)
513#define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT)
514
515/*
516 * Trace Sequence registers
517 */
518
519#define S_SCD_TRSEQ_EVENT4 0
520#define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4)
521#define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4)
522#define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4)
523
524#define S_SCD_TRSEQ_EVENT3 4
525#define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3)
526#define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3)
527#define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3)
528
529#define S_SCD_TRSEQ_EVENT2 8
530#define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2)
531#define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2)
532#define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2)
533
534#define S_SCD_TRSEQ_EVENT1 12
535#define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1)
536#define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1)
537#define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1)
538
539#define K_SCD_TRSEQ_E0 0
540#define K_SCD_TRSEQ_E1 1
541#define K_SCD_TRSEQ_E2 2
542#define K_SCD_TRSEQ_E3 3
543#define K_SCD_TRSEQ_E0_E1 4
544#define K_SCD_TRSEQ_E1_E2 5
545#define K_SCD_TRSEQ_E2_E3 6
546#define K_SCD_TRSEQ_E0_E1_E2 7
547#define K_SCD_TRSEQ_E0_E1_E2_E3 8
548#define K_SCD_TRSEQ_E0E1 9
549#define K_SCD_TRSEQ_E0E1E2 10
550#define K_SCD_TRSEQ_E0E1E2E3 11
551#define K_SCD_TRSEQ_E0E1_E2 12
552#define K_SCD_TRSEQ_E0E1_E2E3 13
553#define K_SCD_TRSEQ_E0E1_E2_E3 14
554#define K_SCD_TRSEQ_IGNORED 15
555
556#define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
557 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
558 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
559 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
560
561#define S_SCD_TRSEQ_FUNCTION 16
562#define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION)
563#define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION)
564#define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION)
565
566#define K_SCD_TRSEQ_FUNC_NOP 0
567#define K_SCD_TRSEQ_FUNC_START 1
568#define K_SCD_TRSEQ_FUNC_STOP 2
569#define K_SCD_TRSEQ_FUNC_FREEZE 3
570
571#define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
572#define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
573#define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
574#define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
575
576#define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18)
577#define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19)
578#define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
579#define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
580#define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)
581
582#endif
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h
new file mode 100644
index 000000000000..287cbfe9efa2
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_smbus.h
@@ -0,0 +1,170 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * SMBUS Constants File: sb1250_smbus.h
5 *
6 * This module contains constants and macros useful for
7 * manipulating the SB1250's SMbus devices.
8 *
9 * SB1250 specification level: 01/02/2002
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34
35#ifndef _SB1250_SMBUS_H
36#define _SB1250_SMBUS_H
37
38#include "sb1250_defs.h"
39
40/*
41 * SMBus Clock Frequency Register (Table 14-2)
42 */
43
44#define S_SMB_FREQ_DIV 0
45#define M_SMB_FREQ_DIV _SB_MAKEMASK(13,S_SMB_FREQ_DIV)
46#define V_SMB_FREQ_DIV(x) _SB_MAKEVALUE(x,S_SMB_FREQ_DIV)
47
48#define K_SMB_FREQ_400KHZ 0x1F
49#define K_SMB_FREQ_100KHZ 0x7D
50
51#define S_SMB_CMD 0
52#define M_SMB_CMD _SB_MAKEMASK(8,S_SMB_CMD)
53#define V_SMB_CMD(x) _SB_MAKEVALUE(x,S_SMB_CMD)
54
55/*
56 * SMBus control register (Table 14-4)
57 */
58
59#define M_SMB_ERR_INTR _SB_MAKEMASK1(0)
60#define M_SMB_FINISH_INTR _SB_MAKEMASK1(1)
61#define M_SMB_DATA_OUT _SB_MAKEMASK1(4)
62#define M_SMB_DATA_DIR _SB_MAKEMASK1(5)
63#define M_SMB_DATA_DIR_OUTPUT M_SMB_DATA_DIR
64#define M_SMB_CLK_OUT _SB_MAKEMASK1(6)
65#define M_SMB_DIRECT_ENABLE _SB_MAKEMASK1(7)
66
67/*
68 * SMBus status registers (Table 14-5)
69 */
70
71#define M_SMB_BUSY _SB_MAKEMASK1(0)
72#define M_SMB_ERROR _SB_MAKEMASK1(1)
73#define M_SMB_ERROR_TYPE _SB_MAKEMASK1(2)
74#define M_SMB_REF _SB_MAKEMASK1(6)
75#define M_SMB_DATA_IN _SB_MAKEMASK1(7)
76
77/*
78 * SMBus Start/Command registers (Table 14-9)
79 */
80
81#define S_SMB_ADDR 0
82#define M_SMB_ADDR _SB_MAKEMASK(7,S_SMB_ADDR)
83#define V_SMB_ADDR(x) _SB_MAKEVALUE(x,S_SMB_ADDR)
84#define G_SMB_ADDR(x) _SB_GETVALUE(x,S_SMB_ADDR,M_SMB_ADDR)
85
86#define M_SMB_QDATA _SB_MAKEMASK1(7)
87
88#define S_SMB_TT 8
89#define M_SMB_TT _SB_MAKEMASK(3,S_SMB_TT)
90#define V_SMB_TT(x) _SB_MAKEVALUE(x,S_SMB_TT)
91#define G_SMB_TT(x) _SB_GETVALUE(x,S_SMB_TT,M_SMB_TT)
92
93#define K_SMB_TT_WR1BYTE 0
94#define K_SMB_TT_WR2BYTE 1
95#define K_SMB_TT_WR3BYTE 2
96#define K_SMB_TT_CMD_RD1BYTE 3
97#define K_SMB_TT_CMD_RD2BYTE 4
98#define K_SMB_TT_RD1BYTE 5
99#define K_SMB_TT_QUICKCMD 6
100#define K_SMB_TT_EEPROMREAD 7
101
102#define V_SMB_TT_WR1BYTE V_SMB_TT(K_SMB_TT_WR1BYTE)
103#define V_SMB_TT_WR2BYTE V_SMB_TT(K_SMB_TT_WR2BYTE)
104#define V_SMB_TT_WR3BYTE V_SMB_TT(K_SMB_TT_WR3BYTE)
105#define V_SMB_TT_CMD_RD1BYTE V_SMB_TT(K_SMB_TT_CMD_RD1BYTE)
106#define V_SMB_TT_CMD_RD2BYTE V_SMB_TT(K_SMB_TT_CMD_RD2BYTE)
107#define V_SMB_TT_RD1BYTE V_SMB_TT(K_SMB_TT_RD1BYTE)
108#define V_SMB_TT_QUICKCMD V_SMB_TT(K_SMB_TT_QUICKCMD)
109#define V_SMB_TT_EEPROMREAD V_SMB_TT(K_SMB_TT_EEPROMREAD)
110
111#define M_SMB_PEC _SB_MAKEMASK1(15)
112
113/*
114 * SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7)
115 */
116
117#define S_SMB_LB 0
118#define M_SMB_LB _SB_MAKEMASK(8,S_SMB_LB)
119#define V_SMB_LB(x) _SB_MAKEVALUE(x,S_SMB_LB)
120
121#define S_SMB_MB 8
122#define M_SMB_MB _SB_MAKEMASK(8,S_SMB_MB)
123#define V_SMB_MB(x) _SB_MAKEVALUE(x,S_SMB_MB)
124
125
126/*
127 * SMBus Packet Error Check register (Table 14-8)
128 */
129
130#define S_SPEC_PEC 0
131#define M_SPEC_PEC _SB_MAKEMASK(8,S_SPEC_PEC)
132#define V_SPEC_MB(x) _SB_MAKEVALUE(x,S_SPEC_PEC)
133
134
135#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
136
137#define S_SMB_CMDH 8
138#define M_SMB_CMDH _SB_MAKEMASK(8,S_SMBH_CMD)
139#define V_SMB_CMDH(x) _SB_MAKEVALUE(x,S_SMBH_CMD)
140
141#define M_SMB_EXTEND _SB_MAKEMASK1(14)
142
143#define M_SMB_DIR _SB_MAKEMASK1(13)
144
145#define S_SMB_DFMT 8
146#define M_SMB_DFMT _SB_MAKEMASK(3,S_SMB_DFMT)
147#define V_SMB_DFMT(x) _SB_MAKEVALUE(x,S_SMB_DFMT)
148#define G_SMB_DFMT(x) _SB_GETVALUE(x,S_SMB_DFMT,M_SMB_DFMT)
149
150#define K_SMB_DFMT_1BYTE 0
151#define K_SMB_DFMT_2BYTE 1
152#define K_SMB_DFMT_3BYTE 2
153#define K_SMB_DFMT_4BYTE 3
154#define K_SMB_DFMT_NODATA 4
155#define K_SMB_DFMT_CMD4BYTE 5
156#define K_SMB_DFMT_CMD5BYTE 6
157#define K_SMB_DFMT_RESERVED 7
158
159#define V_SMB_DFMT_1BYTE V_SMB_DFMT(K_SMB_DFMT_1BYTE)
160#define V_SMB_DFMT_2BYTE V_SMB_DFMT(K_SMB_DFMT_2BYTE)
161#define V_SMB_DFMT_3BYTE V_SMB_DFMT(K_SMB_DFMT_3BYTE)
162#define V_SMB_DFMT_4BYTE V_SMB_DFMT(K_SMB_DFMT_4BYTE)
163#define V_SMB_DFMT_NODATA V_SMB_DFMT(K_SMB_DFMT_NODATA)
164#define V_SMB_DFMT_CMD4BYTE V_SMB_DFMT(K_SMB_DFMT_CMD4BYTE)
165#define V_SMB_DFMT_CMD5BYTE V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
166#define V_SMB_DFMT_RESERVED V_SMB_DFMT(K_SMB_DFMT_RESERVED)
167
168#endif /* 1250 PASS2 || 112x PASS1 */
169
170#endif
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h
new file mode 100644
index 000000000000..8d5e8edd3c4b
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_syncser.h
@@ -0,0 +1,148 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * Synchronous Serial Constants File: sb1250_syncser.h
5 *
6 * This module contains constants and macros useful for
7 * manipulating the SB1250's Synchronous Serial
8 *
9 * SB1250 specification level: User's manual 1/02/02
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34
35#ifndef _SB1250_SYNCSER_H
36#define _SB1250_SYNCSER_H
37
38#include "sb1250_defs.h"
39
40/*
41 * Serial Mode Configuration Register
42 */
43
44#define M_SYNCSER_CRC_MODE _SB_MAKEMASK1(0)
45#define M_SYNCSER_MSB_FIRST _SB_MAKEMASK1(1)
46
47#define S_SYNCSER_FLAG_NUM 2
48#define M_SYNCSER_FLAG_NUM _SB_MAKEMASK(4,S_SYNCSER_FLAG_NUM)
49#define V_SYNCSER_FLAG_NUM _SB_MAKEVALUE(x,S_SYNCSER_FLAG_NUM)
50
51#define M_SYNCSER_FLAG_EN _SB_MAKEMASK1(6)
52#define M_SYNCSER_HDLC_EN _SB_MAKEMASK1(7)
53#define M_SYNCSER_LOOP_MODE _SB_MAKEMASK1(8)
54#define M_SYNCSER_LOOPBACK _SB_MAKEMASK1(9)
55
56/*
57 * Serial Clock Source and Line Interface Mode Register
58 */
59
60#define M_SYNCSER_RXCLK_INV _SB_MAKEMASK1(0)
61#define M_SYNCSER_RXCLK_EXT _SB_MAKEMASK1(1)
62
63#define S_SYNCSER_RXSYNC_DLY 2
64#define M_SYNCSER_RXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_RXSYNC_DLY)
65#define V_SYNCSER_RXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_RXSYNC_DLY)
66
67#define M_SYNCSER_RXSYNC_LOW _SB_MAKEMASK1(4)
68#define M_SYNCSER_RXSTRB_LOW _SB_MAKEMASK1(5)
69
70#define M_SYNCSER_RXSYNC_EDGE _SB_MAKEMASK1(6)
71#define M_SYNCSER_RXSYNC_INT _SB_MAKEMASK1(7)
72
73#define M_SYNCSER_TXCLK_INV _SB_MAKEMASK1(8)
74#define M_SYNCSER_TXCLK_EXT _SB_MAKEMASK1(9)
75
76#define S_SYNCSER_TXSYNC_DLY 10
77#define M_SYNCSER_TXSYNC_DLY _SB_MAKEMASK(2,S_SYNCSER_TXSYNC_DLY)
78#define V_SYNCSER_TXSYNC_DLY(x) _SB_MAKEVALUE(x,S_SYNCSER_TXSYNC_DLY)
79
80#define M_SYNCSER_TXSYNC_LOW _SB_MAKEMASK1(12)
81#define M_SYNCSER_TXSTRB_LOW _SB_MAKEMASK1(13)
82
83#define M_SYNCSER_TXSYNC_EDGE _SB_MAKEMASK1(14)
84#define M_SYNCSER_TXSYNC_INT _SB_MAKEMASK1(15)
85
86/*
87 * Serial Command Register
88 */
89
90#define M_SYNCSER_CMD_RX_EN _SB_MAKEMASK1(0)
91#define M_SYNCSER_CMD_TX_EN _SB_MAKEMASK1(1)
92#define M_SYNCSER_CMD_RX_RESET _SB_MAKEMASK1(2)
93#define M_SYNCSER_CMD_TX_RESET _SB_MAKEMASK1(3)
94#define M_SYNCSER_CMD_TX_PAUSE _SB_MAKEMASK1(5)
95
96/*
97 * Serial DMA Enable Register
98 */
99
100#define M_SYNCSER_DMA_RX_EN _SB_MAKEMASK1(0)
101#define M_SYNCSER_DMA_TX_EN _SB_MAKEMASK1(4)
102
103/*
104 * Serial Status Register
105 */
106
107#define M_SYNCSER_RX_CRCERR _SB_MAKEMASK1(0)
108#define M_SYNCSER_RX_ABORT _SB_MAKEMASK1(1)
109#define M_SYNCSER_RX_OCTET _SB_MAKEMASK1(2)
110#define M_SYNCSER_RX_LONGFRM _SB_MAKEMASK1(3)
111#define M_SYNCSER_RX_SHORTFRM _SB_MAKEMASK1(4)
112#define M_SYNCSER_RX_OVERRUN _SB_MAKEMASK1(5)
113#define M_SYNCSER_RX_SYNC_ERR _SB_MAKEMASK1(6)
114#define M_SYNCSER_TX_CRCERR _SB_MAKEMASK1(8)
115#define M_SYNCSER_TX_UNDERRUN _SB_MAKEMASK1(9)
116#define M_SYNCSER_TX_SYNC_ERR _SB_MAKEMASK1(10)
117#define M_SYNCSER_TX_PAUSE_COMPLETE _SB_MAKEMASK1(11)
118#define M_SYNCSER_RX_EOP_COUNT _SB_MAKEMASK1(16)
119#define M_SYNCSER_RX_EOP_TIMER _SB_MAKEMASK1(17)
120#define M_SYNCSER_RX_EOP_SEEN _SB_MAKEMASK1(18)
121#define M_SYNCSER_RX_HWM _SB_MAKEMASK1(19)
122#define M_SYNCSER_RX_LWM _SB_MAKEMASK1(20)
123#define M_SYNCSER_RX_DSCR _SB_MAKEMASK1(21)
124#define M_SYNCSER_RX_DERR _SB_MAKEMASK1(22)
125#define M_SYNCSER_TX_EOP_COUNT _SB_MAKEMASK1(24)
126#define M_SYNCSER_TX_EOP_TIMER _SB_MAKEMASK1(25)
127#define M_SYNCSER_TX_EOP_SEEN _SB_MAKEMASK1(26)
128#define M_SYNCSER_TX_HWM _SB_MAKEMASK1(27)
129#define M_SYNCSER_TX_LWM _SB_MAKEMASK1(28)
130#define M_SYNCSER_TX_DSCR _SB_MAKEMASK1(29)
131#define M_SYNCSER_TX_DERR _SB_MAKEMASK1(30)
132#define M_SYNCSER_TX_DZERO _SB_MAKEMASK1(31)
133
134/*
135 * Sequencer Table Entry format
136 */
137
138#define M_SYNCSER_SEQ_LAST _SB_MAKEMASK1(0)
139#define M_SYNCSER_SEQ_BYTE _SB_MAKEMASK1(1)
140
141#define S_SYNCSER_SEQ_COUNT 2
142#define M_SYNCSER_SEQ_COUNT _SB_MAKEMASK(4,S_SYNCSER_SEQ_COUNT)
143#define V_SYNCSER_SEQ_COUNT(x) _SB_MAKEVALUE(x,S_SYNCSER_SEQ_COUNT)
144
145#define M_SYNCSER_SEQ_ENABLE _SB_MAKEMASK1(6)
146#define M_SYNCSER_SEQ_STROBE _SB_MAKEMASK1(7)
147
148#endif
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h
new file mode 100644
index 000000000000..7655d6945cca
--- /dev/null
+++ b/include/asm-mips/sibyte/sb1250_uart.h
@@ -0,0 +1,354 @@
1/* *********************************************************************
2 * SB1250 Board Support Package
3 *
4 * UART Constants File: sb1250_uart.h
5 *
6 * This module contains constants and macros useful for
7 * manipulating the SB1250's UARTs
8 *
9 * SB1250 specification level: User's manual 1/02/02
10 *
11 * Author: Mitch Lichtenberg
12 *
13 *********************************************************************
14 *
15 * Copyright 2000,2001,2002,2003
16 * Broadcom Corporation. All rights reserved.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 ********************************************************************* */
33
34
35#ifndef _SB1250_UART_H
36#define _SB1250_UART_H
37
38#include "sb1250_defs.h"
39
40/* **********************************************************************
41 * DUART Registers
42 ********************************************************************** */
43
44/*
45 * DUART Mode Register #1 (Table 10-3)
46 * Register: DUART_MODE_REG_1_A
47 * Register: DUART_MODE_REG_1_B
48 */
49
50#define S_DUART_BITS_PER_CHAR 0
51#define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR)
52#define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR)
53
54#define K_DUART_BITS_PER_CHAR_RSV0 0
55#define K_DUART_BITS_PER_CHAR_RSV1 1
56#define K_DUART_BITS_PER_CHAR_7 2
57#define K_DUART_BITS_PER_CHAR_8 3
58
59#define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
60#define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
61#define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
62#define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
63
64
65#define M_DUART_PARITY_TYPE_EVEN 0x00
66#define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2)
67
68#define S_DUART_PARITY_MODE 3
69#define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE)
70#define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE)
71
72#define K_DUART_PARITY_MODE_ADD 0
73#define K_DUART_PARITY_MODE_ADD_FIXED 1
74#define K_DUART_PARITY_MODE_NONE 2
75
76#define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
77#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
78#define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
79
80#define M_DUART_ERR_MODE _SB_MAKEMASK1(5) /* must be zero */
81
82#define M_DUART_RX_IRQ_SEL_RXRDY 0
83#define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6)
84
85#define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7)
86
87/*
88 * DUART Mode Register #2 (Table 10-4)
89 * Register: DUART_MODE_REG_2_A
90 * Register: DUART_MODE_REG_2_B
91 */
92
93#define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */
94
95#define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3)
96#define M_DUART_STOP_BIT_LEN_1 0
97
98#define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4)
99
100
101#define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */
102
103#define S_DUART_CHAN_MODE 6
104#define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE)
105#define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE)
106
107#define K_DUART_CHAN_MODE_NORMAL 0
108#define K_DUART_CHAN_MODE_LCL_LOOP 2
109#define K_DUART_CHAN_MODE_REM_LOOP 3
110
111#define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL)
112#define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP)
113#define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP)
114
115/*
116 * DUART Command Register (Table 10-5)
117 * Register: DUART_CMD_A
118 * Register: DUART_CMD_B
119 */
120
121#define M_DUART_RX_EN _SB_MAKEMASK1(0)
122#define M_DUART_RX_DIS _SB_MAKEMASK1(1)
123#define M_DUART_TX_EN _SB_MAKEMASK1(2)
124#define M_DUART_TX_DIS _SB_MAKEMASK1(3)
125
126#define S_DUART_MISC_CMD 4
127#define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD)
128#define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD)
129
130#define K_DUART_MISC_CMD_NOACTION0 0
131#define K_DUART_MISC_CMD_NOACTION1 1
132#define K_DUART_MISC_CMD_RESET_RX 2
133#define K_DUART_MISC_CMD_RESET_TX 3
134#define K_DUART_MISC_CMD_NOACTION4 4
135#define K_DUART_MISC_CMD_RESET_BREAK_INT 5
136#define K_DUART_MISC_CMD_START_BREAK 6
137#define K_DUART_MISC_CMD_STOP_BREAK 7
138
139#define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
140#define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
141#define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
142#define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
143#define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
144#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
145#define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
146#define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
147
148#define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7)
149
150/*
151 * DUART Status Register (Table 10-6)
152 * Register: DUART_STATUS_A
153 * Register: DUART_STATUS_B
154 * READ-ONLY
155 */
156
157#define M_DUART_RX_RDY _SB_MAKEMASK1(0)
158#define M_DUART_RX_FFUL _SB_MAKEMASK1(1)
159#define M_DUART_TX_RDY _SB_MAKEMASK1(2)
160#define M_DUART_TX_EMT _SB_MAKEMASK1(3)
161#define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4)
162#define M_DUART_PARITY_ERR _SB_MAKEMASK1(5)
163#define M_DUART_FRM_ERR _SB_MAKEMASK1(6)
164#define M_DUART_RCVD_BRK _SB_MAKEMASK1(7)
165
166/*
167 * DUART Baud Rate Register (Table 10-7)
168 * Register: DUART_CLK_SEL_A
169 * Register: DUART_CLK_SEL_B
170 */
171
172#define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0)
173#define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1)
174
175/*
176 * DUART Data Registers (Table 10-8 and 10-9)
177 * Register: DUART_RX_HOLD_A
178 * Register: DUART_RX_HOLD_B
179 * Register: DUART_TX_HOLD_A
180 * Register: DUART_TX_HOLD_B
181 */
182
183#define M_DUART_RX_DATA _SB_MAKEMASK(8,0)
184#define M_DUART_TX_DATA _SB_MAKEMASK(8,0)
185
186/*
187 * DUART Input Port Register (Table 10-10)
188 * Register: DUART_IN_PORT
189 */
190
191#define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0)
192#define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1)
193#define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2)
194#define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3)
195#define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4)
196#define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5)
197#define M_DUART_RIN0_PIN _SB_MAKEMASK1(6)
198#define M_DUART_RIN1_PIN _SB_MAKEMASK1(7)
199
200/*
201 * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
202 * Register: DUART_INPORT_CHNG
203 */
204
205#define S_DUART_IN_PIN_VAL 0
206#define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL)
207
208#define S_DUART_IN_PIN_CHNG 4
209#define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG)
210
211
212/*
213 * DUART Output port control register (Table 10-14)
214 * Register: DUART_OPCR
215 */
216
217#define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */
218#define M_DUART_OPC2_SEL _SB_MAKEMASK1(1)
219#define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */
220#define M_DUART_OPC3_SEL _SB_MAKEMASK1(3)
221#define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */
222
223/*
224 * DUART Aux Control Register (Table 10-15)
225 * Register: DUART_AUX_CTRL
226 */
227
228#define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0)
229#define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1)
230#define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2)
231#define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3)
232#define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4)
233
234#define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0)
235#define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2)
236
237/*
238 * DUART Interrupt Status Register (Table 10-16)
239 * Register: DUART_ISR
240 */
241
242#define M_DUART_ISR_TX_A _SB_MAKEMASK1(0)
243#define M_DUART_ISR_RX_A _SB_MAKEMASK1(1)
244#define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2)
245#define M_DUART_ISR_IN_A _SB_MAKEMASK1(3)
246#define M_DUART_ISR_TX_B _SB_MAKEMASK1(4)
247#define M_DUART_ISR_RX_B _SB_MAKEMASK1(5)
248#define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6)
249#define M_DUART_ISR_IN_B _SB_MAKEMASK1(7)
250
251/*
252 * DUART Channel A Interrupt Status Register (Table 10-17)
253 * DUART Channel B Interrupt Status Register (Table 10-18)
254 * Register: DUART_ISR_A
255 * Register: DUART_ISR_B
256 */
257
258#define M_DUART_ISR_TX _SB_MAKEMASK1(0)
259#define M_DUART_ISR_RX _SB_MAKEMASK1(1)
260#define M_DUART_ISR_BRK _SB_MAKEMASK1(2)
261#define M_DUART_ISR_IN _SB_MAKEMASK1(3)
262#define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4)
263
264/*
265 * DUART Interrupt Mask Register (Table 10-19)
266 * Register: DUART_IMR
267 */
268
269#define M_DUART_IMR_TX_A _SB_MAKEMASK1(0)
270#define M_DUART_IMR_RX_A _SB_MAKEMASK1(1)
271#define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2)
272#define M_DUART_IMR_IN_A _SB_MAKEMASK1(3)
273#define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0)
274
275#define M_DUART_IMR_TX_B _SB_MAKEMASK1(4)
276#define M_DUART_IMR_RX_B _SB_MAKEMASK1(5)
277#define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6)
278#define M_DUART_IMR_IN_B _SB_MAKEMASK1(7)
279#define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4)
280
281/*
282 * DUART Channel A Interrupt Mask Register (Table 10-20)
283 * DUART Channel B Interrupt Mask Register (Table 10-21)
284 * Register: DUART_IMR_A
285 * Register: DUART_IMR_B
286 */
287
288#define M_DUART_IMR_TX _SB_MAKEMASK1(0)
289#define M_DUART_IMR_RX _SB_MAKEMASK1(1)
290#define M_DUART_IMR_BRK _SB_MAKEMASK1(2)
291#define M_DUART_IMR_IN _SB_MAKEMASK1(3)
292#define M_DUART_IMR_ALL _SB_MAKEMASK(4,0)
293#define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4)
294
295
296/*
297 * DUART Output Port Set Register (Table 10-22)
298 * Register: DUART_SET_OPR
299 */
300
301#define M_DUART_SET_OPR0 _SB_MAKEMASK1(0)
302#define M_DUART_SET_OPR1 _SB_MAKEMASK1(1)
303#define M_DUART_SET_OPR2 _SB_MAKEMASK1(2)
304#define M_DUART_SET_OPR3 _SB_MAKEMASK1(3)
305#define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4)
306
307/*
308 * DUART Output Port Clear Register (Table 10-23)
309 * Register: DUART_CLEAR_OPR
310 */
311
312#define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0)
313#define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1)
314#define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2)
315#define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3)
316#define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4)
317
318/*
319 * DUART Output Port RTS Register (Table 10-24)
320 * Register: DUART_OUT_PORT
321 */
322
323#define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0)
324#define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1)
325#define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2)
326#define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3)
327#define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4)
328
329#define M_DUART_OUT_PIN_SET(chan) \
330 (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
331#define M_DUART_OUT_PIN_CLR(chan) \
332 (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
333
334#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
335/*
336 * Full Interrupt Control Register
337 */
338
339#define S_DUART_SIG_FULL _SB_MAKE64(0)
340#define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL)
341#define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL)
342#define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL)
343
344#define S_DUART_INT_TIME _SB_MAKE64(4)
345#define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME)
346#define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME)
347#define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME)
348#endif /* 1250 PASS2 || 112x PASS1 */
349
350
351/* ********************************************************************** */
352
353
354#endif
diff --git a/include/asm-mips/sibyte/sentosa.h b/include/asm-mips/sibyte/sentosa.h
new file mode 100644
index 000000000000..824605847af4
--- /dev/null
+++ b/include/asm-mips/sibyte/sentosa.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2000, 2001 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#ifndef __ASM_SIBYTE_SENTOSA_H
19#define __ASM_SIBYTE_SENTOSA_H
20
21#include <linux/config.h>
22#include <asm/sibyte/sb1250.h>
23#include <asm/sibyte/sb1250_int.h>
24
25#ifdef CONFIG_SIBYTE_SENTOSA
26#define SIBYTE_BOARD_NAME "BCM91250E (Sentosa)"
27#endif
28#ifdef CONFIG_SIBYTE_RHONE
29#define SIBYTE_BOARD_NAME "BCM91125E (Rhone)"
30#endif
31
32/* Generic bus chip selects */
33#ifdef CONFIG_SIBYTE_RHONE
34#define LEDS_CS 6
35#define LEDS_PHYS 0x1d0a0000
36#endif
37
38/* GPIOs */
39#define K_GPIO_DBG_LED 0
40
41#endif /* __ASM_SIBYTE_SENTOSA_H */
diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h
new file mode 100644
index 000000000000..97fa0494c30c
--- /dev/null
+++ b/include/asm-mips/sibyte/swarm.h
@@ -0,0 +1,71 @@
1/*
2 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18#ifndef __ASM_SIBYTE_SWARM_H
19#define __ASM_SIBYTE_SWARM_H
20
21#include <linux/config.h>
22#include <asm/sibyte/sb1250.h>
23#include <asm/sibyte/sb1250_int.h>
24
25#ifdef CONFIG_SIBYTE_SWARM
26#define SIBYTE_BOARD_NAME "BCM91250A (SWARM)"
27#define SIBYTE_HAVE_PCMCIA 1
28#define SIBYTE_HAVE_IDE 1
29#endif
30#ifdef CONFIG_SIBYTE_PTSWARM
31#define SIBYTE_BOARD_NAME "PTSWARM"
32#define SIBYTE_HAVE_PCMCIA 1
33#define SIBYTE_HAVE_IDE 1
34#define SIBYTE_DEFAULT_CONSOLE "ttyS0,115200"
35#endif
36#ifdef CONFIG_SIBYTE_LITTLESUR
37#define SIBYTE_BOARD_NAME "BCM1250C2 (LittleSur)"
38#define SIBYTE_HAVE_PCMCIA 0
39#define SIBYTE_HAVE_IDE 1
40#define SIBYTE_DEFAULT_CONSOLE "cfe0"
41#endif
42#ifdef CONFIG_SIBYTE_CRHONE
43#define SIBYTE_BOARD_NAME "BCM91125C (CRhone)"
44#define SIBYTE_HAVE_PCMCIA 0
45#define SIBYTE_HAVE_IDE 0
46#endif
47#ifdef CONFIG_SIBYTE_CRHINE
48#define SIBYTE_BOARD_NAME "BCM91120C (CRhine)"
49#define SIBYTE_HAVE_PCMCIA 0
50#define SIBYTE_HAVE_IDE 0
51#endif
52
53/* Generic bus chip selects */
54#define LEDS_CS 3
55#define LEDS_PHYS 0x100a0000
56
57#ifdef SIBYTE_HAVE_IDE
58#define IDE_CS 4
59#define IDE_PHYS 0x100b0000
60#define K_GPIO_GB_IDE 4
61#define K_INT_GB_IDE (K_INT_GPIO_0 + K_GPIO_GB_IDE)
62#endif
63
64#ifdef SIBYTE_HAVE_PCMCIA
65#define PCMCIA_CS 6
66#define PCMCIA_PHYS 0x11000000
67#define K_GPIO_PC_READY 9
68#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY)
69#endif
70
71#endif /* __ASM_SIBYTE_SWARM_H */
diff --git a/include/asm-mips/sibyte/trace_prof.h b/include/asm-mips/sibyte/trace_prof.h
new file mode 100644
index 000000000000..557792075e9a
--- /dev/null
+++ b/include/asm-mips/sibyte/trace_prof.h
@@ -0,0 +1,110 @@
1/*
2 * Copyright (C) 2001 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#ifndef __ASM_SIBYTE_TRACE_PROF_H
20#define __ASM_SIBYTE_TRACE_PROF_H
21
22#undef DBG
23#if SBPROF_TB_DEBUG
24#define DBG(a) a
25#else
26#define DBG(a)
27#endif
28
29#define SBPROF_TB_MAJOR 240
30#define DEVNAME "bcm1250_tbprof"
31
32typedef u_int64_t tb_sample_t[6*256];
33
34struct sbprof_tb {
35 int open;
36 tb_sample_t *sbprof_tbbuf;
37 int next_tb_sample;
38
39 volatile int tb_enable;
40 volatile int tb_armed;
41
42 wait_queue_head_t tb_sync;
43 wait_queue_head_t tb_read;
44};
45
46#define MAX_SAMPLE_BYTES (24*1024*1024)
47#define MAX_TBSAMPLE_BYTES (12*1024*1024)
48
49#define MAX_SAMPLES (MAX_SAMPLE_BYTES/sizeof(u_int32_t))
50#define TB_SAMPLE_SIZE (sizeof(tb_sample_t))
51#define MAX_TB_SAMPLES (MAX_TBSAMPLE_BYTES/TB_SAMPLE_SIZE)
52
53/* IOCTLs */
54#define SBPROF_ZBSTART _IOW('s', 0, int)
55#define SBPROF_ZBSTOP _IOW('s', 1, int)
56#define SBPROF_ZBWAITFULL _IOW('s', 2, int)
57
58/***************************************************************************
59 * Routines for gathering ZBbus profiles using trace buffer
60 ***************************************************************************/
61
62/* Requires: Already called zclk_timer_init with a value that won't
63 saturate 40 bits. No subsequent use of SCD performance counters
64 or trace buffer.
65 Effect: Starts gathering random ZBbus profiles using trace buffer. */
66extern int sbprof_zbprof_start(struct file *filp);
67
68/* Effect: Stops collection of ZBbus profiles */
69extern int sbprof_zbprof_stop(void);
70
71
72/***************************************************************************
73 * Routines for using 40-bit SCD cycle counter
74 *
75 * Client responsible for either handling interrupts or making sure
76 * the cycles counter never saturates, e.g., by doing
77 * zclk_timer_init(0) at least every 2^40 - 1 ZCLKs.
78 ***************************************************************************/
79
80/* Configures SCD counter 0 to count ZCLKs starting from val;
81 Configures SCD counters1,2,3 to count nothing.
82 Must not be called while gathering ZBbus profiles.
83
84unsigned long long val; */
85#define zclk_timer_init(val) \
86 __asm__ __volatile__ (".set push;" \
87 ".set mips64;" \
88 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
89 "sd %0, 0x10($8);" /* write val to counter0 */ \
90 "sd %1, 0($8);" /* config counter0 for zclks*/ \
91 ".set pop" \
92 : /* no outputs */ \
93 /* enable, counter0 */ \
94 : /* inputs */ "r"(val), "r" ((1ULL << 33) | 1ULL) \
95 : /* modifies */ "$8" )
96
97
98/* Reads SCD counter 0 and puts result in value
99 unsigned long long val; */
100#define zclk_get(val) \
101 __asm__ __volatile__ (".set push;" \
102 ".set mips64;" \
103 "la $8, 0xb00204c0;" /* SCD perf_cnt_cfg */ \
104 "ld %0, 0x10($8);" /* write val to counter0 */ \
105 ".set pop" \
106 : /* outputs */ "=r"(val) \
107 : /* inputs */ \
108 : /* modifies */ "$8" )
109
110#endif /* __ASM_SIBYTE_TRACE_PROF_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 00:18:06 -0500