diff options
author | Mark Mason <mmason@upwardaccess.com> | 2007-03-28 17:40:25 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-04-27 11:20:24 -0400 |
commit | 8deab1144b553548fb2f1b51affdd36dcd652aaa (patch) | |
tree | ca5c971933b74f73532381db5bb76dc2dbe34dec /include/asm-mips/sibyte/bcm1480_scd.h | |
parent | eacb9d61919db56482dcea7ec943c9508175dc16 (diff) |
[MIPS] Updated Sibyte headers
This is an update to the earlier patch for the sibyte headers, and superceeds
the previous patch. Changes were necessary to get the tbprof driver working
on the bcm1480.
Patch to update Sibyte header files to match master versions maintained
at Broadcom. This patch also corrects some whitespace problems, and
(hopefully) shouldn't introduce any new ones.
Signed-off-by: Mark Mason <mason@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/sibyte/bcm1480_scd.h')
-rw-r--r-- | include/asm-mips/sibyte/bcm1480_scd.h | 94 |
1 files changed, 32 insertions, 62 deletions
diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h index 648bed96780f..6111d6dcf117 100644 --- a/include/asm-mips/sibyte/bcm1480_scd.h +++ b/include/asm-mips/sibyte/bcm1480_scd.h | |||
@@ -10,7 +10,7 @@ | |||
10 | * | 10 | * |
11 | ********************************************************************* | 11 | ********************************************************************* |
12 | * | 12 | * |
13 | * Copyright 2000,2001,2002,2003 | 13 | * Copyright 2000,2001,2002,2003,2004,2005 |
14 | * Broadcom Corporation. All rights reserved. | 14 | * Broadcom Corporation. All rights reserved. |
15 | * | 15 | * |
16 | * This program is free software; you can redistribute it and/or | 16 | * This program is free software; you can redistribute it and/or |
@@ -78,6 +78,7 @@ | |||
78 | #define K_SYS_PART_BCM1280 0x1206 | 78 | #define K_SYS_PART_BCM1280 0x1206 |
79 | #define K_SYS_PART_BCM1455 0x1407 | 79 | #define K_SYS_PART_BCM1455 0x1407 |
80 | #define K_SYS_PART_BCM1255 0x1257 | 80 | #define K_SYS_PART_BCM1255 0x1257 |
81 | #define K_SYS_PART_BCM1158 0x1156 | ||
81 | 82 | ||
82 | /* | 83 | /* |
83 | * Manufacturing Information Register (Table 14) | 84 | * Manufacturing Information Register (Table 14) |
@@ -237,58 +238,42 @@ | |||
237 | * System Performance Counter Configuration Register (Table 31) | 238 | * System Performance Counter Configuration Register (Table 31) |
238 | * Register: PERF_CNT_CFG_0 | 239 | * Register: PERF_CNT_CFG_0 |
239 | * | 240 | * |
240 | * Since the clear/enable bits are moved compared to the | 241 | * SPC_CFG_SRC[0-3] is the same as the 1250. |
241 | * 1250 and there are more fields, this register will be BCM1480 specific. | 242 | * SPC_CFG_SRC[4-7] only exist on the 1480 |
243 | * The clear/enable bits are in different locations on the 1250 and 1480. | ||
242 | */ | 244 | */ |
243 | 245 | ||
244 | #define S_BCM1480_SPC_CFG_SRC0 0 | 246 | #define S_SPC_CFG_SRC4 32 |
245 | #define M_BCM1480_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC0) | 247 | #define M_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_SPC_CFG_SRC4) |
246 | #define V_BCM1480_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC0) | 248 | #define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC4) |
247 | #define G_BCM1480_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC0,M_BCM1480_SPC_CFG_SRC0) | 249 | #define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_SPC_CFG_SRC4,M_SPC_CFG_SRC4) |
248 | 250 | ||
249 | #define S_BCM1480_SPC_CFG_SRC1 8 | 251 | #define S_SPC_CFG_SRC5 40 |
250 | #define M_BCM1480_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC1) | 252 | #define M_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_SPC_CFG_SRC5) |
251 | #define V_BCM1480_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC1) | 253 | #define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC5) |
252 | #define G_BCM1480_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC1,M_BCM1480_SPC_CFG_SRC1) | 254 | #define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_SPC_CFG_SRC5,M_SPC_CFG_SRC5) |
253 | 255 | ||
254 | #define S_BCM1480_SPC_CFG_SRC2 16 | 256 | #define S_SPC_CFG_SRC6 48 |
255 | #define M_BCM1480_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC2) | 257 | #define M_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_SPC_CFG_SRC6) |
256 | #define V_BCM1480_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC2) | 258 | #define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC6) |
257 | #define G_BCM1480_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC2,M_BCM1480_SPC_CFG_SRC2) | 259 | #define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_SPC_CFG_SRC6,M_SPC_CFG_SRC6) |
258 | 260 | ||
259 | #define S_BCM1480_SPC_CFG_SRC3 24 | 261 | #define S_SPC_CFG_SRC7 56 |
260 | #define M_BCM1480_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC3) | 262 | #define M_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_SPC_CFG_SRC7) |
261 | #define V_BCM1480_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC3) | 263 | #define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC7) |
262 | #define G_BCM1480_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC3,M_BCM1480_SPC_CFG_SRC3) | 264 | #define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_SPC_CFG_SRC7,M_SPC_CFG_SRC7) |
263 | |||
264 | #define S_BCM1480_SPC_CFG_SRC4 32 | ||
265 | #define M_BCM1480_SPC_CFG_SRC4 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC4) | ||
266 | #define V_BCM1480_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC4) | ||
267 | #define G_BCM1480_SPC_CFG_SRC4(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC4,M_BCM1480_SPC_CFG_SRC4) | ||
268 | |||
269 | #define S_BCM1480_SPC_CFG_SRC5 40 | ||
270 | #define M_BCM1480_SPC_CFG_SRC5 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC5) | ||
271 | #define V_BCM1480_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC5) | ||
272 | #define G_BCM1480_SPC_CFG_SRC5(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC5,M_BCM1480_SPC_CFG_SRC5) | ||
273 | |||
274 | #define S_BCM1480_SPC_CFG_SRC6 48 | ||
275 | #define M_BCM1480_SPC_CFG_SRC6 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC6) | ||
276 | #define V_BCM1480_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC6) | ||
277 | #define G_BCM1480_SPC_CFG_SRC6(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC6,M_BCM1480_SPC_CFG_SRC6) | ||
278 | |||
279 | #define S_BCM1480_SPC_CFG_SRC7 56 | ||
280 | #define M_BCM1480_SPC_CFG_SRC7 _SB_MAKEMASK(8,S_BCM1480_SPC_CFG_SRC7) | ||
281 | #define V_BCM1480_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x,S_BCM1480_SPC_CFG_SRC7) | ||
282 | #define G_BCM1480_SPC_CFG_SRC7(x) _SB_GETVALUE(x,S_BCM1480_SPC_CFG_SRC7,M_BCM1480_SPC_CFG_SRC7) | ||
283 | 265 | ||
284 | /* | 266 | /* |
285 | * System Performance Counter Control Register (Table 32) | 267 | * System Performance Counter Control Register (Table 32) |
286 | * Register: PERF_CNT_CFG_1 | 268 | * Register: PERF_CNT_CFG_1 |
287 | * BCM1480 specific | 269 | * BCM1480 specific |
288 | */ | 270 | */ |
289 | 271 | #define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) | |
290 | #define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) | 272 | #define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) |
291 | #define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) | 273 | #if SIBYTE_HDR_FEATURE_CHIP(1480) |
274 | #define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR | ||
275 | #define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE | ||
276 | #endif | ||
292 | 277 | ||
293 | /* | 278 | /* |
294 | * System Performance Counters (Table 33) | 279 | * System Performance Counters (Table 33) |
@@ -405,20 +390,10 @@ | |||
405 | * Trace Control Register (Table 49) | 390 | * Trace Control Register (Table 49) |
406 | * Register: TRACE_CFG | 391 | * Register: TRACE_CFG |
407 | * | 392 | * |
408 | * Bits 0..8 are the same as the BCM1250, rest are different. | 393 | * BCM1480 changes to this register (other than location of the CUR_ADDR field) |
409 | * Entire register is redefined below. | 394 | * are defined below. |
410 | */ | 395 | */ |
411 | 396 | ||
412 | #define M_BCM1480_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0) | ||
413 | #define M_BCM1480_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1) | ||
414 | #define M_BCM1480_SCD_TRACE_CFG_START _SB_MAKEMASK1(2) | ||
415 | #define M_BCM1480_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3) | ||
416 | #define M_BCM1480_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4) | ||
417 | #define M_BCM1480_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5) | ||
418 | #define M_BCM1480_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6) | ||
419 | #define M_BCM1480_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7) | ||
420 | #define M_BCM1480_SCD_TRACE_CFG_FORCE_CNT _SB_MAKEMASK1(8) | ||
421 | |||
422 | #define S_BCM1480_SCD_TRACE_CFG_MODE 16 | 397 | #define S_BCM1480_SCD_TRACE_CFG_MODE 16 |
423 | #define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) | 398 | #define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2,S_BCM1480_SCD_TRACE_CFG_MODE) |
424 | #define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) | 399 | #define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_MODE) |
@@ -428,9 +403,4 @@ | |||
428 | #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 | 403 | #define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 |
429 | #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 | 404 | #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 |
430 | 405 | ||
431 | #define S_BCM1480_SCD_TRACE_CFG_CUR_ADDR 24 | ||
432 | #define M_BCM1480_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR) | ||
433 | #define V_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR) | ||
434 | #define G_BCM1480_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_BCM1480_SCD_TRACE_CFG_CUR_ADDR,M_BCM1480_SCD_TRACE_CFG_CUR_ADDR) | ||
435 | |||
436 | #endif /* _BCM1480_SCD_H */ | 406 | #endif /* _BCM1480_SCD_H */ |