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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-mips/serial.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
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diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_SERIAL_H
10#define _ASM_SERIAL_H
11
12#include <linux/config.h>
13
14/*
15 * This assumes you have a 1.8432 MHz clock for your UART.
16 *
17 * It'd be nice if someone built a serial card with a 24.576 MHz
18 * clock, since the 16550A is capable of handling a top speed of 1.5
19 * megabits/second; but this requires the faster clock.
20 */
21#define BASE_BAUD (1843200 / 16)
22
23/* Standard COM flags (except for COM4, because of the 8514 problem) */
24#ifdef CONFIG_SERIAL_DETECT_IRQ
25#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
26#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
27#else
28#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
29#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
30#endif
31
32#ifdef CONFIG_SERIAL_MANY_PORTS
33#define FOURPORT_FLAGS ASYNC_FOURPORT
34#define ACCENT_FLAGS 0
35#define BOCA_FLAGS 0
36#define HUB6_FLAGS 0
37#define RS_TABLE_SIZE 64
38#else
39#define RS_TABLE_SIZE
40#endif
41
42/*
43 * The following define the access methods for the HUB6 card. All
44 * access is through two ports for all 24 possible chips. The card is
45 * selected through the high 2 bits, the port on that card with the
46 * "middle" 3 bits, and the register on that port with the bottom
47 * 3 bits.
48 *
49 * While the access port and interrupt is configurable, the default
50 * port locations are 0x302 for the port control register, and 0x303
51 * for the data read/write register. Normally, the interrupt is at irq3
52 * but can be anything from 3 to 7 inclusive. Note that using 3 will
53 * require disabling com2.
54 */
55
56#define C_P(card,port) (((card)<<6|(port)<<3) + 1)
57
58#ifdef CONFIG_MACH_JAZZ
59#include <asm/jazz.h>
60
61#ifndef CONFIG_OLIVETTI_M700
62 /* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
63 exactly which ones ... XXX */
64#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
65#else
66/* but the M700 isn't such a strange beast */
67#define JAZZ_BASE_BAUD BASE_BAUD
68#endif
69
70#define _JAZZ_SERIAL_INIT(int, base) \
71 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
72 .iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
73 .io_type = SERIAL_IO_MEM }
74#define JAZZ_SERIAL_PORT_DEFNS \
75 _JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
76 _JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
77#else
78#define JAZZ_SERIAL_PORT_DEFNS
79#endif
80
81#ifdef CONFIG_MIPS_COBALT
82#include <asm/cobalt/cobalt.h>
83#define COBALT_BASE_BAUD (18432000 / 16)
84#define COBALT_SERIAL_PORT_DEFNS \
85 /* UART CLK PORT IRQ FLAGS */ \
86 { 0, COBALT_BASE_BAUD, 0xc800000, COBALT_SERIAL_IRQ, STD_COM_FLAGS }, /* ttyS0 */
87#else
88#define COBALT_SERIAL_PORT_DEFNS
89#endif
90
91/*
92 * Both Galileo boards have the same UART mappings.
93 */
94#if defined (CONFIG_MIPS_EV96100) || defined (CONFIG_MIPS_EV64120)
95#include <asm/galileo-boards/ev96100.h>
96#include <asm/galileo-boards/ev96100int.h>
97#define EV96100_SERIAL_PORT_DEFNS \
98 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
99 .flags = STD_COM_FLAGS, \
100 .iomem_base = EV96100_UART0_REGS_BASE, .iomem_reg_shift = 2, \
101 .io_type = SERIAL_IO_MEM }, \
102 { .baud_base = EV96100_BASE_BAUD, .irq = EV96100INT_UART_0, \
103 .flags = STD_COM_FLAGS, \
104 .iomem_base = EV96100_UART1_REGS_BASE, .iomem_reg_shift = 2, \
105 .io_type = SERIAL_IO_MEM },
106#else
107#define EV96100_SERIAL_PORT_DEFNS
108#endif
109
110#ifdef CONFIG_MIPS_ITE8172
111#include <asm/it8172/it8172.h>
112#include <asm/it8172/it8172_int.h>
113#include <asm/it8712.h>
114#define ITE_SERIAL_PORT_DEFNS \
115 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
116 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
117 { .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
118 .irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .type = 0x3 }, \
119 /* Smart Card Reader 0 */ \
120 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
121 .irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
122 /* Smart Card Reader 1 */ \
123 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
124 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
125#else
126#define ITE_SERIAL_PORT_DEFNS
127#endif
128
129#ifdef CONFIG_MIPS_IVR
130#include <asm/it8172/it8172.h>
131#include <asm/it8172/it8172_int.h>
132#define IVR_SERIAL_PORT_DEFNS \
133 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
134 .irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
135 /* Smart Card Reader 1 */ \
136 { .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
137 .irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
138#else
139#define IVR_SERIAL_PORT_DEFNS
140#endif
141
142#ifdef CONFIG_TOSHIBA_JMR3927
143#include <asm/jmr3927/jmr3927.h>
144#define TXX927_SERIAL_PORT_DEFNS \
145 { .baud_base = JMR3927_BASE_BAUD, .port = UART0_ADDR, .irq = UART0_INT, \
146 .flags = UART0_FLAGS, .type = 1 }, \
147 { .baud_base = JMR3927_BASE_BAUD, .port = UART1_ADDR, .irq = UART1_INT, \
148 .flags = UART1_FLAGS, .type = 1 },
149#else
150#define TXX927_SERIAL_PORT_DEFNS
151#endif
152
153#ifdef CONFIG_SERIAL_AU1X00
154#include <asm/mach-au1x00/au1000.h>
155#ifdef CONFIG_SOC_AU1000
156#define AU1000_SERIAL_PORT_DEFNS \
157 { .baud_base = 0, .port = UART0_ADDR, \
158 .iomem_base = (unsigned char *)UART0_ADDR, \
159 .irq = AU1000_UART0_INT, .flags = STD_COM_FLAGS, \
160 .iomem_reg_shift = 2 }, \
161 { .baud_base = 0, .port = UART1_ADDR, \
162 .iomem_base = (unsigned char *)UART1_ADDR, \
163 .irq = AU1000_UART1_INT, .flags = STD_COM_FLAGS, \
164 .iomem_reg_shift = 2 }, \
165 { .baud_base = 0, .port = UART2_ADDR, \
166 .iomem_base = (unsigned char *)UART2_ADDR, \
167 .irq = AU1000_UART2_INT, .flags = STD_COM_FLAGS, \
168 .iomem_reg_shift = 2 }, \
169 { .baud_base = 0, .port = UART3_ADDR, \
170 .iomem_base = (unsigned char *)UART3_ADDR, \
171 .irq = AU1000_UART3_INT, .flags = STD_COM_FLAGS, \
172 .iomem_reg_shift = 2 },
173#endif
174
175#ifdef CONFIG_SOC_AU1500
176#define AU1000_SERIAL_PORT_DEFNS \
177 { .baud_base = 0, .port = UART0_ADDR, \
178 .iomem_base = (unsigned char *)UART0_ADDR, \
179 .irq = AU1500_UART0_INT, .flags = STD_COM_FLAGS, \
180 .iomem_reg_shift = 2 }, \
181 { .baud_base = 0, .port = UART3_ADDR, \
182 .iomem_base = (unsigned char *)UART3_ADDR, \
183 .irq = AU1500_UART3_INT, .flags = STD_COM_FLAGS, \
184 .iomem_reg_shift = 2 },
185#endif
186
187#ifdef CONFIG_SOC_AU1100
188#define AU1000_SERIAL_PORT_DEFNS \
189 { .baud_base = 0, .port = UART0_ADDR, \
190 .iomem_base = (unsigned char *)UART0_ADDR, \
191 .irq = AU1100_UART0_INT, .flags = STD_COM_FLAGS, \
192 .iomem_reg_shift = 2 }, \
193 { .baud_base = 0, .port = UART1_ADDR, \
194 .iomem_base = (unsigned char *)UART1_ADDR, \
195 .irq = AU1100_UART1_INT, .flags = STD_COM_FLAGS, \
196 .iomem_reg_shift = 2 }, \
197 { .baud_base = 0, .port = UART3_ADDR, \
198 .iomem_base = (unsigned char *)UART3_ADDR, \
199 .irq = AU1100_UART3_INT, .flags = STD_COM_FLAGS, \
200 .iomem_reg_shift = 2 },
201#endif
202
203#ifdef CONFIG_SOC_AU1550
204#define AU1000_SERIAL_PORT_DEFNS \
205 { .baud_base = 0, .port = UART0_ADDR, \
206 .iomem_base = (unsigned char *)UART0_ADDR, \
207 .irq = AU1550_UART0_INT, .flags = STD_COM_FLAGS, \
208 .iomem_reg_shift = 2 }, \
209 { .baud_base = 0, .port = UART1_ADDR, \
210 .iomem_base = (unsigned char *)UART1_ADDR, \
211 .irq = AU1550_UART1_INT, .flags = STD_COM_FLAGS, \
212 .iomem_reg_shift = 2 }, \
213 { .baud_base = 0, .port = UART3_ADDR, \
214 .iomem_base = (unsigned char *)UART3_ADDR, \
215 .irq = AU1550_UART3_INT, .flags = STD_COM_FLAGS,\
216 .iomem_reg_shift = 2 },
217#endif
218
219#ifdef CONFIG_SOC_AU1200
220#define AU1000_SERIAL_PORT_DEFNS \
221 { .baud_base = 0, .port = UART0_ADDR, \
222 .iomem_base = (unsigned char *)UART0_ADDR, \
223 .irq = AU1200_UART0_INT, .flags = STD_COM_FLAGS, \
224 .iomem_reg_shift = 2 }, \
225 { .baud_base = 0, .port = UART1_ADDR, \
226 .iomem_base = (unsigned char *)UART1_ADDR, \
227 .irq = AU1200_UART1_INT, .flags = STD_COM_FLAGS, \
228 .iomem_reg_shift = 2 },
229#endif
230
231#else
232#define AU1000_SERIAL_PORT_DEFNS
233#endif
234
235#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
236#define STD_SERIAL_PORT_DEFNS \
237 /* UART CLK PORT IRQ FLAGS */ \
238 { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
239 { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
240 { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
241 { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
242
243#ifdef CONFIG_SERIAL_MANY_PORTS
244#define EXTRA_SERIAL_PORT_DEFNS \
245 { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
246 { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
247 { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
248 { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
249 { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \
250 { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \
251 { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \
252 { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \
253 { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \
254 { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \
255 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \
256 { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \
257 { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \
258 { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \
259 { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \
260 { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \
261 { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \
262 { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \
263 { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \
264 { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \
265 { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \
266 { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \
267 { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \
268 { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \
269 { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \
270 { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \
271 { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \
272 { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */
273#else /* CONFIG_SERIAL_MANY_PORTS */
274#define EXTRA_SERIAL_PORT_DEFNS
275#endif /* CONFIG_SERIAL_MANY_PORTS */
276
277#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
278#define STD_SERIAL_PORT_DEFNS
279#define EXTRA_SERIAL_PORT_DEFNS
280#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
281
282/* You can have up to four HUB6's in the system, but I've only
283 * included two cards here for a total of twelve ports.
284 */
285#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS))
286#define HUB6_SERIAL_PORT_DFNS \
287 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \
288 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \
289 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \
290 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \
291 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \
292 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \
293 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \
294 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \
295 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \
296 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \
297 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \
298 { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */
299#else
300#define HUB6_SERIAL_PORT_DFNS
301#endif
302
303#ifdef CONFIG_MOMENCO_JAGUAR_ATX
304/* Ordinary NS16552 duart with a 20MHz crystal. */
305#define JAGUAR_ATX_UART_CLK 20000000
306#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16)
307
308#define JAGUAR_ATX_SERIAL1_IRQ 6
309#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
310
311#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
312 { baud_base: JAGUAR_ATX_BASE_BAUD, irq: int, \
313 flags: (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
314 iomem_base: (u8 *) base, iomem_reg_shift: 2, \
315 io_type: SERIAL_IO_MEM }
316#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
317 _JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
318#else
319#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
320#endif
321
322#ifdef CONFIG_MOMENCO_OCELOT_3
323#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
324#define OCELOT_3_SERIAL_IRQ 6
325#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
326
327#define _OCELOT_3_SERIAL_INIT(int, base) \
328 { baud_base: OCELOT_3_BASE_BAUD, irq: int, \
329 flags: STD_COM_FLAGS, \
330 iomem_base: (u8 *) base, iomem_reg_shift: 2, \
331 io_type: SERIAL_IO_MEM }
332
333#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
334 _OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
335#else
336#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
337#endif
338
339#ifdef CONFIG_MOMENCO_OCELOT
340/* Ordinary NS16552 duart with a 20MHz crystal. */
341#define OCELOT_BASE_BAUD ( 20000000 / 16 )
342
343#define OCELOT_SERIAL1_IRQ 4
344#define OCELOT_SERIAL1_BASE 0xe0001020
345
346#define _OCELOT_SERIAL_INIT(int, base) \
347 { .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
348 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
349 .io_type = SERIAL_IO_MEM }
350#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
351 _OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
352#else
353#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
354#endif
355
356#ifdef CONFIG_MOMENCO_OCELOT_G
357/* Ordinary NS16552 duart with a 20MHz crystal. */
358#define OCELOT_G_BASE_BAUD ( 20000000 / 16 )
359
360#define OCELOT_G_SERIAL1_IRQ 4
361#if 0
362#define OCELOT_G_SERIAL1_BASE 0xe0001020
363#else
364#define OCELOT_G_SERIAL1_BASE 0xfd000020
365#endif
366
367#define _OCELOT_G_SERIAL_INIT(int, base) \
368 { .baud_base = OCELOT_G_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS,\
369 .iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
370 .io_type = SERIAL_IO_MEM }
371#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
372 _OCELOT_G_SERIAL_INIT(OCELOT_G_SERIAL1_IRQ, OCELOT_G_SERIAL1_BASE)
373#else
374#define MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS
375#endif
376
377#ifdef CONFIG_MOMENCO_OCELOT_C
378/* Ordinary NS16552 duart with a 20MHz crystal. */
379#define OCELOT_C_BASE_BAUD ( 20000000 / 16 )
380
381#define OCELOT_C_SERIAL1_IRQ 80
382#define OCELOT_C_SERIAL1_BASE 0xfd000020
383
384#define OCELOT_C_SERIAL2_IRQ 81
385#define OCELOT_C_SERIAL2_BASE 0xfd000000
386
387#define _OCELOT_C_SERIAL_INIT(int, base) \
388 { .baud_base = OCELOT_C_BASE_BAUD, \
389 .irq = (int), \
390 .flags = STD_COM_FLAGS, \
391 .iomem_base = (u8 *) base, \
392 .iomem_reg_shift = 2, \
393 .io_type = SERIAL_IO_MEM \
394 }
395#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
396 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL1_IRQ, OCELOT_C_SERIAL1_BASE), \
397 _OCELOT_C_SERIAL_INIT(OCELOT_C_SERIAL2_IRQ, OCELOT_C_SERIAL2_BASE)
398#else
399#define MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS
400#endif
401
402#ifdef CONFIG_DDB5477
403#include <asm/ddb5xxx/ddb5477.h>
404#define DDB5477_SERIAL_PORT_DEFNS \
405 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
406 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
407 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
408 { .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
409 .flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
410 .iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
411#else
412#define DDB5477_SERIAL_PORT_DEFNS
413#endif
414
415#ifdef CONFIG_SGI_IP32
416/*
417 * The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
418 * They are initialized in ip32_setup
419 */
420#define IP32_SERIAL_PORT_DEFNS \
421 {},{},
422#else
423#define IP32_SERIAL_PORT_DEFNS
424#endif /* CONFIG_SGI_IP32 */
425
426#define SERIAL_PORT_DFNS \
427 COBALT_SERIAL_PORT_DEFNS \
428 DDB5477_SERIAL_PORT_DEFNS \
429 EV96100_SERIAL_PORT_DEFNS \
430 EXTRA_SERIAL_PORT_DEFNS \
431 HUB6_SERIAL_PORT_DFNS \
432 IP32_SERIAL_PORT_DEFNS \
433 ITE_SERIAL_PORT_DEFNS \
434 IVR_SERIAL_PORT_DEFNS \
435 JAZZ_SERIAL_PORT_DEFNS \
436 STD_SERIAL_PORT_DEFNS \
437 MOMENCO_OCELOT_G_SERIAL_PORT_DEFNS \
438 MOMENCO_OCELOT_C_SERIAL_PORT_DEFNS \
439 MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
440 MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
441 TXX927_SERIAL_PORT_DEFNS \
442 AU1000_SERIAL_PORT_DEFNS
443
444#endif /* _ASM_SERIAL_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 17:29:04 -0500