[MIPS] local_r4k_flush_cache_page fix

    
If dcache_size != icache_size or dcache_size != scache_size, or
set-associative cache, icache/scache does not flushed properly.  Make
blast_?cache_page_indexed() masks its index value correctly.  Also,
use physical address for physically indexed pcache/scache.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 2 insertions, 1 deletions

diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
index 9632c27dad15..0bcb79a58ee9 100644
--- a/include/asm-mips/r4kcache.h
+++ b/include/asm-mips/r4kcache.h
@@ -257,7 +257,8 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page)	\
                                                                         \
 static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
 {                                                                       \
-        unsigned long start = page;                                     \
+        unsigned long indexmask = current_cpu_data.desc.waysize - 1;    \
+        unsigned long start = INDEX_BASE + (page & indexmask);          \
         unsigned long end = start + PAGE_SIZE;                          \
         unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
         unsigned long ws_end = current_cpu_data.desc.ways <<            \