Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

1 files changed, 88 insertions, 0 deletions

diff --git a/include/asm-mips/prefetch.h b/include/asm-mips/prefetch.h
new file mode 100644
index 000000000000..71293ec1657c
--- /dev/null
+++ b/include/asm-mips/prefetch.h
@@ -0,0 +1,88 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 by Ralf Baechle
+ */
+#ifndef __ASM_PREFETCH_H
+#define __ASM_PREFETCH_H
+
+#include <linux/config.h>
+
+/*
+ * R5000 and RM5200 implements pref and prefx instructions but they're nops, so
+ * rather than wasting time we pretend these processors don't support
+ * prefetching at all.
+ *
+ * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained,
+ * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore.
+ *
+ * Hell (and the book on my shelf I can't open ...) know what the R8000 does.
+ *
+ * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements
+ * Pref_PrepareForStore also.
+ *
+ * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's
+ * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
+ * current versions due to erratum G105.
+ *
+ * VR7701 only implements the Load prefetch.
+ *
+ * Finally MIPS32 and MIPS64 implement all of the following hints.
+ */
+
+#define Pref_Load                       0
+#define Pref_Store                      1
+                                                /* 2 and 3 are reserved */
+#define Pref_LoadStreamed               4
+#define Pref_StoreStreamed              5
+#define Pref_LoadRetained               6
+#define Pref_StoreRetained              7
+                                                /* 8 ... 24 are reserved */
+#define Pref_WriteBackInvalidate        25
+#define Pref_PrepareForStore            30
+
+#ifdef __ASSEMBLY__
+
+        .macro  __pref hint addr
+#ifdef CONFIG_CPU_HAS_PREFETCH
+        pref    \hint, \addr
+#endif
+        .endm
+
+        .macro  pref_load addr
+        __pref  Pref_Load, \addr
+        .endm
+
+        .macro  pref_store addr
+        __pref  Pref_Store, \addr
+        .endm
+
+        .macro  pref_load_streamed addr
+        __pref  Pref_LoadStreamed, \addr
+        .endm
+
+        .macro  pref_store_streamed addr
+        __pref  Pref_StoreStreamed, \addr
+        .endm
+
+        .macro  pref_load_retained addr
+        __pref  Pref_LoadRetained, \addr
+        .endm
+
+        .macro  pref_store_retained addr
+        __pref  Pref_StoreRetained, \addr
+        .endm
+
+        .macro  pref_wback_inv addr
+        __pref  Pref_WriteBackInvalidate, \addr
+        .endm
+
+        .macro  pref_prepare_for_store addr
+        __pref  Pref_PrepareForStore, \addr
+        .endm
+
+#endif
+
+#endif /* __ASM_PREFETCH_H */