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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2006-05-03 14:56:43 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-06-05 19:15:15 -0400
commit79e0bc37255a4b934291b4d3ea5a4561fbd78da4 (patch)
tree5505705aba14aa4560bbd875f50b5f15f9e18f29 /include/asm-mips/pgtable.h
parent9370b35175ca43fad7d24bc7b391473f3becbee8 (diff)
[MIPS] Fix mprotect() syscall for MIPS32 w/36-bit physical address support
Fix mprotect() syscall for MIPS32 CPUs with 36-bit physical address support: pte_modify() macro didn't clear the hardware page protection bits before modifying... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/pgtable.h')
-rw-r--r--include/asm-mips/pgtable.h5
1 files changed, 3 insertions, 2 deletions
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index f80fe75c7800..d0af2a3b0152 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -353,8 +353,9 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
353#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) 353#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
354static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 354static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
355{ 355{
356 pte.pte_low &= _PAGE_CHG_MASK; 356 pte.pte_low &= _PAGE_CHG_MASK;
357 pte.pte_low |= pgprot_val(newprot); 357 pte.pte_high &= ~0x3f;
358 pte.pte_low |= pgprot_val(newprot);
358 pte.pte_high |= pgprot_val(newprot) & 0x3f; 359 pte.pte_high |= pgprot_val(newprot) & 0x3f;
359 return pte; 360 return pte;
360} 361}