diff options
author | Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> | 2007-07-09 00:10:55 -0400 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2007-07-10 12:33:04 -0400 |
commit | c99cabf034d42c9e4a9c1ed9dfd26411b2fb9b57 (patch) | |
tree | 30a696c0ab083427b8865418004f2a8bab96be44 /include/asm-mips/nile4.h | |
parent | ecd27b92fbb41f779d857632a69bd45dbaf0f915 (diff) |
[MIPS] remove LASAT Networks platforms support
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/nile4.h')
-rw-r--r-- | include/asm-mips/nile4.h | 310 |
1 files changed, 0 insertions, 310 deletions
diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h deleted file mode 100644 index c3ca959aa4d9..000000000000 --- a/include/asm-mips/nile4.h +++ /dev/null | |||
@@ -1,310 +0,0 @@ | |||
1 | /* | ||
2 | * asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions | ||
3 | * | ||
4 | * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com> | ||
5 | * Sony Software Development Center Europe (SDCE), Brussels | ||
6 | * | ||
7 | * This file is based on the following documentation: | ||
8 | * | ||
9 | * NEC Vrc 5074 System Controller Data Sheet, June 1998 | ||
10 | */ | ||
11 | |||
12 | #ifndef _ASM_NILE4_H | ||
13 | #define _ASM_NILE4_H | ||
14 | |||
15 | #define NILE4_BASE 0xbfa00000 | ||
16 | #define NILE4_SIZE 0x00200000 /* 2 MB */ | ||
17 | |||
18 | |||
19 | /* | ||
20 | * Physical Device Address Registers (PDARs) | ||
21 | */ | ||
22 | |||
23 | #define NILE4_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */ | ||
24 | #define NILE4_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */ | ||
25 | #define NILE4_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */ | ||
26 | #define NILE4_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */ | ||
27 | #define NILE4_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */ | ||
28 | #define NILE4_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */ | ||
29 | #define NILE4_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */ | ||
30 | #define NILE4_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */ | ||
31 | #define NILE4_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */ | ||
32 | #define NILE4_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */ | ||
33 | #define NILE4_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */ | ||
34 | #define NILE4_INTCS 0x0070 /* Controller Internal Registers and Devices */ | ||
35 | /* [R/W] */ | ||
36 | #define NILE4_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */ | ||
37 | |||
38 | |||
39 | /* | ||
40 | * CPU Interface Registers | ||
41 | */ | ||
42 | |||
43 | #define NILE4_CPUSTAT 0x0080 /* CPU Status [R/W] */ | ||
44 | #define NILE4_INTCTRL 0x0088 /* Interrupt Control [R/W] */ | ||
45 | #define NILE4_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */ | ||
46 | #define NILE4_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */ | ||
47 | /* Enable [R/W] */ | ||
48 | #define NILE4_INTCLR 0x00A0 /* Interrupt Clear [R/W] */ | ||
49 | #define NILE4_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */ | ||
50 | |||
51 | |||
52 | /* | ||
53 | * Memory-Interface Registers | ||
54 | */ | ||
55 | |||
56 | #define NILE4_MEMCTRL 0x00C0 /* Memory Control */ | ||
57 | #define NILE4_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */ | ||
58 | #define NILE4_CHKERR 0x00D0 /* Memory Check Error Status [R] */ | ||
59 | |||
60 | |||
61 | /* | ||
62 | * PCI-Bus Registers | ||
63 | */ | ||
64 | |||
65 | #define NILE4_PCICTRL 0x00E0 /* PCI Control [R/W] */ | ||
66 | #define NILE4_PCIARB 0x00E8 /* PCI Arbiter [R/W] */ | ||
67 | #define NILE4_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */ | ||
68 | #define NILE4_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */ | ||
69 | #define NILE4_PCIERR 0x00B8 /* PCI Error [R/W] */ | ||
70 | |||
71 | |||
72 | /* | ||
73 | * Local-Bus Registers | ||
74 | */ | ||
75 | |||
76 | #define NILE4_LCNFG 0x0100 /* Local Bus Configuration [R/W] */ | ||
77 | #define NILE4_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */ | ||
78 | #define NILE4_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */ | ||
79 | #define NILE4_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */ | ||
80 | #define NILE4_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */ | ||
81 | #define NILE4_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */ | ||
82 | #define NILE4_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */ | ||
83 | #define NILE4_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */ | ||
84 | #define NILE4_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */ | ||
85 | /* Enables [R/W] */ | ||
86 | #define NILE4_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */ | ||
87 | #define NILE4_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */ | ||
88 | |||
89 | |||
90 | /* | ||
91 | * DMA Registers | ||
92 | */ | ||
93 | |||
94 | #define NILE4_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */ | ||
95 | #define NILE4_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */ | ||
96 | #define NILE4_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */ | ||
97 | #define NILE4_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */ | ||
98 | #define NILE4_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */ | ||
99 | #define NILE4_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */ | ||
100 | |||
101 | |||
102 | /* | ||
103 | * Timer Registers | ||
104 | */ | ||
105 | |||
106 | #define NILE4_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */ | ||
107 | #define NILE4_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */ | ||
108 | #define NILE4_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */ | ||
109 | #define NILE4_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */ | ||
110 | #define NILE4_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */ | ||
111 | #define NILE4_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */ | ||
112 | #define NILE4_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */ | ||
113 | #define NILE4_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */ | ||
114 | |||
115 | |||
116 | /* | ||
117 | * PCI Configuration Space Registers | ||
118 | */ | ||
119 | |||
120 | #define NILE4_PCI_BASE 0x0200 | ||
121 | |||
122 | #define NILE4_VID 0x0200 /* PCI Vendor ID [R] */ | ||
123 | #define NILE4_DID 0x0202 /* PCI Device ID [R] */ | ||
124 | #define NILE4_PCICMD 0x0204 /* PCI Command [R/W] */ | ||
125 | #define NILE4_PCISTS 0x0206 /* PCI Status [R/W] */ | ||
126 | #define NILE4_REVID 0x0208 /* PCI Revision ID [R] */ | ||
127 | #define NILE4_CLASS 0x0209 /* PCI Class Code [R] */ | ||
128 | #define NILE4_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */ | ||
129 | #define NILE4_MLTIM 0x020D /* PCI Latency Timer [R/W] */ | ||
130 | #define NILE4_HTYPE 0x020E /* PCI Header Type [R] */ | ||
131 | #define NILE4_BIST 0x020F /* BIST [R] (unimplemented) */ | ||
132 | #define NILE4_BARC 0x0210 /* PCI Base Address Register Control [R/W] */ | ||
133 | #define NILE4_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */ | ||
134 | #define NILE4_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */ | ||
135 | #define NILE4_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */ | ||
136 | /* (unimplemented) */ | ||
137 | #define NILE4_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */ | ||
138 | #define NILE4_SSID 0x022E /* PCI Sub-System ID [R/W] */ | ||
139 | #define NILE4_ROM 0x0230 /* Expansion ROM Base Address [R] */ | ||
140 | /* (unimplemented) */ | ||
141 | #define NILE4_INTLIN 0x023C /* PCI Interrupt Line [R/W] */ | ||
142 | #define NILE4_INTPIN 0x023D /* PCI Interrupt Pin [R] */ | ||
143 | #define NILE4_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */ | ||
144 | #define NILE4_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */ | ||
145 | #define NILE4_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */ | ||
146 | #define NILE4_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */ | ||
147 | #define NILE4_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */ | ||
148 | #define NILE4_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */ | ||
149 | #define NILE4_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */ | ||
150 | #define NILE4_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */ | ||
151 | #define NILE4_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */ | ||
152 | #define NILE4_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */ | ||
153 | |||
154 | |||
155 | /* | ||
156 | * Serial-Port Registers | ||
157 | */ | ||
158 | |||
159 | #define NILE4_UART_BASE 0x0300 | ||
160 | |||
161 | #define NILE4_UARTRBR 0x0300 /* UART Receiver Data Buffer [R] */ | ||
162 | #define NILE4_UARTTHR 0x0300 /* UART Transmitter Data Holding [W] */ | ||
163 | #define NILE4_UARTIER 0x0308 /* UART Interrupt Enable [R/W] */ | ||
164 | #define NILE4_UARTDLL 0x0300 /* UART Divisor Latch LSB [R/W] */ | ||
165 | #define NILE4_UARTDLM 0x0308 /* UART Divisor Latch MSB [R/W] */ | ||
166 | #define NILE4_UARTIIR 0x0310 /* UART Interrupt ID [R] */ | ||
167 | #define NILE4_UARTFCR 0x0310 /* UART FIFO Control [W] */ | ||
168 | #define NILE4_UARTLCR 0x0318 /* UART Line Control [R/W] */ | ||
169 | #define NILE4_UARTMCR 0x0320 /* UART Modem Control [R/W] */ | ||
170 | #define NILE4_UARTLSR 0x0328 /* UART Line Status [R/W] */ | ||
171 | #define NILE4_UARTMSR 0x0330 /* UART Modem Status [R/W] */ | ||
172 | #define NILE4_UARTSCR 0x0338 /* UART Scratch [R/W] */ | ||
173 | |||
174 | #define NILE4_UART_BASE_BAUD 520833 /* 100 MHz / 12 / 16 */ | ||
175 | |||
176 | |||
177 | /* | ||
178 | * Interrupt Lines | ||
179 | */ | ||
180 | |||
181 | #define NILE4_INT_CPCE 0 /* CPU-Interface Parity-Error Interrupt */ | ||
182 | #define NILE4_INT_CNTD 1 /* CPU No-Target Decode Interrupt */ | ||
183 | #define NILE4_INT_MCE 2 /* Memory-Check Error Interrupt */ | ||
184 | #define NILE4_INT_DMA 3 /* DMA Controller Interrupt */ | ||
185 | #define NILE4_INT_UART 4 /* UART Interrupt */ | ||
186 | #define NILE4_INT_WDOG 5 /* Watchdog Timer Interrupt */ | ||
187 | #define NILE4_INT_GPT 6 /* General-Purpose Timer Interrupt */ | ||
188 | #define NILE4_INT_LBRTD 7 /* Local-Bus Ready Timer Interrupt */ | ||
189 | #define NILE4_INT_INTA 8 /* PCI Interrupt Signal INTA# */ | ||
190 | #define NILE4_INT_INTB 9 /* PCI Interrupt Signal INTB# */ | ||
191 | #define NILE4_INT_INTC 10 /* PCI Interrupt Signal INTC# */ | ||
192 | #define NILE4_INT_INTD 11 /* PCI Interrupt Signal INTD# */ | ||
193 | #define NILE4_INT_INTE 12 /* PCI Interrupt Signal INTE# (ISA cascade) */ | ||
194 | #define NILE4_INT_RESV 13 /* Reserved */ | ||
195 | #define NILE4_INT_PCIS 14 /* PCI SERR# Interrupt */ | ||
196 | #define NILE4_INT_PCIE 15 /* PCI Internal Error Interrupt */ | ||
197 | |||
198 | |||
199 | /* | ||
200 | * Nile 4 Register Access | ||
201 | */ | ||
202 | |||
203 | static inline void nile4_sync(void) | ||
204 | { | ||
205 | volatile u32 *p = (volatile u32 *)0xbfc00000; | ||
206 | (void)(*p); | ||
207 | } | ||
208 | |||
209 | static inline void nile4_out32(u32 offset, u32 val) | ||
210 | { | ||
211 | *(volatile u32 *)(NILE4_BASE+offset) = val; | ||
212 | nile4_sync(); | ||
213 | } | ||
214 | |||
215 | static inline u32 nile4_in32(u32 offset) | ||
216 | { | ||
217 | u32 val = *(volatile u32 *)(NILE4_BASE+offset); | ||
218 | nile4_sync(); | ||
219 | return val; | ||
220 | } | ||
221 | |||
222 | static inline void nile4_out16(u32 offset, u16 val) | ||
223 | { | ||
224 | *(volatile u16 *)(NILE4_BASE+offset) = val; | ||
225 | nile4_sync(); | ||
226 | } | ||
227 | |||
228 | static inline u16 nile4_in16(u32 offset) | ||
229 | { | ||
230 | u16 val = *(volatile u16 *)(NILE4_BASE+offset); | ||
231 | nile4_sync(); | ||
232 | return val; | ||
233 | } | ||
234 | |||
235 | static inline void nile4_out8(u32 offset, u8 val) | ||
236 | { | ||
237 | *(volatile u8 *)(NILE4_BASE+offset) = val; | ||
238 | nile4_sync(); | ||
239 | } | ||
240 | |||
241 | static inline u8 nile4_in8(u32 offset) | ||
242 | { | ||
243 | u8 val = *(volatile u8 *)(NILE4_BASE+offset); | ||
244 | nile4_sync(); | ||
245 | return val; | ||
246 | } | ||
247 | |||
248 | |||
249 | /* | ||
250 | * Physical Device Address Registers | ||
251 | */ | ||
252 | |||
253 | extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width, | ||
254 | int on_memory_bus, int visible); | ||
255 | |||
256 | |||
257 | /* | ||
258 | * PCI Master Registers | ||
259 | */ | ||
260 | |||
261 | #define NILE4_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */ | ||
262 | #define NILE4_PCICMD_IO 1 /* PCI I/O Space */ | ||
263 | #define NILE4_PCICMD_MEM 3 /* PCI Memory Space */ | ||
264 | #define NILE4_PCICMD_CFG 5 /* PCI Configuration Space */ | ||
265 | |||
266 | |||
267 | /* | ||
268 | * PCI Address Spaces | ||
269 | * | ||
270 | * Note that these are multiplexed using PCIINIT[01]! | ||
271 | */ | ||
272 | |||
273 | #define NILE4_PCI_IO_BASE 0xa6000000 | ||
274 | #define NILE4_PCI_MEM_BASE 0xa8000000 | ||
275 | #define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE | ||
276 | #define NILE4_PCI_IACK_BASE NILE4_PCI_IO_BASE | ||
277 | |||
278 | |||
279 | extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr); | ||
280 | |||
281 | |||
282 | /* | ||
283 | * Interrupt Programming | ||
284 | */ | ||
285 | |||
286 | #define NUM_I8259_INTERRUPTS 16 | ||
287 | #define NUM_NILE4_INTERRUPTS 16 | ||
288 | |||
289 | #define IRQ_I8259_CASCADE NILE4_INT_INTE | ||
290 | #define is_i8259_irq(irq) ((irq) < NUM_I8259_INTERRUPTS) | ||
291 | #define nile4_to_irq(n) ((n)+NUM_I8259_INTERRUPTS) | ||
292 | #define irq_to_nile4(n) ((n)-NUM_I8259_INTERRUPTS) | ||
293 | |||
294 | extern void nile4_map_irq(int nile4_irq, int cpu_irq); | ||
295 | extern void nile4_map_irq_all(int cpu_irq); | ||
296 | extern void nile4_enable_irq(unsigned int nile4_irq); | ||
297 | extern void nile4_disable_irq(unsigned int nile4_irq); | ||
298 | extern void nile4_disable_irq_all(void); | ||
299 | extern u16 nile4_get_irq_stat(int cpu_irq); | ||
300 | extern void nile4_enable_irq_output(int cpu_irq); | ||
301 | extern void nile4_disable_irq_output(int cpu_irq); | ||
302 | extern void nile4_set_pci_irq_polarity(int pci_irq, int high); | ||
303 | extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level); | ||
304 | extern void nile4_clear_irq(int nile4_irq); | ||
305 | extern void nile4_clear_irq_mask(u32 mask); | ||
306 | extern u8 nile4_i8259_iack(void); | ||
307 | extern void nile4_dump_irq_status(void); /* Debug */ | ||
308 | |||
309 | #endif | ||
310 | |||