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authorRalf Baechle <ralf@linux-mips.org>2006-11-29 20:14:45 -0500
committerRalf Baechle <ralf@linux-mips.org>2006-11-29 20:14:45 -0500
commit2472d0b519c9634d89420064315c0926149947aa (patch)
tree6f5d871af3c77ce80fcc7140e2d3ce1e375e74aa /include/asm-mips/mipsregs.h
parent583bb86fbb9e85287f020fe4eb5352a0ec3c66a3 (diff)
[MIPS] Remove unused R10000 performance counter definitions.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mipsregs.h')
-rw-r--r--include/asm-mips/mipsregs.h56
1 files changed, 0 insertions, 56 deletions
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
index 1f318d707998..9985cb7c16e7 100644
--- a/include/asm-mips/mipsregs.h
+++ b/include/asm-mips/mipsregs.h
@@ -545,62 +545,6 @@
545#define MIPS_FPIR_L (_ULCAST_(1) << 21) 545#define MIPS_FPIR_L (_ULCAST_(1) << 21)
546#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 546#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
547 547
548/*
549 * R10000 performance counter definitions.
550 *
551 * FIXME: The R10000 performance counter opens a nice way to implement CPU
552 * time accounting with a precission of one cycle. I don't have
553 * R10000 silicon but just a manual, so ...
554 */
555
556/*
557 * Events counted by counter #0
558 */
559#define CE0_CYCLES 0
560#define CE0_INSN_ISSUED 1
561#define CE0_LPSC_ISSUED 2
562#define CE0_S_ISSUED 3
563#define CE0_SC_ISSUED 4
564#define CE0_SC_FAILED 5
565#define CE0_BRANCH_DECODED 6
566#define CE0_QW_WB_SECONDARY 7
567#define CE0_CORRECTED_ECC_ERRORS 8
568#define CE0_ICACHE_MISSES 9
569#define CE0_SCACHE_I_MISSES 10
570#define CE0_SCACHE_I_WAY_MISSPREDICTED 11
571#define CE0_EXT_INTERVENTIONS_REQ 12
572#define CE0_EXT_INVALIDATE_REQ 13
573#define CE0_VIRTUAL_COHERENCY_COND 14
574#define CE0_INSN_GRADUATED 15
575
576/*
577 * Events counted by counter #1
578 */
579#define CE1_CYCLES 0
580#define CE1_INSN_GRADUATED 1
581#define CE1_LPSC_GRADUATED 2
582#define CE1_S_GRADUATED 3
583#define CE1_SC_GRADUATED 4
584#define CE1_FP_INSN_GRADUATED 5
585#define CE1_QW_WB_PRIMARY 6
586#define CE1_TLB_REFILL 7
587#define CE1_BRANCH_MISSPREDICTED 8
588#define CE1_DCACHE_MISS 9
589#define CE1_SCACHE_D_MISSES 10
590#define CE1_SCACHE_D_WAY_MISSPREDICTED 11
591#define CE1_EXT_INTERVENTION_HITS 12
592#define CE1_EXT_INVALIDATE_REQ 13
593#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
594#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
595
596/*
597 * These flags define in which privilege mode the counters count events
598 */
599#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
600#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
601#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
602#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
603
604#ifndef __ASSEMBLY__ 548#ifndef __ASSEMBLY__
605 549
606/* 550/*