aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips/mipsmtregs.h
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:15 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:15 -0400
commit21a151d8ca3aa74ee79f9791a9d4dc370d3e0636 (patch)
tree8556b3a32ded6a49225beb4a7aa4447cc87a0e00 /include/asm-mips/mipsmtregs.h
parent49a89efbbbcc178a39555c43bd59a7593c429664 (diff)
[MIPS] checkfiles: Fix "need space after that ','" errors.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mipsmtregs.h')
-rw-r--r--include/asm-mips/mipsmtregs.h60
1 files changed, 30 insertions, 30 deletions
diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h
index 294bca12cd3f..5a2f8a3a6a1f 100644
--- a/include/asm-mips/mipsmtregs.h
+++ b/include/asm-mips/mipsmtregs.h
@@ -41,27 +41,27 @@
41 * Macros for use in assembly language code 41 * Macros for use in assembly language code
42 */ 42 */
43 43
44#define CP0_MVPCONTROL $0,1 44#define CP0_MVPCONTROL $0, 1
45#define CP0_MVPCONF0 $0,2 45#define CP0_MVPCONF0 $0, 2
46#define CP0_MVPCONF1 $0,3 46#define CP0_MVPCONF1 $0, 3
47#define CP0_VPECONTROL $1,1 47#define CP0_VPECONTROL $1, 1
48#define CP0_VPECONF0 $1,2 48#define CP0_VPECONF0 $1, 2
49#define CP0_VPECONF1 $1,3 49#define CP0_VPECONF1 $1, 3
50#define CP0_YQMASK $1,4 50#define CP0_YQMASK $1, 4
51#define CP0_VPESCHEDULE $1,5 51#define CP0_VPESCHEDULE $1, 5
52#define CP0_VPESCHEFBK $1,6 52#define CP0_VPESCHEFBK $1, 6
53#define CP0_TCSTATUS $2,1 53#define CP0_TCSTATUS $2, 1
54#define CP0_TCBIND $2,2 54#define CP0_TCBIND $2, 2
55#define CP0_TCRESTART $2,3 55#define CP0_TCRESTART $2, 3
56#define CP0_TCHALT $2,4 56#define CP0_TCHALT $2, 4
57#define CP0_TCCONTEXT $2,5 57#define CP0_TCCONTEXT $2, 5
58#define CP0_TCSCHEDULE $2,6 58#define CP0_TCSCHEDULE $2, 6
59#define CP0_TCSCHEFBK $2,7 59#define CP0_TCSCHEFBK $2, 7
60#define CP0_SRSCONF0 $6,1 60#define CP0_SRSCONF0 $6, 1
61#define CP0_SRSCONF1 $6,2 61#define CP0_SRSCONF1 $6, 2
62#define CP0_SRSCONF2 $6,3 62#define CP0_SRSCONF2 $6, 3
63#define CP0_SRSCONF3 $6,4 63#define CP0_SRSCONF3 $6, 4
64#define CP0_SRSCONF4 $6,5 64#define CP0_SRSCONF4 $6, 5
65 65
66#endif 66#endif
67 67
@@ -291,7 +291,7 @@ static inline void ehb(void)
291 __res; \ 291 __res; \
292}) 292})
293 293
294#define mftr(rt,u,sel) \ 294#define mftr(rt, u, sel) \
295({ \ 295({ \
296 unsigned long __res; \ 296 unsigned long __res; \
297 \ 297 \
@@ -315,7 +315,7 @@ do { \
315 : : "r" (v)); \ 315 : : "r" (v)); \
316} while (0) 316} while (0)
317 317
318#define mttc0(rd,sel,v) \ 318#define mttc0(rd, sel, v) \
319({ \ 319({ \
320 __asm__ __volatile__( \ 320 __asm__ __volatile__( \
321 " .set push \n" \ 321 " .set push \n" \
@@ -330,7 +330,7 @@ do { \
330}) 330})
331 331
332 332
333#define mttr(rd,u,sel,v) \ 333#define mttr(rd, u, sel, v) \
334({ \ 334({ \
335 __asm__ __volatile__( \ 335 __asm__ __volatile__( \
336 "mttr %0," #rd ", " #u ", " #sel \ 336 "mttr %0," #rd ", " #u ", " #sel \
@@ -362,7 +362,7 @@ do { \
362#define write_vpe_c0_config1(val) mttc0(16, 1, val) 362#define write_vpe_c0_config1(val) mttc0(16, 1, val)
363#define read_vpe_c0_config7() mftc0(16, 7) 363#define read_vpe_c0_config7() mftc0(16, 7)
364#define write_vpe_c0_config7(val) mttc0(16, 7, val) 364#define write_vpe_c0_config7(val) mttc0(16, 7, val)
365#define read_vpe_c0_ebase() mftc0(15,1) 365#define read_vpe_c0_ebase() mftc0(15, 1)
366#define write_vpe_c0_ebase(val) mttc0(15, 1, val) 366#define write_vpe_c0_ebase(val) mttc0(15, 1, val)
367#define write_vpe_c0_compare(val) mttc0(11, 0, val) 367#define write_vpe_c0_compare(val) mttc0(11, 0, val)
368#define read_vpe_c0_badvaddr() mftc0(8, 0) 368#define read_vpe_c0_badvaddr() mftc0(8, 0)
@@ -372,15 +372,15 @@ do { \
372 372
373/* TC */ 373/* TC */
374#define read_tc_c0_tcstatus() mftc0(2, 1) 374#define read_tc_c0_tcstatus() mftc0(2, 1)
375#define write_tc_c0_tcstatus(val) mttc0(2,1,val) 375#define write_tc_c0_tcstatus(val) mttc0(2, 1, val)
376#define read_tc_c0_tcbind() mftc0(2, 2) 376#define read_tc_c0_tcbind() mftc0(2, 2)
377#define write_tc_c0_tcbind(val) mttc0(2,2,val) 377#define write_tc_c0_tcbind(val) mttc0(2, 2, val)
378#define read_tc_c0_tcrestart() mftc0(2, 3) 378#define read_tc_c0_tcrestart() mftc0(2, 3)
379#define write_tc_c0_tcrestart(val) mttc0(2,3,val) 379#define write_tc_c0_tcrestart(val) mttc0(2, 3, val)
380#define read_tc_c0_tchalt() mftc0(2, 4) 380#define read_tc_c0_tchalt() mftc0(2, 4)
381#define write_tc_c0_tchalt(val) mttc0(2,4,val) 381#define write_tc_c0_tchalt(val) mttc0(2, 4, val)
382#define read_tc_c0_tccontext() mftc0(2, 5) 382#define read_tc_c0_tccontext() mftc0(2, 5)
383#define write_tc_c0_tccontext(val) mttc0(2,5,val) 383#define write_tc_c0_tccontext(val) mttc0(2, 5, val)
384 384
385/* GPR */ 385/* GPR */
386#define read_tc_gpr_sp() mftgpr(29) 386#define read_tc_gpr_sp() mftgpr(29)