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authorChris Dearman <chris@mips.com>2007-04-27 10:58:41 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-06-14 13:25:14 -0400
commitb72c05262298cc2ac92edb657f5ea3a97ad5ea3d (patch)
tree41819862465a5cd6b89eb7b8bff3a79a5817064f /include/asm-mips/mips-boards
parenteedab661a51966c454e38c17266a531aa58b4a98 (diff)
[MIPS] Malta: Fix for SOCitSC based Maltas
And an attempt to tidy up the core/controller differences. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mips-boards')
-rw-r--r--include/asm-mips/mips-boards/generic.h22
-rw-r--r--include/asm-mips/mips-boards/msc01_pci.h1
2 files changed, 20 insertions, 3 deletions
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
index b98f1658cfd0..c8ebcc3e1267 100644
--- a/include/asm-mips/mips-boards/generic.h
+++ b/include/asm-mips/mips-boards/generic.h
@@ -73,12 +73,28 @@
73 * CoreEMUL with Bonito System Controller is treated like a Core20K 73 * CoreEMUL with Bonito System Controller is treated like a Core20K
74 * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC 74 * CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
75 */ 75 */
76#define MIPS_REVISION_CORID_CORE_EMUL_BON 0x63 76#define MIPS_REVISION_CORID_CORE_EMUL_BON -1
77#define MIPS_REVISION_CORID_CORE_EMUL_MSC 0x65 77#define MIPS_REVISION_CORID_CORE_EMUL_MSC -2
78 78
79#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) 79#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
80 80
81extern unsigned int mips_revision_corid; 81extern int mips_revision_corid;
82
83#define MIPS_REVISION_SCON_OTHER 0
84#define MIPS_REVISION_SCON_SOCITSC 1
85#define MIPS_REVISION_SCON_SOCITSCP 2
86
87/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
88#define MIPS_REVISION_SCON_UNKNOWN -1
89#define MIPS_REVISION_SCON_GT64120 -2
90#define MIPS_REVISION_SCON_BONITO -3
91#define MIPS_REVISION_SCON_BRTL -4
92#define MIPS_REVISION_SCON_SOCIT -5
93#define MIPS_REVISION_SCON_ROCIT -6
94
95#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
96
97extern int mips_revision_sconid;
82 98
83#ifdef CONFIG_PCI 99#ifdef CONFIG_PCI
84extern void mips_pcibios_init(void); 100extern void mips_pcibios_init(void);
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
index 8eaefb837b9d..e036b7dd6deb 100644
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ b/include/asm-mips/mips-boards/msc01_pci.h
@@ -208,6 +208,7 @@
208 * latter, they should be moved elsewhere. 208 * latter, they should be moved elsewhere.
209 */ 209 */
210#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000 210#define MIPS_MSC01_PCI_REG_BASE 0x1bd00000
211#define MIPS_SOCITSC_PCI_REG_BASE 0x1ff10000
211 212
212extern unsigned long _pcictrl_msc; 213extern unsigned long _pcictrl_msc;
213 214