[MIPS] Add support for MIPS CMP platform.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4 files changed, 121 insertions, 0 deletions

diff --git a/include/asm-mips/mips-boards/launch.h b/include/asm-mips/mips-boards/launch.h
new file mode 100644
index 000000000000..d8ae7f95a522
--- /dev/null
+++ b/include/asm-mips/mips-boards/launch.h
@@ -0,0 +1,35 @@
+/*
+ *
+ */
+
+#ifndef _ASSEMBLER_
+
+struct cpulaunch {
+    unsigned long       pc;
+    unsigned long       gp;
+    unsigned long       sp;
+    unsigned long       a0;
+    unsigned long       _pad[3]; /* pad to cache line size to avoid thrashing */
+    unsigned long       flags;
+};
+
+#else
+
+#define LOG2CPULAUNCH   5
+#define LAUNCH_PC       0
+#define LAUNCH_GP       4
+#define LAUNCH_SP       8
+#define LAUNCH_A0       12
+#define LAUNCH_FLAGS    28
+
+#endif
+
+#define LAUNCH_FREADY   1
+#define LAUNCH_FGO      2
+#define LAUNCH_FGONE    4
+
+#define CPULAUNCH       0x00000f00
+#define NCPULAUNCH      8
+
+/* Polling period in count cycles for secondary CPU's */
+#define LAUNCHPERIOD    10000
diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h
index 93bf4e51b8a4..c1891578fa65 100644
--- a/include/asm-mips/mips-boards/malta.h
+++ b/include/asm-mips/mips-boards/malta.h
@@ -52,6 +52,29 @@ static inline unsigned long get_msc_port_base(unsigned long reg)
 }
 
 /*
+ * GCMP Specific definitions
+ */
+#define GCMP_BASE_ADDR                  0x1fbf8000
+#define GCMP_ADDRSPACE_SZ               (256 * 1024)
+
+/*
+ * GIC Specific definitions
+ */
+#define GIC_BASE_ADDR                   0x1bdc0000
+#define GIC_ADDRSPACE_SZ                (128 * 1024)
+
+/*
+ * MSC01 BIU Specific definitions
+ * FIXME : These should be elsewhere ?
+ */
+#define MSC01_BIU_REG_BASE              0x1bc80000
+#define MSC01_BIU_ADDRSPACE_SZ          (256 * 1024)
+#define MSC01_SC_CFG_OFS                0x0110
+#define MSC01_SC_CFG_GICPRES_MSK        0x00000004
+#define MSC01_SC_CFG_GICPRES_SHF        2
+#define MSC01_SC_CFG_GICENA_SHF         3
+
+/*
  * Malta RTC-device indirect register access.
  */
 #define MALTA_RTC_ADR_REG       0x70
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
index 7461318f1cd1..cea872fc6f5c 100644
--- a/include/asm-mips/mips-boards/maltaint.h
+++ b/include/asm-mips/mips-boards/maltaint.h
@@ -39,7 +39,9 @@
 #define MIPSCPU_INT_I8259A      MIPSCPU_INT_MB0
 #define MIPSCPU_INT_MB1         3
 #define MIPSCPU_INT_SMI         MIPSCPU_INT_MB1
+#define MIPSCPU_INT_IPI0        MIPSCPU_INT_MB1 /* GIC IPI */
 #define MIPSCPU_INT_MB2         4
+#define MIPSCPU_INT_IPI1        MIPSCPU_INT_MB2 /* GIC IPI */
 #define MIPSCPU_INT_MB3         5
 #define MIPSCPU_INT_COREHI      MIPSCPU_INT_MB3
 #define MIPSCPU_INT_MB4         6
@@ -76,6 +78,31 @@
 #define MSC01E_INT_PERFCTR      10
 #define MSC01E_INT_CPUCTR       11
 
+/* GIC's Nomenclature for Core Interrupt Pins on the Malta */
+#define GIC_CPU_INT0            0 /* Core Interrupt 2   */
+#define GIC_CPU_INT1            1 /* .                  */
+#define GIC_CPU_INT2            2 /* .                  */
+#define GIC_CPU_INT3            3 /* .                  */
+#define GIC_CPU_INT4            4 /* .                  */
+#define GIC_CPU_INT5            5 /* Core Interrupt 5   */
+
+#define GIC_EXT_INTR(x)         x
+
+/* Dummy data */
+#define X                       0xdead
+
+/* External Interrupts used for IPI */
+#define GIC_IPI_EXT_INTR_RESCHED_VPE0   16
+#define GIC_IPI_EXT_INTR_CALLFNC_VPE0   17
+#define GIC_IPI_EXT_INTR_RESCHED_VPE1   18
+#define GIC_IPI_EXT_INTR_CALLFNC_VPE1   19
+#define GIC_IPI_EXT_INTR_RESCHED_VPE2   20
+#define GIC_IPI_EXT_INTR_CALLFNC_VPE2   21
+#define GIC_IPI_EXT_INTR_RESCHED_VPE3   22
+#define GIC_IPI_EXT_INTR_CALLFNC_VPE3   23
+
+#define MIPS_GIC_IRQ_BASE       (MIPS_CPU_IRQ_BASE + 8)
+
 #ifndef __ASSEMBLY__
 extern void maltaint_init(void);
 #endif
diff --git a/include/asm-mips/mips-boards/maltasmp.h b/include/asm-mips/mips-boards/maltasmp.h
new file mode 100644
index 000000000000..8d7e955d506e
--- /dev/null
+++ b/include/asm-mips/mips-boards/maltasmp.h
@@ -0,0 +1,36 @@
+/*
+ * There are several SMP models supported
+ * SMTC is mutually exclusive to other options (atm)
+ */
+#if defined(CONFIG_MIPS_MT_SMTC)
+#define malta_smtc      1
+#define malta_cmp       0
+#define malta_smvp      0
+#else
+#define malta_smtc      0
+#if defined(CONFIG_MIPS_CMP)
+extern int gcmp_present;
+#define malta_cmp       gcmp_present
+#else
+#define malta_cmp       0
+#endif
+/* FIXME: should become COMFIG_MIPS_MT_SMVP */
+#if defined(CONFIG_MIPS_MT_SMP)
+#define malta_smvp      1
+#else
+#define malta_smvp      0
+#endif
+#endif
+
+#include <asm/mipsregs.h>
+#include <asm/mipsmtregs.h>
+
+/* malta_smtc */
+#include <asm/smtc.h>
+#include <asm/smtc_ipi.h>
+
+/* malta_cmp */
+#include <asm/cmp.h>
+
+/* malta_smvp */
+#include <asm/smvp.h>