diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2005-09-30 08:59:37 -0400 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:32:30 -0400 |
commit | c78cbf49c4edf2f9ca9e56d4b87a5d6ef08b7fed (patch) | |
tree | 44bee3daac887df59c0d69658b19c21da4e1839f /include/asm-mips/mips-boards/simint.h | |
parent | b288f135872b651ebf6cd1565d0709a5e31997f7 (diff) |
Support for MIPSsim, the cycle accurate MIPS simulator.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mips-boards/simint.h')
-rw-r--r-- | include/asm-mips/mips-boards/simint.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h new file mode 100644 index 000000000000..4952e0b3bf11 --- /dev/null +++ b/include/asm-mips/mips-boards/simint.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can distribute it and/or modify it | ||
5 | * under the terms of the GNU General Public License (Version 2) as | ||
6 | * published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | ||
11 | * for more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License along | ||
14 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
15 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | ||
16 | */ | ||
17 | #ifndef _MIPS_SIMINT_H | ||
18 | #define _MIPS_SIMINT_H | ||
19 | |||
20 | |||
21 | #define SIM_INT_BASE 0 | ||
22 | #define MIPSCPU_INT_MB0 2 | ||
23 | #define MIPSCPU_INT_BASE 16 | ||
24 | #define MIPS_CPU_TIMER_IRQ 7 | ||
25 | |||
26 | |||
27 | #define MIPSCPU_INT_CPUCTR 7 | ||
28 | |||
29 | #define MSC01E_INT_BASE 64 | ||
30 | |||
31 | #define MIPSCPU_INT_CPUCTR 7 | ||
32 | #define MSC01E_INT_CPUCTR 11 | ||
33 | |||
34 | #endif | ||