diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-06-20 17:27:10 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-06-20 17:27:10 -0400 |
commit | 3b1d4ed5353af04d6aa20be2701727b9cdb2ac61 (patch) | |
tree | e4a3335c925abd933f1650e1ee4786e6bfad8f35 /include/asm-mips/mips-boards/maltaint.h | |
parent | 7c8545e98468c53809fc06788a3b9a34dff05240 (diff) |
[MIPS] Don't drag a platform specific header into generic arch code.
For some platforms it's definitions may conflict. So that's the one-liner.
The rest is 10 square kilometers of collateral damage fixup this include
used to paper over.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mips-boards/maltaint.h')
-rw-r--r-- | include/asm-mips/mips-boards/maltaint.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h index 9180d6466113..7461318f1cd1 100644 --- a/include/asm-mips/mips-boards/maltaint.h +++ b/include/asm-mips/mips-boards/maltaint.h | |||
@@ -32,11 +32,6 @@ | |||
32 | */ | 32 | */ |
33 | #define MALTA_INT_BASE 0 | 33 | #define MALTA_INT_BASE 0 |
34 | 34 | ||
35 | /* | ||
36 | * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode) | ||
37 | */ | ||
38 | #define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE | ||
39 | |||
40 | /* CPU interrupt offsets */ | 35 | /* CPU interrupt offsets */ |
41 | #define MIPSCPU_INT_SW0 0 | 36 | #define MIPSCPU_INT_SW0 0 |
42 | #define MIPSCPU_INT_SW1 1 | 37 | #define MIPSCPU_INT_SW1 1 |
@@ -49,7 +44,6 @@ | |||
49 | #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 | 44 | #define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3 |
50 | #define MIPSCPU_INT_MB4 6 | 45 | #define MIPSCPU_INT_MB4 6 |
51 | #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 | 46 | #define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4 |
52 | #define MIPSCPU_INT_CPUCTR 7 | ||
53 | 47 | ||
54 | /* | 48 | /* |
55 | * Interrupts 64..127 are used for Soc-it Classic interrupts | 49 | * Interrupts 64..127 are used for Soc-it Classic interrupts |