diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2005-09-30 08:59:37 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:32:30 -0400 |
| commit | c78cbf49c4edf2f9ca9e56d4b87a5d6ef08b7fed (patch) | |
| tree | 44bee3daac887df59c0d69658b19c21da4e1839f /include/asm-mips/mach-sim | |
| parent | b288f135872b651ebf6cd1565d0709a5e31997f7 (diff) | |
Support for MIPSsim, the cycle accurate MIPS simulator.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-sim')
| -rw-r--r-- | include/asm-mips/mach-sim/cpu-feature-overrides.h | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/include/asm-mips/mach-sim/cpu-feature-overrides.h b/include/asm-mips/mach-sim/cpu-feature-overrides.h new file mode 100644 index 000000000000..09457217a57d --- /dev/null +++ b/include/asm-mips/mach-sim/cpu-feature-overrides.h | |||
| @@ -0,0 +1,66 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2003, 2004 Chris Dearman | ||
| 7 | */ | ||
| 8 | #ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H | ||
| 9 | #define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H | ||
| 10 | |||
| 11 | #include <linux/config.h> | ||
| 12 | |||
| 13 | /* | ||
| 14 | * CPU feature overrides for MIPS boards | ||
| 15 | */ | ||
| 16 | #ifdef CONFIG_CPU_MIPS32 | ||
| 17 | #define cpu_has_tlb 1 | ||
| 18 | #define cpu_has_4kex 1 | ||
| 19 | #define cpu_has_4ktlb 1 | ||
| 20 | #define cpu_has_fpu 0 | ||
| 21 | /* #define cpu_has_32fpr ? */ | ||
| 22 | #define cpu_has_counter 1 | ||
| 23 | /* #define cpu_has_watch ? */ | ||
| 24 | #define cpu_has_divec 1 | ||
| 25 | #define cpu_has_vce 0 | ||
| 26 | /* #define cpu_has_cache_cdex_p ? */ | ||
| 27 | /* #define cpu_has_cache_cdex_s ? */ | ||
| 28 | /* #define cpu_has_prefetch ? */ | ||
| 29 | #define cpu_has_mcheck 1 | ||
| 30 | /* #define cpu_has_ejtag ? */ | ||
| 31 | #define cpu_has_llsc 1 | ||
| 32 | /* #define cpu_has_vtag_icache ? */ | ||
| 33 | /* #define cpu_has_dc_aliases ? */ | ||
| 34 | /* #define cpu_has_ic_fills_f_dc ? */ | ||
| 35 | #define cpu_has_nofpuex 0 | ||
| 36 | /* #define cpu_has_64bits ? */ | ||
| 37 | /* #define cpu_has_64bit_zero_reg ? */ | ||
| 38 | /* #define cpu_has_subset_pcaches ? */ | ||
| 39 | #endif | ||
| 40 | |||
| 41 | #ifdef CONFIG_CPU_MIPS64 | ||
| 42 | #define cpu_has_tlb 1 | ||
| 43 | #define cpu_has_4kex 1 | ||
| 44 | #define cpu_has_4ktlb 1 | ||
| 45 | /* #define cpu_has_fpu ? */ | ||
| 46 | /* #define cpu_has_32fpr ? */ | ||
| 47 | #define cpu_has_counter 1 | ||
| 48 | /* #define cpu_has_watch ? */ | ||
| 49 | #define cpu_has_divec 1 | ||
| 50 | #define cpu_has_vce 0 | ||
| 51 | /* #define cpu_has_cache_cdex_p ? */ | ||
| 52 | /* #define cpu_has_cache_cdex_s ? */ | ||
| 53 | /* #define cpu_has_prefetch ? */ | ||
| 54 | #define cpu_has_mcheck 1 | ||
| 55 | /* #define cpu_has_ejtag ? */ | ||
| 56 | #define cpu_has_llsc 1 | ||
| 57 | /* #define cpu_has_vtag_icache ? */ | ||
| 58 | /* #define cpu_has_dc_aliases ? */ | ||
| 59 | /* #define cpu_has_ic_fills_f_dc ? */ | ||
| 60 | #define cpu_has_nofpuex 0 | ||
| 61 | /* #define cpu_has_64bits ? */ | ||
| 62 | /* #define cpu_has_64bit_zero_reg ? */ | ||
| 63 | /* #define cpu_has_subset_pcaches ? */ | ||
| 64 | #endif | ||
| 65 | |||
| 66 | #endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ | ||