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authorDavid Woodhouse <David.Woodhouse@intel.com>2008-07-11 09:36:25 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2008-07-11 09:36:25 -0400
commita8931ef380c92d121ae74ecfb03b2d63f72eea6f (patch)
tree980fb6b019e11e6cb1ece55b7faff184721a8053 /include/asm-mips/mach-pb1x00
parent90574d0a4d4b73308ae54a2a57a4f3f1fa98e984 (diff)
parente5a5816f7875207cb0a0a7032e39a4686c5e10a4 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-mips/mach-pb1x00')
-rw-r--r--include/asm-mips/mach-pb1x00/pb1000.h189
-rw-r--r--include/asm-mips/mach-pb1x00/pb1100.h96
-rw-r--r--include/asm-mips/mach-pb1x00/pb1200.h93
-rw-r--r--include/asm-mips/mach-pb1x00/pb1500.h38
-rw-r--r--include/asm-mips/mach-pb1x00/pb1550.h51
5 files changed, 190 insertions, 277 deletions
diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h
index b52e0e7ee3fb..6d1ff9060e44 100644
--- a/include/asm-mips/mach-pb1x00/pb1000.h
+++ b/include/asm-mips/mach-pb1x00/pb1000.h
@@ -1,9 +1,8 @@
1/* 1/*
2 * Alchemy Semi PB1000 Referrence Board 2 * Alchemy Semi Pb1000 Referrence Board
3 * 3 *
4 * Copyright 2001 MontaVista Software Inc. 4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. 5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * ppopov@mvista.com or source@mvista.com
7 * 6 *
8 * ######################################################################## 7 * ########################################################################
9 * 8 *
@@ -28,145 +27,61 @@
28#define __ASM_PB1000_H 27#define __ASM_PB1000_H
29 28
30/* PCMCIA PB1000 specific defines */ 29/* PCMCIA PB1000 specific defines */
31#define PCMCIA_MAX_SOCK 1 30#define PCMCIA_MAX_SOCK 1
32#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 31#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
33 32
34#define PB1000_PCR 0xBE000000 33#define PB1000_PCR 0xBE000000
35# define PCR_SLOT_0_VPP0 (1<<0) 34# define PCR_SLOT_0_VPP0 (1 << 0)
36# define PCR_SLOT_0_VPP1 (1<<1) 35# define PCR_SLOT_0_VPP1 (1 << 1)
37# define PCR_SLOT_0_VCC0 (1<<2) 36# define PCR_SLOT_0_VCC0 (1 << 2)
38# define PCR_SLOT_0_VCC1 (1<<3) 37# define PCR_SLOT_0_VCC1 (1 << 3)
39# define PCR_SLOT_0_RST (1<<4) 38# define PCR_SLOT_0_RST (1 << 4)
40 39# define PCR_SLOT_1_VPP0 (1 << 8)
41# define PCR_SLOT_1_VPP0 (1<<8) 40# define PCR_SLOT_1_VPP1 (1 << 9)
42# define PCR_SLOT_1_VPP1 (1<<9) 41# define PCR_SLOT_1_VCC0 (1 << 10)
43# define PCR_SLOT_1_VCC0 (1<<10) 42# define PCR_SLOT_1_VCC1 (1 << 11)
44# define PCR_SLOT_1_VCC1 (1<<11) 43# define PCR_SLOT_1_RST (1 << 12)
45# define PCR_SLOT_1_RST (1<<12) 44
46 45#define PB1000_MDR 0xBE000004
47#define PB1000_MDR 0xBE000004 46# define MDR_PI (1 << 5) /* PCMCIA int latch */
48# define MDR_PI (1<<5) /* pcmcia int latch */ 47# define MDR_EPI (1 << 14) /* enable PCMCIA int */
49# define MDR_EPI (1<<14) /* enable pcmcia int */ 48# define MDR_CPI (1 << 15) /* clear PCMCIA int */
50# define MDR_CPI (1<<15) /* clear pcmcia int */ 49
51 50#define PB1000_ACR1 0xBE000008
52#define PB1000_ACR1 0xBE000008 51# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
53# define ACR1_SLOT_0_CD1 (1<<0) /* card detect 1 */ 52# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
54# define ACR1_SLOT_0_CD2 (1<<1) /* card detect 2 */ 53# define ACR1_SLOT_0_READY (1 << 2) /* ready */
55# define ACR1_SLOT_0_READY (1<<2) /* ready */ 54# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
56# define ACR1_SLOT_0_STATUS (1<<3) /* status change */ 55# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
57# define ACR1_SLOT_0_VS1 (1<<4) /* voltage sense 1 */ 56# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
58# define ACR1_SLOT_0_VS2 (1<<5) /* voltage sense 2 */ 57# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
59# define ACR1_SLOT_0_INPACK (1<<6) /* inpack pin status */ 58# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
60# define ACR1_SLOT_1_CD1 (1<<8) /* card detect 1 */ 59# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
61# define ACR1_SLOT_1_CD2 (1<<9) /* card detect 2 */ 60# define ACR1_SLOT_1_READY (1 << 10) /* ready */
62# define ACR1_SLOT_1_READY (1<<10) /* ready */ 61# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
63# define ACR1_SLOT_1_STATUS (1<<11) /* status change */ 62# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
64# define ACR1_SLOT_1_VS1 (1<<12) /* voltage sense 1 */ 63# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
65# define ACR1_SLOT_1_VS2 (1<<13) /* voltage sense 2 */ 64# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
66# define ACR1_SLOT_1_INPACK (1<<14) /* inpack pin status */ 65
67 66#define CPLD_AUX0 0xBE00000C
68#define CPLD_AUX0 0xBE00000C 67#define CPLD_AUX1 0xBE000010
69#define CPLD_AUX1 0xBE000010 68#define CPLD_AUX2 0xBE000014
70#define CPLD_AUX2 0xBE000014
71 69
72/* Voltage levels */ 70/* Voltage levels */
73 71
74/* VPPEN1 - VPPEN0 */ 72/* VPPEN1 - VPPEN0 */
75#define VPP_GND ((0<<1) | (0<<0)) 73#define VPP_GND ((0 << 1) | (0 << 0))
76#define VPP_5V ((1<<1) | (0<<0)) 74#define VPP_5V ((1 << 1) | (0 << 0))
77#define VPP_3V ((0<<1) | (1<<0)) 75#define VPP_3V ((0 << 1) | (1 << 0))
78#define VPP_12V ((0<<1) | (1<<0)) 76#define VPP_12V ((0 << 1) | (1 << 0))
79#define VPP_HIZ ((1<<1) | (1<<0)) 77#define VPP_HIZ ((1 << 1) | (1 << 0))
80 78
81/* VCCEN1 - VCCEN0 */ 79/* VCCEN1 - VCCEN0 */
82#define VCC_3V ((0<<1) | (1<<0)) 80#define VCC_3V ((0 << 1) | (1 << 0))
83#define VCC_5V ((1<<1) | (0<<0)) 81#define VCC_5V ((1 << 1) | (0 << 0))
84#define VCC_HIZ ((0<<1) | (0<<0)) 82#define VCC_HIZ ((0 << 1) | (0 << 0))
85 83
86/* VPP/VCC */ 84/* VPP/VCC */
87#define SET_VCC_VPP(VCC, VPP, SLOT)\ 85#define SET_VCC_VPP(VCC, VPP, SLOT) \
88 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 86 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
89
90
91/* PCI PB1000 specific defines */
92/* The reason these defines are here instead of au1000.h is because
93 * the Au1000 does not have a PCI bus controller so the PCI implementation
94 * on the some of the older Pb1000 boards was very board specific.
95 */
96#define PCI_CONFIG_BASE 0xBA020000 /* the only external slot */
97
98#define SDRAM_DEVID 0xBA010000
99#define SDRAM_CMD 0xBA010004
100#define SDRAM_CLASS 0xBA010008
101#define SDRAM_MISC 0xBA01000C
102#define SDRAM_MBAR 0xBA010010
103
104#define PCI_IO_DATA_PORT 0xBA800000
105
106#define PCI_IO_ADDR 0xBE00001C
107#define PCI_INT_ACK 0xBBC00000
108#define PCI_IO_READ 0xBBC00020
109#define PCI_IO_WRITE 0xBBC00030
110
111#define PCI_BRIDGE_CONFIG 0xBE000018
112
113#define PCI_IO_START 0x10000000
114#define PCI_IO_END 0x1000ffff
115#define PCI_MEM_START 0x18000000
116#define PCI_MEM_END 0x18ffffff
117
118#define PCI_FIRST_DEVFN 0
119#define PCI_LAST_DEVFN 1
120
121static inline u8 au_pci_io_readb(u32 addr)
122{
123 writel(addr, PCI_IO_ADDR);
124 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
125 return (readl(PCI_IO_DATA_PORT) & 0xff);
126}
127
128static inline u16 au_pci_io_readw(u32 addr)
129{
130 writel(addr, PCI_IO_ADDR);
131 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
132 return (readl(PCI_IO_DATA_PORT) & 0xffff);
133}
134
135static inline u32 au_pci_io_readl(u32 addr)
136{
137 writel(addr, PCI_IO_ADDR);
138 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG);
139 return readl(PCI_IO_DATA_PORT);
140}
141
142static inline void au_pci_io_writeb(u8 val, u32 addr)
143{
144 writel(addr, PCI_IO_ADDR);
145 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
146 writel(val, PCI_IO_DATA_PORT);
147}
148
149static inline void au_pci_io_writew(u16 val, u32 addr)
150{
151 writel(addr, PCI_IO_ADDR);
152 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
153 writel(val, PCI_IO_DATA_PORT);
154}
155
156static inline void au_pci_io_writel(u32 val, u32 addr)
157{
158 writel(addr, PCI_IO_ADDR);
159 writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG);
160 writel(val, PCI_IO_DATA_PORT);
161}
162
163static inline void set_sdram_extbyte(void)
164{
165 writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG);
166}
167
168static inline void set_slot_extbyte(void)
169{
170 writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
171}
172#endif /* __ASM_PB1000_H */ 87#endif /* __ASM_PB1000_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h
index 63aa3926b297..b1a60f1cbd02 100644
--- a/include/asm-mips/mach-pb1x00/pb1100.h
+++ b/include/asm-mips/mach-pb1x00/pb1100.h
@@ -1,9 +1,8 @@
1/* 1/*
2 * Alchemy Semi PB1100 Referrence Board 2 * Alchemy Semi Pb1100 Referrence Board
3 * 3 *
4 * Copyright 2001 MontaVista Software Inc. 4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. 5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * ppopov@mvista.com or source@mvista.com
7 * 6 *
8 * ######################################################################## 7 * ########################################################################
9 * 8 *
@@ -27,59 +26,60 @@
27#ifndef __ASM_PB1100_H 26#ifndef __ASM_PB1100_H
28#define __ASM_PB1100_H 27#define __ASM_PB1100_H
29 28
30#define PB1100_IDENT 0xAE000000 29#define PB1100_IDENT 0xAE000000
31#define BOARD_STATUS_REG 0xAE000004 30#define BOARD_STATUS_REG 0xAE000004
32# define PB1100_ROM_SEL (1<<15) 31# define PB1100_ROM_SEL (1 << 15)
33# define PB1100_ROM_SIZ (1<<14) 32# define PB1100_ROM_SIZ (1 << 14)
34# define PB1100_SWAP_BOOT (1<<13) 33# define PB1100_SWAP_BOOT (1 << 13)
35# define PB1100_FLASH_WP (1<<12) 34# define PB1100_FLASH_WP (1 << 12)
36# define PB1100_ROM_H_STS (1<<11) 35# define PB1100_ROM_H_STS (1 << 11)
37# define PB1100_ROM_L_STS (1<<10) 36# define PB1100_ROM_L_STS (1 << 10)
38# define PB1100_FLASH_H_STS (1<<9) 37# define PB1100_FLASH_H_STS (1 << 9)
39# define PB1100_FLASH_L_STS (1<<8) 38# define PB1100_FLASH_L_STS (1 << 8)
40# define PB1100_SRAM_SIZ (1<<7) 39# define PB1100_SRAM_SIZ (1 << 7)
41# define PB1100_TSC_BUSY (1<<6) 40# define PB1100_TSC_BUSY (1 << 6)
42# define PB1100_PCMCIA_VS_MASK (3<<4) 41# define PB1100_PCMCIA_VS_MASK (3 << 4)
43# define PB1100_RS232_CD (1<<3) 42# define PB1100_RS232_CD (1 << 3)
44# define PB1100_RS232_CTS (1<<2) 43# define PB1100_RS232_CTS (1 << 2)
45# define PB1100_RS232_DSR (1<<1) 44# define PB1100_RS232_DSR (1 << 1)
46# define PB1100_RS232_RI (1<<0) 45# define PB1100_RS232_RI (1 << 0)
47 46
48#define PB1100_IRDA_RS232 0xAE00000C 47#define PB1100_IRDA_RS232 0xAE00000C
49# define PB1100_IRDA_FULL (0<<14) /* full power */ 48# define PB1100_IRDA_FULL (0 << 14) /* full power */
50# define PB1100_IRDA_SHUTDOWN (1<<14) 49# define PB1100_IRDA_SHUTDOWN (1 << 14)
51# define PB1100_IRDA_TT (2<<14) /* 2/3 power */ 50# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */
52# define PB1100_IRDA_OT (3<<14) /* 1/3 power */ 51# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */
53# define PB1100_IRDA_FIR (1<<13) 52# define PB1100_IRDA_FIR (1 << 13)
54 53
55#define PCMCIA_BOARD_REG 0xAE000010 54#define PCMCIA_BOARD_REG 0xAE000010
56# define PB1100_SD_WP1_RO (1<<15) /* read only */ 55# define PB1100_SD_WP1_RO (1 << 15) /* read only */
57# define PB1100_SD_WP0_RO (1<<14) /* read only */ 56# define PB1100_SD_WP0_RO (1 << 14) /* read only */
58# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ 57# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */
59# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ 58# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */
60# define PB1100_SEL_SD_CONN1 (1<<9) 59# define PB1100_SEL_SD_CONN1 (1 << 9)
61# define PB1100_SEL_SD_CONN0 (1<<8) 60# define PB1100_SEL_SD_CONN0 (1 << 8)
62# define PC_DEASSERT_RST (1<<7) 61# define PC_DEASSERT_RST (1 << 7)
63# define PC_DRV_EN (1<<4) 62# define PC_DRV_EN (1 << 4)
64 63
65#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ 64#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
66 65
67#define PB1100_RST_VDDI 0xAE00001C 66#define PB1100_RST_VDDI 0xAE00001C
68# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ 67# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */
69# define PB1100_VDDI_MASK (0x1F) 68# define PB1100_VDDI_MASK 0x1F
70 69
71#define PB1100_LEDS 0xAE000018 70#define PB1100_LEDS 0xAE000018
72 71
73/* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED. 72/*
74 * 7:0 is the LED Display's decimal points. 73 * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
74 * 7:0 is the LED Display's decimal points.
75 */ 75 */
76#define PB1100_HEX_LED 0xAE000018 76#define PB1100_HEX_LED 0xAE000018
77 77
78/* PCMCIA PB1100 specific defines */ 78/* PCMCIA Pb1100 specific defines */
79#define PCMCIA_MAX_SOCK 0 79#define PCMCIA_MAX_SOCK 0
80#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 80#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
81 81
82/* VPP/VCC */ 82/* VPP/VCC */
83#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0)) 83#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
84 84
85#endif /* __ASM_PB1100_H */ 85#endif /* __ASM_PB1100_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
index e2c6bcac3b42..c8618df88cb5 100644
--- a/include/asm-mips/mach-pb1x00/pb1200.h
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * AMD Alchemy PB1200 Referrence Board 2 * AMD Alchemy Pb1200 Referrence Board
3 * Board Registers defines. 3 * Board Registers defines.
4 * 4 *
5 * ######################################################################## 5 * ########################################################################
@@ -27,21 +27,20 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 28#include <asm/mach-au1x00/au1xxx_psc.h>
29 29
30// This is defined in au1000.h with bogus value 30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31#undef AU1X00_EXTERNAL_INT 31#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
32 34
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 35/*
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 36 * SPI and SMB are muxed on the Pb1200 board.
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX 37 * Refer to board documentation.
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
37
38/* SPI and SMB are muxed on the Pb1200 board.
39 Refer to board documentation.
40 */ 38 */
41#define SPI_PSC_BASE PSC0_BASE_ADDR 39#define SPI_PSC_BASE PSC0_BASE_ADDR
42#define SMBUS_PSC_BASE PSC0_BASE_ADDR 40#define SMBUS_PSC_BASE PSC0_BASE_ADDR
43/* AC97 and I2S are muxed on the Pb1200 board. 41/*
44 Refer to board documentation. 42 * AC97 and I2S are muxed on the Pb1200 board.
43 * Refer to board documentation.
45 */ 44 */
46#define AC97_PSC_BASE PSC1_BASE_ADDR 45#define AC97_PSC_BASE PSC1_BASE_ADDR
47#define I2S_PSC_BASE PSC1_BASE_ADDR 46#define I2S_PSC_BASE PSC1_BASE_ADDR
@@ -102,10 +101,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
102#define BCSR_STATUS_SWAPBOOT 0x0040 101#define BCSR_STATUS_SWAPBOOT 0x0040
103#define BCSR_STATUS_FLASHBUSY 0x0100 102#define BCSR_STATUS_FLASHBUSY 0x0100
104#define BCSR_STATUS_IDECBLID 0x0200 103#define BCSR_STATUS_IDECBLID 0x0200
105#define BCSR_STATUS_SD0WP 0x0400 104#define BCSR_STATUS_SD0WP 0x0400
106#define BCSR_STATUS_SD1WP 0x0800 105#define BCSR_STATUS_SD1WP 0x0800
107#define BCSR_STATUS_U0RXD 0x1000 106#define BCSR_STATUS_U0RXD 0x1000
108#define BCSR_STATUS_U1RXD 0x2000 107#define BCSR_STATUS_U1RXD 0x2000
109 108
110#define BCSR_SWITCHES_OCTAL 0x00FF 109#define BCSR_SWITCHES_OCTAL 0x00FF
111#define BCSR_SWITCHES_DIP_1 0x0080 110#define BCSR_SWITCHES_DIP_1 0x0080
@@ -123,11 +122,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
123#define BCSR_RESETS_DC 0x0004 122#define BCSR_RESETS_DC 0x0004
124#define BCSR_RESETS_IDE 0x0008 123#define BCSR_RESETS_IDE 0x0008
125/* not resets but in the same register */ 124/* not resets but in the same register */
126#define BCSR_RESETS_WSCFSM 0x0800 125#define BCSR_RESETS_WSCFSM 0x0800
127#define BCSR_RESETS_PCS0MUX 0x1000 126#define BCSR_RESETS_PCS0MUX 0x1000
128#define BCSR_RESETS_PCS1MUX 0x2000 127#define BCSR_RESETS_PCS1MUX 0x2000
129#define BCSR_RESETS_SPISEL 0x4000 128#define BCSR_RESETS_SPISEL 0x4000
130#define BCSR_RESETS_SD1MUX 0x8000 129#define BCSR_RESETS_SD1MUX 0x8000
131 130
132#define BCSR_PCMCIA_PC0VPP 0x0003 131#define BCSR_PCMCIA_PC0VPP 0x0003
133#define BCSR_PCMCIA_PC0VCC 0x000C 132#define BCSR_PCMCIA_PC0VCC 0x000C
@@ -163,7 +162,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
163#define BCSR_INT_PC0STSCHG 0x0008 162#define BCSR_INT_PC0STSCHG 0x0008
164#define BCSR_INT_PC1 0x0010 163#define BCSR_INT_PC1 0x0010
165#define BCSR_INT_PC1STSCHG 0x0020 164#define BCSR_INT_PC1STSCHG 0x0020
166#define BCSR_INT_DC 0x0040 165#define BCSR_INT_DC 0x0040
167#define BCSR_INT_FLASHBUSY 0x0080 166#define BCSR_INT_FLASHBUSY 0x0080
168#define BCSR_INT_PC0INSERT 0x0100 167#define BCSR_INT_PC0INSERT 0x0100
169#define BCSR_INT_PC0EJECT 0x0200 168#define BCSR_INT_PC0EJECT 0x0200
@@ -174,14 +173,6 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
174#define BCSR_INT_SD1INSERT 0x4000 173#define BCSR_INT_SD1INSERT 0x4000
175#define BCSR_INT_SD1EJECT 0x8000 174#define BCSR_INT_SD1EJECT 0x8000
176 175
177/* PCMCIA Db1x00 specific defines */
178#define PCMCIA_MAX_SOCK 1
179#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
180
181/* VPP/VCC */
182#define SET_VCC_VPP(VCC, VPP, SLOT)\
183 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
184
185#define SMC91C111_PHYS_ADDR 0x0D000300 176#define SMC91C111_PHYS_ADDR 0x0D000300
186#define SMC91C111_INT PB1200_ETH_INT 177#define SMC91C111_INT PB1200_ETH_INT
187 178
@@ -192,18 +183,19 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
192#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 183#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
193#define IDE_RQSIZE 128 184#define IDE_RQSIZE 128
194 185
195#define NAND_PHYS_ADDR 0x1C000000 186#define NAND_PHYS_ADDR 0x1C000000
196 187
197/* Timing values as described in databook, * ns value stripped of 188/*
189 * Timing values as described in databook, * ns value stripped of
198 * lower 2 bits. 190 * lower 2 bits.
199 * These defines are here rather than an SOC1200 generic file because 191 * These defines are here rather than an Au1200 generic file because
200 * the parts chosen on another board may be different and may require 192 * the parts chosen on another board may be different and may require
201 * different timings. 193 * different timings.
202 */ 194 */
203#define NAND_T_H (18 >> 2) 195#define NAND_T_H (18 >> 2)
204#define NAND_T_PUL (30 >> 2) 196#define NAND_T_PUL (30 >> 2)
205#define NAND_T_SU (30 >> 2) 197#define NAND_T_SU (30 >> 2)
206#define NAND_T_WH (30 >> 2) 198#define NAND_T_WH (30 >> 2)
207 199
208/* Bitfield shift amounts */ 200/* Bitfield shift amounts */
209#define NAND_T_H_SHIFT 0 201#define NAND_T_H_SHIFT 0
@@ -211,11 +203,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
211#define NAND_T_SU_SHIFT 8 203#define NAND_T_SU_SHIFT 8
212#define NAND_T_WH_SHIFT 12 204#define NAND_T_WH_SHIFT 12
213 205
214#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 206#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
215 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 207 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
216 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 208 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
217 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 209 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
218
219 210
220/* 211/*
221 * External Interrupts for Pb1200 as of 8/6/2004. 212 * External Interrupts for Pb1200 as of 8/6/2004.
@@ -248,13 +239,21 @@ enum external_pb1200_ints {
248 PB1200_INT_END = PB1200_INT_BEGIN + 15 239 PB1200_INT_END = PB1200_INT_BEGIN + 15
249}; 240};
250 241
251/* For drivers/pcmcia/au1000_db1x00.c */ 242/*
252#define BOARD_PC0_INT PB1200_PC0_INT 243 * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
253#define BOARD_PC1_INT PB1200_PC1_INT 244 */
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) 245#define PCMCIA_MAX_SOCK 1
246#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
255 247
256/* Nand chip select */ 248/* VPP/VCC */
249#define SET_VCC_VPP(VCC, VPP, SLOT) \
250 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
251
252#define BOARD_PC0_INT PB1200_PC0_INT
253#define BOARD_PC1_INT PB1200_PC1_INT
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
255
256/* NAND chip select */
257#define NAND_CS 1 257#define NAND_CS 1
258 258
259#endif /* __ASM_PB1200_H */ 259#endif /* __ASM_PB1200_H */
260
diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h
index ff6d40c87a25..da51a2eb7b82 100644
--- a/include/asm-mips/mach-pb1x00/pb1500.h
+++ b/include/asm-mips/mach-pb1x00/pb1500.h
@@ -1,9 +1,8 @@
1/* 1/*
2 * Alchemy Semi PB1500 Referrence Board 2 * Alchemy Semi Pb1500 Referrence Board
3 * 3 *
4 * Copyright 2001 MontaVista Software Inc. 4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. 5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * ppopov@mvista.com or source@mvista.com
7 * 6 *
8 * ######################################################################## 7 * ########################################################################
9 * 8 *
@@ -27,25 +26,24 @@
27#ifndef __ASM_PB1500_H 26#ifndef __ASM_PB1500_H
28#define __ASM_PB1500_H 27#define __ASM_PB1500_H
29 28
29#define IDENT_BOARD_REG 0xAE000000
30#define BOARD_STATUS_REG 0xAE000004
31#define PCI_BOARD_REG 0xAE000010
32#define PCMCIA_BOARD_REG 0xAE000010
33# define PC_DEASSERT_RST 0x80
34# define PC_DRV_EN 0x10
35#define PB1500_G_CONTROL 0xAE000014
36#define PB1500_RST_VDDI 0xAE00001C
37#define PB1500_LEDS 0xAE000018
30 38
31#define IDENT_BOARD_REG 0xAE000000 39#define PB1500_HEX_LED 0xAF000004
32#define BOARD_STATUS_REG 0xAE000004 40#define PB1500_HEX_LED_BLANK 0xAF000008
33#define PCI_BOARD_REG 0xAE000010
34#define PCMCIA_BOARD_REG 0xAE000010
35 #define PC_DEASSERT_RST 0x80
36 #define PC_DRV_EN 0x10
37#define PB1500_G_CONTROL 0xAE000014
38#define PB1500_RST_VDDI 0xAE00001C
39#define PB1500_LEDS 0xAE000018
40 41
41#define PB1500_HEX_LED 0xAF000004 42/* PCMCIA Pb1500 specific defines */
42#define PB1500_HEX_LED_BLANK 0xAF000008 43#define PCMCIA_MAX_SOCK 0
43 44#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
44/* PCMCIA PB1500 specific defines */
45#define PCMCIA_MAX_SOCK 0
46#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
47 45
48/* VPP/VCC */ 46/* VPP/VCC */
49#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0)) 47#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
50 48
51#endif /* __ASM_PB1500_H */ 49#endif /* __ASM_PB1500_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h
index c2ab0e2df4ae..6704a11497db 100644
--- a/include/asm-mips/mach-pb1x00/pb1550.h
+++ b/include/asm-mips/mach-pb1x00/pb1550.h
@@ -30,15 +30,15 @@
30#include <linux/types.h> 30#include <linux/types.h>
31#include <asm/mach-au1x00/au1xxx_psc.h> 31#include <asm/mach-au1x00/au1xxx_psc.h>
32 32
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX 35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX 36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
37 37
38#define SPI_PSC_BASE PSC0_BASE_ADDR 38#define SPI_PSC_BASE PSC0_BASE_ADDR
39#define AC97_PSC_BASE PSC1_BASE_ADDR 39#define AC97_PSC_BASE PSC1_BASE_ADDR
40#define SMBUS_PSC_BASE PSC2_BASE_ADDR 40#define SMBUS_PSC_BASE PSC2_BASE_ADDR
41#define I2S_PSC_BASE PSC3_BASE_ADDR 41#define I2S_PSC_BASE PSC3_BASE_ADDR
42 42
43#define BCSR_PHYS_ADDR 0xAF000000 43#define BCSR_PHYS_ADDR 0xAF000000
44 44
@@ -129,12 +129,12 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
129#define BCSR_SYSTEM_POWEROFF 0x4000 129#define BCSR_SYSTEM_POWEROFF 0x4000
130#define BCSR_SYSTEM_RESET 0x8000 130#define BCSR_SYSTEM_RESET 0x8000
131 131
132#define PCMCIA_MAX_SOCK 1 132#define PCMCIA_MAX_SOCK 1
133#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 133#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
134 134
135/* VPP/VCC */ 135/* VPP/VCC */
136#define SET_VCC_VPP(VCC, VPP, SLOT)\ 136#define SET_VCC_VPP(VCC, VPP, SLOT) \
137 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 137 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
138 138
139#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) 139#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
140#define PB1550_BOTH_BANKS 140#define PB1550_BOTH_BANKS
@@ -144,16 +144,17 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
144#define PB1550_USER_ONLY 144#define PB1550_USER_ONLY
145#endif 145#endif
146 146
147/* Timing values as described in databook, * ns value stripped of 147/*
148 * Timing values as described in databook, * ns value stripped of
148 * lower 2 bits. 149 * lower 2 bits.
149 * These defines are here rather than an SOC1550 generic file because 150 * These defines are here rather than an SOC1550 generic file because
150 * the parts chosen on another board may be different and may require 151 * the parts chosen on another board may be different and may require
151 * different timings. 152 * different timings.
152 */ 153 */
153#define NAND_T_H (18 >> 2) 154#define NAND_T_H (18 >> 2)
154#define NAND_T_PUL (30 >> 2) 155#define NAND_T_PUL (30 >> 2)
155#define NAND_T_SU (30 >> 2) 156#define NAND_T_SU (30 >> 2)
156#define NAND_T_WH (30 >> 2) 157#define NAND_T_WH (30 >> 2)
157 158
158/* Bitfield shift amounts */ 159/* Bitfield shift amounts */
159#define NAND_T_H_SHIFT 0 160#define NAND_T_H_SHIFT 0
@@ -161,16 +162,16 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
161#define NAND_T_SU_SHIFT 8 162#define NAND_T_SU_SHIFT 8
162#define NAND_T_WH_SHIFT 12 163#define NAND_T_WH_SHIFT 12
163 164
164#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 165#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
165 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 166 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
166 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 167 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
167 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 168 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
168 169
169#define NAND_CS 1 170#define NAND_CS 1
170 171
171/* should be done by yamon */ 172/* Should be done by YAMON */
172#define NAND_STCFG 0x00400005 /* 8-bit NAND */ 173#define NAND_STCFG 0x00400005 /* 8-bit NAND */
173#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */ 174#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
174#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */ 175#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
175 176
176#endif /* __ASM_PB1550_H */ 177#endif /* __ASM_PB1550_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 12:34:28 -0500