aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips/mach-pb1x00
diff options
context:
space:
mode:
authorSergei Shtylyov <sshtylyov@ru.mvista.com>2008-04-30 15:29:04 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-05-12 11:46:55 -0400
commitc3d1d5c8c10c937c65186f6dac75e2fb4675ef07 (patch)
tree7068d6740a59499be13961643c971a52fe198c7f /include/asm-mips/mach-pb1x00
parent6afabe6c9335c0534224b53c3db4b091621af2dd (diff)
[MIPS] Pb1200/DBAu1200 code style cleanup
Fix several errors and warnings given by checkpatch.pl: - use of C99 // comments; - initialization of a 'static' variable to 0; - space after opening and before closing parentheses; - missing space between 'for' and opening parenthesis; - macros with complex values not enclosed in parentheses; - printk() without KERN_* facility level; - unnecessary braces for single-statement block; - using simple_strtol() where strict_strtol() could be used; - line over 80 characters. In addition to these changes, also do the following: - mention DBAu1200 board in the Makefile; - replace the group of #include/#ifdef directives by a single #include <au1xxx.h> since this header contains the needed stuff; - properly indent the blocks; - insert spaces between operator and its operands, remove excess spaces there; - remove needless parentheses and add some for clarity; - replace numeric literals/expressions with the matching macros; - remove space after the type cast's closing parenthesis; - reduce pb1200_setup_cascade() to the single 'return' statement; - reduce the number of printed empty lines in the so-called CPLD workaround; - remove #undef AU1X00_EXTERNAL_INT since that macro is not defined anywhere; - replace spaces after the macro name with tabs in the #define directives; - remove excess tabs after the macro name in the #define directives; - fix typo in the BCSR_RESETS_PWMR1mUX macro's name; - group all Pb1200 PCMCIA definitions together; - put the function's result type and name/parameters on the same line; - insert missing and remove excess new lines; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first line and/or adding space/asterisk on their left side; - fix typos/errors, capitalize acronyms, etc. in the comments; - combine some comments; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-pb1x00')
-rw-r--r--include/asm-mips/mach-pb1x00/pb1200.h93
1 files changed, 46 insertions, 47 deletions
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
index e2c6bcac3b42..c8618df88cb5 100644
--- a/include/asm-mips/mach-pb1x00/pb1200.h
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * AMD Alchemy PB1200 Referrence Board 2 * AMD Alchemy Pb1200 Referrence Board
3 * Board Registers defines. 3 * Board Registers defines.
4 * 4 *
5 * ######################################################################## 5 * ########################################################################
@@ -27,21 +27,20 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 28#include <asm/mach-au1x00/au1xxx_psc.h>
29 29
30// This is defined in au1000.h with bogus value 30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31#undef AU1X00_EXTERNAL_INT 31#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
32 34
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 35/*
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 36 * SPI and SMB are muxed on the Pb1200 board.
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX 37 * Refer to board documentation.
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
37
38/* SPI and SMB are muxed on the Pb1200 board.
39 Refer to board documentation.
40 */ 38 */
41#define SPI_PSC_BASE PSC0_BASE_ADDR 39#define SPI_PSC_BASE PSC0_BASE_ADDR
42#define SMBUS_PSC_BASE PSC0_BASE_ADDR 40#define SMBUS_PSC_BASE PSC0_BASE_ADDR
43/* AC97 and I2S are muxed on the Pb1200 board. 41/*
44 Refer to board documentation. 42 * AC97 and I2S are muxed on the Pb1200 board.
43 * Refer to board documentation.
45 */ 44 */
46#define AC97_PSC_BASE PSC1_BASE_ADDR 45#define AC97_PSC_BASE PSC1_BASE_ADDR
47#define I2S_PSC_BASE PSC1_BASE_ADDR 46#define I2S_PSC_BASE PSC1_BASE_ADDR
@@ -102,10 +101,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
102#define BCSR_STATUS_SWAPBOOT 0x0040 101#define BCSR_STATUS_SWAPBOOT 0x0040
103#define BCSR_STATUS_FLASHBUSY 0x0100 102#define BCSR_STATUS_FLASHBUSY 0x0100
104#define BCSR_STATUS_IDECBLID 0x0200 103#define BCSR_STATUS_IDECBLID 0x0200
105#define BCSR_STATUS_SD0WP 0x0400 104#define BCSR_STATUS_SD0WP 0x0400
106#define BCSR_STATUS_SD1WP 0x0800 105#define BCSR_STATUS_SD1WP 0x0800
107#define BCSR_STATUS_U0RXD 0x1000 106#define BCSR_STATUS_U0RXD 0x1000
108#define BCSR_STATUS_U1RXD 0x2000 107#define BCSR_STATUS_U1RXD 0x2000
109 108
110#define BCSR_SWITCHES_OCTAL 0x00FF 109#define BCSR_SWITCHES_OCTAL 0x00FF
111#define BCSR_SWITCHES_DIP_1 0x0080 110#define BCSR_SWITCHES_DIP_1 0x0080
@@ -123,11 +122,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
123#define BCSR_RESETS_DC 0x0004 122#define BCSR_RESETS_DC 0x0004
124#define BCSR_RESETS_IDE 0x0008 123#define BCSR_RESETS_IDE 0x0008
125/* not resets but in the same register */ 124/* not resets but in the same register */
126#define BCSR_RESETS_WSCFSM 0x0800 125#define BCSR_RESETS_WSCFSM 0x0800
127#define BCSR_RESETS_PCS0MUX 0x1000 126#define BCSR_RESETS_PCS0MUX 0x1000
128#define BCSR_RESETS_PCS1MUX 0x2000 127#define BCSR_RESETS_PCS1MUX 0x2000
129#define BCSR_RESETS_SPISEL 0x4000 128#define BCSR_RESETS_SPISEL 0x4000
130#define BCSR_RESETS_SD1MUX 0x8000 129#define BCSR_RESETS_SD1MUX 0x8000
131 130
132#define BCSR_PCMCIA_PC0VPP 0x0003 131#define BCSR_PCMCIA_PC0VPP 0x0003
133#define BCSR_PCMCIA_PC0VCC 0x000C 132#define BCSR_PCMCIA_PC0VCC 0x000C
@@ -163,7 +162,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
163#define BCSR_INT_PC0STSCHG 0x0008 162#define BCSR_INT_PC0STSCHG 0x0008
164#define BCSR_INT_PC1 0x0010 163#define BCSR_INT_PC1 0x0010
165#define BCSR_INT_PC1STSCHG 0x0020 164#define BCSR_INT_PC1STSCHG 0x0020
166#define BCSR_INT_DC 0x0040 165#define BCSR_INT_DC 0x0040
167#define BCSR_INT_FLASHBUSY 0x0080 166#define BCSR_INT_FLASHBUSY 0x0080
168#define BCSR_INT_PC0INSERT 0x0100 167#define BCSR_INT_PC0INSERT 0x0100
169#define BCSR_INT_PC0EJECT 0x0200 168#define BCSR_INT_PC0EJECT 0x0200
@@ -174,14 +173,6 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
174#define BCSR_INT_SD1INSERT 0x4000 173#define BCSR_INT_SD1INSERT 0x4000
175#define BCSR_INT_SD1EJECT 0x8000 174#define BCSR_INT_SD1EJECT 0x8000
176 175
177/* PCMCIA Db1x00 specific defines */
178#define PCMCIA_MAX_SOCK 1
179#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
180
181/* VPP/VCC */
182#define SET_VCC_VPP(VCC, VPP, SLOT)\
183 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
184
185#define SMC91C111_PHYS_ADDR 0x0D000300 176#define SMC91C111_PHYS_ADDR 0x0D000300
186#define SMC91C111_INT PB1200_ETH_INT 177#define SMC91C111_INT PB1200_ETH_INT
187 178
@@ -192,18 +183,19 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
192#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 183#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
193#define IDE_RQSIZE 128 184#define IDE_RQSIZE 128
194 185
195#define NAND_PHYS_ADDR 0x1C000000 186#define NAND_PHYS_ADDR 0x1C000000
196 187
197/* Timing values as described in databook, * ns value stripped of 188/*
189 * Timing values as described in databook, * ns value stripped of
198 * lower 2 bits. 190 * lower 2 bits.
199 * These defines are here rather than an SOC1200 generic file because 191 * These defines are here rather than an Au1200 generic file because
200 * the parts chosen on another board may be different and may require 192 * the parts chosen on another board may be different and may require
201 * different timings. 193 * different timings.
202 */ 194 */
203#define NAND_T_H (18 >> 2) 195#define NAND_T_H (18 >> 2)
204#define NAND_T_PUL (30 >> 2) 196#define NAND_T_PUL (30 >> 2)
205#define NAND_T_SU (30 >> 2) 197#define NAND_T_SU (30 >> 2)
206#define NAND_T_WH (30 >> 2) 198#define NAND_T_WH (30 >> 2)
207 199
208/* Bitfield shift amounts */ 200/* Bitfield shift amounts */
209#define NAND_T_H_SHIFT 0 201#define NAND_T_H_SHIFT 0
@@ -211,11 +203,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
211#define NAND_T_SU_SHIFT 8 203#define NAND_T_SU_SHIFT 8
212#define NAND_T_WH_SHIFT 12 204#define NAND_T_WH_SHIFT 12
213 205
214#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \ 206#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
215 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \ 207 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
216 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 208 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
217 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 209 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
218
219 210
220/* 211/*
221 * External Interrupts for Pb1200 as of 8/6/2004. 212 * External Interrupts for Pb1200 as of 8/6/2004.
@@ -248,13 +239,21 @@ enum external_pb1200_ints {
248 PB1200_INT_END = PB1200_INT_BEGIN + 15 239 PB1200_INT_END = PB1200_INT_BEGIN + 15
249}; 240};
250 241
251/* For drivers/pcmcia/au1000_db1x00.c */ 242/*
252#define BOARD_PC0_INT PB1200_PC0_INT 243 * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
253#define BOARD_PC1_INT PB1200_PC1_INT 244 */
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) 245#define PCMCIA_MAX_SOCK 1
246#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
255 247
256/* Nand chip select */ 248/* VPP/VCC */
249#define SET_VCC_VPP(VCC, VPP, SLOT) \
250 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
251
252#define BOARD_PC0_INT PB1200_PC0_INT
253#define BOARD_PC1_INT PB1200_PC1_INT
254#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
255
256/* NAND chip select */
257#define NAND_CS 1 257#define NAND_CS 1
258 258
259#endif /* __ASM_PB1200_H */ 259#endif /* __ASM_PB1200_H */
260