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authorLen Brown <len.brown@intel.com>2005-12-06 17:31:30 -0500
committerLen Brown <len.brown@intel.com>2005-12-06 17:31:30 -0500
commit3d5271f9883cba7b54762bc4fe027d4172f06db7 (patch)
treeab8a881a14478598a0c8bda0d26c62cdccfffd6d /include/asm-mips/mach-pb1x00/pb1550.h
parent378b2556f4e09fa6f87ff0cb5c4395ff28257d02 (diff)
parent9115a6c787596e687df03010d97fccc5e0762506 (diff)
Pull release into acpica branch
Diffstat (limited to 'include/asm-mips/mach-pb1x00/pb1550.h')
-rw-r--r--include/asm-mips/mach-pb1x00/pb1550.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h
index 431d6088ea96..9578ead11e8a 100644
--- a/include/asm-mips/mach-pb1x00/pb1550.h
+++ b/include/asm-mips/mach-pb1x00/pb1550.h
@@ -166,4 +166,11 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
166 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \ 166 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
167 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT) 167 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
168 168
169#define NAND_CS 1
170
171/* should be done by yamon */
172#define NAND_STCFG 0x00400005 /* 8-bit NAND */
173#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
174#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
175
169#endif /* __ASM_PB1550_H */ 176#endif /* __ASM_PB1550_H */