diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-07-10 12:32:56 -0400 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2007-07-10 12:32:56 -0400 |
commit | f6e2373ad6148476464fc7bb2610c6450c18cd2a (patch) | |
tree | f73cb9a4d26b30b2cbf8530047c3825809867be5 /include/asm-mips/mach-mipssim | |
parent | 24e9d0b96dac5503c0b6f034d553030c604228a7 (diff) |
[MIPS] MIPSsim: Move code away from the other MIPS Inc. BSP code.
It shares no code at all. While at it also fix up the beginning bitrot.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-mipssim')
-rw-r--r-- | include/asm-mips/mach-mipssim/cpu-feature-overrides.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/include/asm-mips/mach-mipssim/cpu-feature-overrides.h b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h new file mode 100644 index 000000000000..779b02205737 --- /dev/null +++ b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2003, 2004 Chris Dearman | ||
7 | */ | ||
8 | #ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H | ||
9 | #define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H | ||
10 | |||
11 | |||
12 | /* | ||
13 | * CPU feature overrides for MIPS boards | ||
14 | */ | ||
15 | #ifdef CONFIG_CPU_MIPS32 | ||
16 | #define cpu_has_tlb 1 | ||
17 | #define cpu_has_4kex 1 | ||
18 | #define cpu_has_4k_cache 1 | ||
19 | #define cpu_has_fpu 0 | ||
20 | /* #define cpu_has_32fpr ? */ | ||
21 | #define cpu_has_counter 1 | ||
22 | /* #define cpu_has_watch ? */ | ||
23 | #define cpu_has_divec 1 | ||
24 | #define cpu_has_vce 0 | ||
25 | /* #define cpu_has_cache_cdex_p ? */ | ||
26 | /* #define cpu_has_cache_cdex_s ? */ | ||
27 | /* #define cpu_has_prefetch ? */ | ||
28 | #define cpu_has_mcheck 1 | ||
29 | /* #define cpu_has_ejtag ? */ | ||
30 | #define cpu_has_llsc 1 | ||
31 | /* #define cpu_has_vtag_icache ? */ | ||
32 | /* #define cpu_has_dc_aliases ? */ | ||
33 | /* #define cpu_has_ic_fills_f_dc ? */ | ||
34 | #define cpu_has_nofpuex 0 | ||
35 | /* #define cpu_has_64bits ? */ | ||
36 | /* #define cpu_has_64bit_zero_reg ? */ | ||
37 | /* #define cpu_has_inclusive_pcaches ? */ | ||
38 | #endif | ||
39 | |||
40 | #ifdef CONFIG_CPU_MIPS64 | ||
41 | #define cpu_has_tlb 1 | ||
42 | #define cpu_has_4kex 1 | ||
43 | #define cpu_has_4k_cache 1 | ||
44 | /* #define cpu_has_fpu ? */ | ||
45 | /* #define cpu_has_32fpr ? */ | ||
46 | #define cpu_has_counter 1 | ||
47 | /* #define cpu_has_watch ? */ | ||
48 | #define cpu_has_divec 1 | ||
49 | #define cpu_has_vce 0 | ||
50 | /* #define cpu_has_cache_cdex_p ? */ | ||
51 | /* #define cpu_has_cache_cdex_s ? */ | ||
52 | /* #define cpu_has_prefetch ? */ | ||
53 | #define cpu_has_mcheck 1 | ||
54 | /* #define cpu_has_ejtag ? */ | ||
55 | #define cpu_has_llsc 1 | ||
56 | /* #define cpu_has_vtag_icache ? */ | ||
57 | /* #define cpu_has_dc_aliases ? */ | ||
58 | /* #define cpu_has_ic_fills_f_dc ? */ | ||
59 | #define cpu_has_nofpuex 0 | ||
60 | /* #define cpu_has_64bits ? */ | ||
61 | /* #define cpu_has_64bit_zero_reg ? */ | ||
62 | /* #define cpu_has_inclusive_pcaches ? */ | ||
63 | #endif | ||
64 | |||
65 | #endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ | ||