diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2008-07-15 13:44:34 -0400 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2008-07-15 13:44:34 -0400 |
commit | 315806cb19f9d375dccbc2d60fa14e16afdcd5ac (patch) | |
tree | effe89f2f8d49bf62018ad5717a0d7c8c5725277 /include/asm-mips/mach-malta/cpu-feature-overrides.h | |
parent | eda49eeebf263f3a34f6968959fc2e4825b42beb (diff) |
[MIPS] Malta: Cleanup organization of code into directories.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-malta/cpu-feature-overrides.h')
-rw-r--r-- | include/asm-mips/mach-malta/cpu-feature-overrides.h | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/include/asm-mips/mach-malta/cpu-feature-overrides.h b/include/asm-mips/mach-malta/cpu-feature-overrides.h new file mode 100644 index 000000000000..7f3e3f9bd23a --- /dev/null +++ b/include/asm-mips/mach-malta/cpu-feature-overrides.h | |||
@@ -0,0 +1,72 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2003, 2004 Chris Dearman | ||
7 | * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) | ||
8 | */ | ||
9 | #ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H | ||
10 | #define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H | ||
11 | |||
12 | |||
13 | /* | ||
14 | * CPU feature overrides for MIPS boards | ||
15 | */ | ||
16 | #ifdef CONFIG_CPU_MIPS32 | ||
17 | #define cpu_has_tlb 1 | ||
18 | #define cpu_has_4kex 1 | ||
19 | #define cpu_has_4k_cache 1 | ||
20 | /* #define cpu_has_fpu ? */ | ||
21 | /* #define cpu_has_32fpr ? */ | ||
22 | #define cpu_has_counter 1 | ||
23 | /* #define cpu_has_watch ? */ | ||
24 | #define cpu_has_divec 1 | ||
25 | #define cpu_has_vce 0 | ||
26 | /* #define cpu_has_cache_cdex_p ? */ | ||
27 | /* #define cpu_has_cache_cdex_s ? */ | ||
28 | /* #define cpu_has_prefetch ? */ | ||
29 | #define cpu_has_mcheck 1 | ||
30 | /* #define cpu_has_ejtag ? */ | ||
31 | #ifdef CONFIG_CPU_HAS_LLSC | ||
32 | #define cpu_has_llsc 1 | ||
33 | #else | ||
34 | #define cpu_has_llsc 0 | ||
35 | #endif | ||
36 | /* #define cpu_has_vtag_icache ? */ | ||
37 | /* #define cpu_has_dc_aliases ? */ | ||
38 | /* #define cpu_has_ic_fills_f_dc ? */ | ||
39 | #define cpu_has_nofpuex 0 | ||
40 | /* #define cpu_has_64bits ? */ | ||
41 | /* #define cpu_has_64bit_zero_reg ? */ | ||
42 | /* #define cpu_has_inclusive_pcaches ? */ | ||
43 | #define cpu_icache_snoops_remote_store 1 | ||
44 | #endif | ||
45 | |||
46 | #ifdef CONFIG_CPU_MIPS64 | ||
47 | #define cpu_has_tlb 1 | ||
48 | #define cpu_has_4kex 1 | ||
49 | #define cpu_has_4k_cache 1 | ||
50 | /* #define cpu_has_fpu ? */ | ||
51 | /* #define cpu_has_32fpr ? */ | ||
52 | #define cpu_has_counter 1 | ||
53 | /* #define cpu_has_watch ? */ | ||
54 | #define cpu_has_divec 1 | ||
55 | #define cpu_has_vce 0 | ||
56 | /* #define cpu_has_cache_cdex_p ? */ | ||
57 | /* #define cpu_has_cache_cdex_s ? */ | ||
58 | /* #define cpu_has_prefetch ? */ | ||
59 | #define cpu_has_mcheck 1 | ||
60 | /* #define cpu_has_ejtag ? */ | ||
61 | #define cpu_has_llsc 1 | ||
62 | /* #define cpu_has_vtag_icache ? */ | ||
63 | /* #define cpu_has_dc_aliases ? */ | ||
64 | /* #define cpu_has_ic_fills_f_dc ? */ | ||
65 | #define cpu_has_nofpuex 0 | ||
66 | /* #define cpu_has_64bits ? */ | ||
67 | /* #define cpu_has_64bit_zero_reg ? */ | ||
68 | /* #define cpu_has_inclusive_pcaches ? */ | ||
69 | #define cpu_icache_snoops_remote_store 1 | ||
70 | #endif | ||
71 | |||
72 | #endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */ | ||