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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2008-04-30 15:29:04 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-05-12 11:46:55 -0400
commitc3d1d5c8c10c937c65186f6dac75e2fb4675ef07 (patch)
tree7068d6740a59499be13961643c971a52fe198c7f /include/asm-mips/mach-db1x00
parent6afabe6c9335c0534224b53c3db4b091621af2dd (diff)
[MIPS] Pb1200/DBAu1200 code style cleanup
Fix several errors and warnings given by checkpatch.pl: - use of C99 // comments; - initialization of a 'static' variable to 0; - space after opening and before closing parentheses; - missing space between 'for' and opening parenthesis; - macros with complex values not enclosed in parentheses; - printk() without KERN_* facility level; - unnecessary braces for single-statement block; - using simple_strtol() where strict_strtol() could be used; - line over 80 characters. In addition to these changes, also do the following: - mention DBAu1200 board in the Makefile; - replace the group of #include/#ifdef directives by a single #include <au1xxx.h> since this header contains the needed stuff; - properly indent the blocks; - insert spaces between operator and its operands, remove excess spaces there; - remove needless parentheses and add some for clarity; - replace numeric literals/expressions with the matching macros; - remove space after the type cast's closing parenthesis; - reduce pb1200_setup_cascade() to the single 'return' statement; - reduce the number of printed empty lines in the so-called CPLD workaround; - remove #undef AU1X00_EXTERNAL_INT since that macro is not defined anywhere; - replace spaces after the macro name with tabs in the #define directives; - remove excess tabs after the macro name in the #define directives; - fix typo in the BCSR_RESETS_PWMR1mUX macro's name; - group all Pb1200 PCMCIA definitions together; - put the function's result type and name/parameters on the same line; - insert missing and remove excess new lines; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first line and/or adding space/asterisk on their left side; - fix typos/errors, capitalize acronyms, etc. in the comments; - combine some comments; - update MontaVista copyright; - remove Pete Popov's old email address... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-db1x00')
-rw-r--r--include/asm-mips/mach-db1x00/db1200.h73
1 files changed, 35 insertions, 38 deletions
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
index eedd048a7261..27f26102b1bb 100644
--- a/include/asm-mips/mach-db1x00/db1200.h
+++ b/include/asm-mips/mach-db1x00/db1200.h
@@ -1,6 +1,6 @@
1/* 1/*
2 * AMD Alchemy DB1200 Referrence Board 2 * AMD Alchemy DBAu1200 Reference Board
3 * Board Registers defines. 3 * Board register defines.
4 * 4 *
5 * ######################################################################## 5 * ########################################################################
6 * 6 *
@@ -27,26 +27,25 @@
27#include <linux/types.h> 27#include <linux/types.h>
28#include <asm/mach-au1x00/au1xxx_psc.h> 28#include <asm/mach-au1x00/au1xxx_psc.h>
29 29
30// This is defined in au1000.h with bogus value 30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31#undef AU1X00_EXTERNAL_INT 31#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
32 34
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX 35/*
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX 36 * SPI and SMB are muxed on the DBAu1200 board.
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX 37 * Refer to board documentation.
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
37
38/* SPI and SMB are muxed on the Pb1200 board.
39 Refer to board documentation.
40 */ 38 */
41#define SPI_PSC_BASE PSC0_BASE_ADDR 39#define SPI_PSC_BASE PSC0_BASE_ADDR
42#define SMBUS_PSC_BASE PSC0_BASE_ADDR 40#define SMBUS_PSC_BASE PSC0_BASE_ADDR
43/* AC97 and I2S are muxed on the Pb1200 board. 41/*
44 Refer to board documentation. 42 * AC'97 and I2S are muxed on the DBAu1200 board.
43 * Refer to board documentation.
45 */ 44 */
46#define AC97_PSC_BASE PSC1_BASE_ADDR 45#define AC97_PSC_BASE PSC1_BASE_ADDR
47#define I2S_PSC_BASE PSC1_BASE_ADDR 46#define I2S_PSC_BASE PSC1_BASE_ADDR
48 47
49#define BCSR_KSEG1_ADDR 0xB9800000 48#define BCSR_KSEG1_ADDR 0xB9800000
50 49
51typedef volatile struct 50typedef volatile struct
52{ 51{
@@ -102,9 +101,9 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
102#define BCSR_STATUS_SWAPBOOT 0x0040 101#define BCSR_STATUS_SWAPBOOT 0x0040
103#define BCSR_STATUS_FLASHBUSY 0x0100 102#define BCSR_STATUS_FLASHBUSY 0x0100
104#define BCSR_STATUS_IDECBLID 0x0200 103#define BCSR_STATUS_IDECBLID 0x0200
105#define BCSR_STATUS_SD0WP 0x0400 104#define BCSR_STATUS_SD0WP 0x0400
106#define BCSR_STATUS_U0RXD 0x1000 105#define BCSR_STATUS_U0RXD 0x1000
107#define BCSR_STATUS_U1RXD 0x2000 106#define BCSR_STATUS_U1RXD 0x2000
108 107
109#define BCSR_SWITCHES_OCTAL 0x00FF 108#define BCSR_SWITCHES_OCTAL 0x00FF
110#define BCSR_SWITCHES_DIP_1 0x0080 109#define BCSR_SWITCHES_DIP_1 0x0080
@@ -122,8 +121,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
122#define BCSR_RESETS_DC 0x0004 121#define BCSR_RESETS_DC 0x0004
123#define BCSR_RESETS_IDE 0x0008 122#define BCSR_RESETS_IDE 0x0008
124#define BCSR_RESETS_TV 0x0010 123#define BCSR_RESETS_TV 0x0010
125/* not resets but in the same register */ 124/* Not resets but in the same register */
126#define BCSR_RESETS_PWMR1mUX 0x0800 125#define BCSR_RESETS_PWMR1MUX 0x0800
127#define BCSR_RESETS_PCS0MUX 0x1000 126#define BCSR_RESETS_PCS0MUX 0x1000
128#define BCSR_RESETS_PCS1MUX 0x2000 127#define BCSR_RESETS_PCS1MUX 0x2000
129#define BCSR_RESETS_SPISEL 0x4000 128#define BCSR_RESETS_SPISEL 0x4000
@@ -160,7 +159,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
160#define BCSR_INT_PC0STSCHG 0x0008 159#define BCSR_INT_PC0STSCHG 0x0008
161#define BCSR_INT_PC1 0x0010 160#define BCSR_INT_PC1 0x0010
162#define BCSR_INT_PC1STSCHG 0x0020 161#define BCSR_INT_PC1STSCHG 0x0020
163#define BCSR_INT_DC 0x0040 162#define BCSR_INT_DC 0x0040
164#define BCSR_INT_FLASHBUSY 0x0080 163#define BCSR_INT_FLASHBUSY 0x0080
165#define BCSR_INT_PC0INSERT 0x0100 164#define BCSR_INT_PC0INSERT 0x0100
166#define BCSR_INT_PC0EJECT 0x0200 165#define BCSR_INT_PC0EJECT 0x0200
@@ -179,10 +178,10 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
179#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 178#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
180#define IDE_RQSIZE 128 179#define IDE_RQSIZE 128
181 180
182#define NAND_PHYS_ADDR 0x20000000 181#define NAND_PHYS_ADDR 0x20000000
183 182
184/* 183/*
185 * External Interrupts for Pb1200 as of 8/6/2004. 184 * External Interrupts for DBAu1200 as of 8/6/2004.
186 * Bit positions in the CPLD registers can be calculated by taking 185 * Bit positions in the CPLD registers can be calculated by taking
187 * the interrupt define and subtracting the DB1200_INT_BEGIN value. 186 * the interrupt define and subtracting the DB1200_INT_BEGIN value.
188 * 187 *
@@ -211,23 +210,21 @@ enum external_pb1200_ints {
211}; 210};
212 211
213 212
214/* For drivers/pcmcia/au1000_db1x00.c */ 213/*
215 214 * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
216/* PCMCIA Db1x00 specific defines */ 215 */
217 216#define PCMCIA_MAX_SOCK 1
218#define PCMCIA_MAX_SOCK 1 217#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
219#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
220 218
221/* VPP/VCC */ 219/* VPP/VCC */
222#define SET_VCC_VPP(VCC, VPP, SLOT)\ 220#define SET_VCC_VPP(VCC, VPP, SLOT) \
223 ((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8)) 221 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
224 222
225#define BOARD_PC0_INT DB1200_PC0_INT 223#define BOARD_PC0_INT DB1200_PC0_INT
226#define BOARD_PC1_INT DB1200_PC1_INT 224#define BOARD_PC1_INT DB1200_PC1_INT
227#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET))) 225#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
228 226
229/* Nand chip select */ 227/* NAND chip select */
230#define NAND_CS 1 228#define NAND_CS 1
231 229
232#endif /* __ASM_DB1200_H */ 230#endif /* __ASM_DB1200_H */
233