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authorRalf Baechle <ralf@linux-mips.org>2008-09-16 13:48:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:52 -0400
commit384740dc49ea651ba350704d13ff6be9976e37fe (patch)
treea6e80cad287ccae7a86d81bfa692fc96889c88ed /include/asm-mips/mach-db1x00
parente8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff)
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-db1x00')
-rw-r--r--include/asm-mips/mach-db1x00/db1200.h230
-rw-r--r--include/asm-mips/mach-db1x00/db1x00.h179
2 files changed, 0 insertions, 409 deletions
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
deleted file mode 100644
index 27f26102b1bb..000000000000
--- a/include/asm-mips/mach-db1x00/db1200.h
+++ /dev/null
@@ -1,230 +0,0 @@
1/*
2 * AMD Alchemy DBAu1200 Reference Board
3 * Board register defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_DB1200_H
25#define __ASM_DB1200_H
26
27#include <linux/types.h>
28#include <asm/mach-au1x00/au1xxx_psc.h>
29
30#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
31#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
32#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
34
35/*
36 * SPI and SMB are muxed on the DBAu1200 board.
37 * Refer to board documentation.
38 */
39#define SPI_PSC_BASE PSC0_BASE_ADDR
40#define SMBUS_PSC_BASE PSC0_BASE_ADDR
41/*
42 * AC'97 and I2S are muxed on the DBAu1200 board.
43 * Refer to board documentation.
44 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR
47
48#define BCSR_KSEG1_ADDR 0xB9800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_U0RXD 0x1000
106#define BCSR_STATUS_U1RXD 0x2000
107
108#define BCSR_SWITCHES_OCTAL 0x00FF
109#define BCSR_SWITCHES_DIP_1 0x0080
110#define BCSR_SWITCHES_DIP_2 0x0040
111#define BCSR_SWITCHES_DIP_3 0x0020
112#define BCSR_SWITCHES_DIP_4 0x0010
113#define BCSR_SWITCHES_DIP_5 0x0008
114#define BCSR_SWITCHES_DIP_6 0x0004
115#define BCSR_SWITCHES_DIP_7 0x0002
116#define BCSR_SWITCHES_DIP_8 0x0001
117#define BCSR_SWITCHES_ROTARY 0x0F00
118
119#define BCSR_RESETS_ETH 0x0001
120#define BCSR_RESETS_CAMERA 0x0002
121#define BCSR_RESETS_DC 0x0004
122#define BCSR_RESETS_IDE 0x0008
123#define BCSR_RESETS_TV 0x0010
124/* Not resets but in the same register */
125#define BCSR_RESETS_PWMR1MUX 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129
130#define BCSR_PCMCIA_PC0VPP 0x0003
131#define BCSR_PCMCIA_PC0VCC 0x000C
132#define BCSR_PCMCIA_PC0DRVEN 0x0010
133#define BCSR_PCMCIA_PC0RST 0x0080
134#define BCSR_PCMCIA_PC1VPP 0x0300
135#define BCSR_PCMCIA_PC1VCC 0x0C00
136#define BCSR_PCMCIA_PC1DRVEN 0x1000
137#define BCSR_PCMCIA_PC1RST 0x8000
138
139#define BCSR_BOARD_LCDVEE 0x0001
140#define BCSR_BOARD_LCDVDD 0x0002
141#define BCSR_BOARD_LCDBL 0x0004
142#define BCSR_BOARD_CAMSNAP 0x0010
143#define BCSR_BOARD_CAMPWR 0x0020
144#define BCSR_BOARD_SD0PWR 0x0040
145
146#define BCSR_LEDS_DECIMALS 0x0003
147#define BCSR_LEDS_LED0 0x0100
148#define BCSR_LEDS_LED1 0x0200
149#define BCSR_LEDS_LED2 0x0400
150#define BCSR_LEDS_LED3 0x0800
151
152#define BCSR_SYSTEM_POWEROFF 0x4000
153#define BCSR_SYSTEM_RESET 0x8000
154
155/* Bit positions for the different interrupt sources */
156#define BCSR_INT_IDE 0x0001
157#define BCSR_INT_ETH 0x0002
158#define BCSR_INT_PC0 0x0004
159#define BCSR_INT_PC0STSCHG 0x0008
160#define BCSR_INT_PC1 0x0010
161#define BCSR_INT_PC1STSCHG 0x0020
162#define BCSR_INT_DC 0x0040
163#define BCSR_INT_FLASHBUSY 0x0080
164#define BCSR_INT_PC0INSERT 0x0100
165#define BCSR_INT_PC0EJECT 0x0200
166#define BCSR_INT_PC1INSERT 0x0400
167#define BCSR_INT_PC1EJECT 0x0800
168#define BCSR_INT_SD0INSERT 0x1000
169#define BCSR_INT_SD0EJECT 0x2000
170
171#define SMC91C111_PHYS_ADDR 0x19000300
172#define SMC91C111_INT DB1200_ETH_INT
173
174#define IDE_PHYS_ADDR 0x18800000
175#define IDE_REG_SHIFT 5
176#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
177#define IDE_INT DB1200_IDE_INT
178#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
179#define IDE_RQSIZE 128
180
181#define NAND_PHYS_ADDR 0x20000000
182
183/*
184 * External Interrupts for DBAu1200 as of 8/6/2004.
185 * Bit positions in the CPLD registers can be calculated by taking
186 * the interrupt define and subtracting the DB1200_INT_BEGIN value.
187 *
188 * Example: IDE bis pos is = 64 - 64
189 * ETH bit pos is = 65 - 64
190 */
191enum external_pb1200_ints {
192 DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
193
194 DB1200_IDE_INT = DB1200_INT_BEGIN,
195 DB1200_ETH_INT,
196 DB1200_PC0_INT,
197 DB1200_PC0_STSCHG_INT,
198 DB1200_PC1_INT,
199 DB1200_PC1_STSCHG_INT,
200 DB1200_DC_INT,
201 DB1200_FLASHBUSY_INT,
202 DB1200_PC0_INSERT_INT,
203 DB1200_PC0_EJECT_INT,
204 DB1200_PC1_INSERT_INT,
205 DB1200_PC1_EJECT_INT,
206 DB1200_SD0_INSERT_INT,
207 DB1200_SD0_EJECT_INT,
208
209 DB1200_INT_END = DB1200_INT_BEGIN + 15,
210};
211
212
213/*
214 * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
215 */
216#define PCMCIA_MAX_SOCK 1
217#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
218
219/* VPP/VCC */
220#define SET_VCC_VPP(VCC, VPP, SLOT) \
221 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
222
223#define BOARD_PC0_INT DB1200_PC0_INT
224#define BOARD_PC1_INT DB1200_PC1_INT
225#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
226
227/* NAND chip select */
228#define NAND_CS 1
229
230#endif /* __ASM_DB1200_H */
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
deleted file mode 100644
index 1a515b8c870f..000000000000
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ /dev/null
@@ -1,179 +0,0 @@
1/*
2 * AMD Alchemy DBAu1x00 Reference Boards
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_DB1X00_H
28#define __ASM_DB1X00_H
29
30#include <asm/mach-au1x00/au1xxx_psc.h>
31
32#ifdef CONFIG_MIPS_DB1550
33
34#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
35#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
36#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
37#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
38
39#define SPI_PSC_BASE PSC0_BASE_ADDR
40#define AC97_PSC_BASE PSC1_BASE_ADDR
41#define SMBUS_PSC_BASE PSC2_BASE_ADDR
42#define I2S_PSC_BASE PSC3_BASE_ADDR
43
44#define BCSR_KSEG1_ADDR 0xAF000000
45#define NAND_PHYS_ADDR 0x20000000
46
47#else
48#define BCSR_KSEG1_ADDR 0xAE000000
49#endif
50
51/*
52 * Overlay data structure of the DBAu1x00 board registers.
53 * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
54 */
55typedef volatile struct
56{
57 /*00*/ unsigned short whoami;
58 unsigned short reserved0;
59 /*04*/ unsigned short status;
60 unsigned short reserved1;
61 /*08*/ unsigned short switches;
62 unsigned short reserved2;
63 /*0C*/ unsigned short resets;
64 unsigned short reserved3;
65 /*10*/ unsigned short pcmcia;
66 unsigned short reserved4;
67 /*14*/ unsigned short specific;
68 unsigned short reserved5;
69 /*18*/ unsigned short leds;
70 unsigned short reserved6;
71 /*1C*/ unsigned short swreset;
72 unsigned short reserved7;
73
74} BCSR;
75
76
77/*
78 * Register/mask bit definitions for the BCSRs
79 */
80#define BCSR_WHOAMI_DCID 0x000F
81#define BCSR_WHOAMI_CPLD 0x00F0
82#define BCSR_WHOAMI_BOARD 0x0F00
83
84#define BCSR_STATUS_PC0VS 0x0003
85#define BCSR_STATUS_PC1VS 0x000C
86#define BCSR_STATUS_PC0FI 0x0010
87#define BCSR_STATUS_PC1FI 0x0020
88#define BCSR_STATUS_FLASHBUSY 0x0100
89#define BCSR_STATUS_ROMBUSY 0x0400
90#define BCSR_STATUS_SWAPBOOT 0x2000
91#define BCSR_STATUS_FLASHDEN 0xC000
92
93#define BCSR_SWITCHES_DIP 0x00FF
94#define BCSR_SWITCHES_DIP_1 0x0080
95#define BCSR_SWITCHES_DIP_2 0x0040
96#define BCSR_SWITCHES_DIP_3 0x0020
97#define BCSR_SWITCHES_DIP_4 0x0010
98#define BCSR_SWITCHES_DIP_5 0x0008
99#define BCSR_SWITCHES_DIP_6 0x0004
100#define BCSR_SWITCHES_DIP_7 0x0002
101#define BCSR_SWITCHES_DIP_8 0x0001
102#define BCSR_SWITCHES_ROTARY 0x0F00
103
104#define BCSR_RESETS_PHY0 0x0001
105#define BCSR_RESETS_PHY1 0x0002
106#define BCSR_RESETS_DC 0x0004
107#define BCSR_RESETS_FIR_SEL 0x2000
108#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
109#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
110#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
111#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
112#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
113
114#define BCSR_PCMCIA_PC0VPP 0x0003
115#define BCSR_PCMCIA_PC0VCC 0x000C
116#define BCSR_PCMCIA_PC0DRVEN 0x0010
117#define BCSR_PCMCIA_PC0RST 0x0080
118#define BCSR_PCMCIA_PC1VPP 0x0300
119#define BCSR_PCMCIA_PC1VCC 0x0C00
120#define BCSR_PCMCIA_PC1DRVEN 0x1000
121#define BCSR_PCMCIA_PC1RST 0x8000
122
123#define BCSR_BOARD_PCIM66EN 0x0001
124#define BCSR_BOARD_SD0_PWR 0x0040
125#define BCSR_BOARD_SD1_PWR 0x0080
126#define BCSR_BOARD_PCIM33 0x0100
127#define BCSR_BOARD_GPIO200RST 0x0400
128#define BCSR_BOARD_PCICFG 0x1000
129#define BCSR_BOARD_SD0_WP 0x4000
130#define BCSR_BOARD_SD1_WP 0x8000
131
132#define BCSR_LEDS_DECIMALS 0x0003
133#define BCSR_LEDS_LED0 0x0100
134#define BCSR_LEDS_LED1 0x0200
135#define BCSR_LEDS_LED2 0x0400
136#define BCSR_LEDS_LED3 0x0800
137
138#define BCSR_SWRESET_RESET 0x0080
139
140/* PCMCIA DBAu1x00 specific defines */
141#define PCMCIA_MAX_SOCK 1
142#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
143
144/* VPP/VCC */
145#define SET_VCC_VPP(VCC, VPP, SLOT)\
146 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
147
148/*
149 * NAND defines
150 *
151 * Timing values as described in databook, * ns value stripped of the
152 * lower 2 bits.
153 * These defines are here rather than an Au1550 generic file because
154 * the parts chosen on another board may be different and may require
155 * different timings.
156 */
157#define NAND_T_H (18 >> 2)
158#define NAND_T_PUL (30 >> 2)
159#define NAND_T_SU (30 >> 2)
160#define NAND_T_WH (30 >> 2)
161
162/* Bitfield shift amounts */
163#define NAND_T_H_SHIFT 0
164#define NAND_T_PUL_SHIFT 4
165#define NAND_T_SU_SHIFT 8
166#define NAND_T_WH_SHIFT 12
167
168#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
169 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
170 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
171 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
172#define NAND_CS 1
173
174/* Should be done by YAMON */
175#define NAND_STCFG 0x00400005 /* 8-bit NAND */
176#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
177#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
178
179#endif /* __ASM_DB1X00_H */
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