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authorIngo Molnar <mingo@elte.hu>2008-10-12 05:32:17 -0400
committerIngo Molnar <mingo@elte.hu>2008-10-12 05:32:17 -0400
commit206855c321adee56db3946ca09a5887cddb9d598 (patch)
tree13a2729d4d0e37170552bd9ad3c6bba71ba0c55c /include/asm-mips/mach-db1x00/db1x00.h
parente8d3f455de4f42d4bab2f6f1aeb2cf3bd18eb508 (diff)
parentcb58ffc3889f0545628f138f849e759a331b8ddc (diff)
Merge branch 'x86/urgent' into core/signal
Conflicts: arch/x86/kernel/signal_64.c
Diffstat (limited to 'include/asm-mips/mach-db1x00/db1x00.h')
-rw-r--r--include/asm-mips/mach-db1x00/db1x00.h179
1 files changed, 0 insertions, 179 deletions
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
deleted file mode 100644
index 1a515b8c870f..000000000000
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ /dev/null
@@ -1,179 +0,0 @@
1/*
2 * AMD Alchemy DBAu1x00 Reference Boards
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_DB1X00_H
28#define __ASM_DB1X00_H
29
30#include <asm/mach-au1x00/au1xxx_psc.h>
31
32#ifdef CONFIG_MIPS_DB1550
33
34#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
35#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
36#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
37#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
38
39#define SPI_PSC_BASE PSC0_BASE_ADDR
40#define AC97_PSC_BASE PSC1_BASE_ADDR
41#define SMBUS_PSC_BASE PSC2_BASE_ADDR
42#define I2S_PSC_BASE PSC3_BASE_ADDR
43
44#define BCSR_KSEG1_ADDR 0xAF000000
45#define NAND_PHYS_ADDR 0x20000000
46
47#else
48#define BCSR_KSEG1_ADDR 0xAE000000
49#endif
50
51/*
52 * Overlay data structure of the DBAu1x00 board registers.
53 * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
54 */
55typedef volatile struct
56{
57 /*00*/ unsigned short whoami;
58 unsigned short reserved0;
59 /*04*/ unsigned short status;
60 unsigned short reserved1;
61 /*08*/ unsigned short switches;
62 unsigned short reserved2;
63 /*0C*/ unsigned short resets;
64 unsigned short reserved3;
65 /*10*/ unsigned short pcmcia;
66 unsigned short reserved4;
67 /*14*/ unsigned short specific;
68 unsigned short reserved5;
69 /*18*/ unsigned short leds;
70 unsigned short reserved6;
71 /*1C*/ unsigned short swreset;
72 unsigned short reserved7;
73
74} BCSR;
75
76
77/*
78 * Register/mask bit definitions for the BCSRs
79 */
80#define BCSR_WHOAMI_DCID 0x000F
81#define BCSR_WHOAMI_CPLD 0x00F0
82#define BCSR_WHOAMI_BOARD 0x0F00
83
84#define BCSR_STATUS_PC0VS 0x0003
85#define BCSR_STATUS_PC1VS 0x000C
86#define BCSR_STATUS_PC0FI 0x0010
87#define BCSR_STATUS_PC1FI 0x0020
88#define BCSR_STATUS_FLASHBUSY 0x0100
89#define BCSR_STATUS_ROMBUSY 0x0400
90#define BCSR_STATUS_SWAPBOOT 0x2000
91#define BCSR_STATUS_FLASHDEN 0xC000
92
93#define BCSR_SWITCHES_DIP 0x00FF
94#define BCSR_SWITCHES_DIP_1 0x0080
95#define BCSR_SWITCHES_DIP_2 0x0040
96#define BCSR_SWITCHES_DIP_3 0x0020
97#define BCSR_SWITCHES_DIP_4 0x0010
98#define BCSR_SWITCHES_DIP_5 0x0008
99#define BCSR_SWITCHES_DIP_6 0x0004
100#define BCSR_SWITCHES_DIP_7 0x0002
101#define BCSR_SWITCHES_DIP_8 0x0001
102#define BCSR_SWITCHES_ROTARY 0x0F00
103
104#define BCSR_RESETS_PHY0 0x0001
105#define BCSR_RESETS_PHY1 0x0002
106#define BCSR_RESETS_DC 0x0004
107#define BCSR_RESETS_FIR_SEL 0x2000
108#define BCSR_RESETS_IRDA_MODE_MASK 0xC000
109#define BCSR_RESETS_IRDA_MODE_FULL 0x0000
110#define BCSR_RESETS_IRDA_MODE_OFF 0x4000
111#define BCSR_RESETS_IRDA_MODE_2_3 0x8000
112#define BCSR_RESETS_IRDA_MODE_1_3 0xC000
113
114#define BCSR_PCMCIA_PC0VPP 0x0003
115#define BCSR_PCMCIA_PC0VCC 0x000C
116#define BCSR_PCMCIA_PC0DRVEN 0x0010
117#define BCSR_PCMCIA_PC0RST 0x0080
118#define BCSR_PCMCIA_PC1VPP 0x0300
119#define BCSR_PCMCIA_PC1VCC 0x0C00
120#define BCSR_PCMCIA_PC1DRVEN 0x1000
121#define BCSR_PCMCIA_PC1RST 0x8000
122
123#define BCSR_BOARD_PCIM66EN 0x0001
124#define BCSR_BOARD_SD0_PWR 0x0040
125#define BCSR_BOARD_SD1_PWR 0x0080
126#define BCSR_BOARD_PCIM33 0x0100
127#define BCSR_BOARD_GPIO200RST 0x0400
128#define BCSR_BOARD_PCICFG 0x1000
129#define BCSR_BOARD_SD0_WP 0x4000
130#define BCSR_BOARD_SD1_WP 0x8000
131
132#define BCSR_LEDS_DECIMALS 0x0003
133#define BCSR_LEDS_LED0 0x0100
134#define BCSR_LEDS_LED1 0x0200
135#define BCSR_LEDS_LED2 0x0400
136#define BCSR_LEDS_LED3 0x0800
137
138#define BCSR_SWRESET_RESET 0x0080
139
140/* PCMCIA DBAu1x00 specific defines */
141#define PCMCIA_MAX_SOCK 1
142#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
143
144/* VPP/VCC */
145#define SET_VCC_VPP(VCC, VPP, SLOT)\
146 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
147
148/*
149 * NAND defines
150 *
151 * Timing values as described in databook, * ns value stripped of the
152 * lower 2 bits.
153 * These defines are here rather than an Au1550 generic file because
154 * the parts chosen on another board may be different and may require
155 * different timings.
156 */
157#define NAND_T_H (18 >> 2)
158#define NAND_T_PUL (30 >> 2)
159#define NAND_T_SU (30 >> 2)
160#define NAND_T_WH (30 >> 2)
161
162/* Bitfield shift amounts */
163#define NAND_T_H_SHIFT 0
164#define NAND_T_PUL_SHIFT 4
165#define NAND_T_SU_SHIFT 8
166#define NAND_T_WH_SHIFT 12
167
168#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
169 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
170 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
171 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
172#define NAND_CS 1
173
174/* Should be done by YAMON */
175#define NAND_STCFG 0x00400005 /* 8-bit NAND */
176#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
177#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
178
179#endif /* __ASM_DB1X00_H */
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