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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2007-09-13 10:51:26 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:04 -0400
commitd5ab1a6910fe850fa092888f210cf6c43136a7ab (patch)
tree142f9f35f0d9fc6e675caf42a1cd8a82b56aa8e9 /include/asm-mips/mach-cobalt
parent718f05f6ddc171a90fb7a277be6f6f65b4ca82be (diff)
[MIPS] Add GT641xx IRQ routines.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-cobalt')
-rw-r--r--include/asm-mips/mach-cobalt/cobalt.h26
-rw-r--r--include/asm-mips/mach-cobalt/irq.h58
2 files changed, 58 insertions, 26 deletions
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
index 9c9d2b998ca4..408eeccbe512 100644
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ b/include/asm-mips/mach-cobalt/cobalt.h
@@ -12,32 +12,6 @@
12#ifndef __ASM_COBALT_H 12#ifndef __ASM_COBALT_H
13#define __ASM_COBALT_H 13#define __ASM_COBALT_H
14 14
15#include <irq.h>
16
17/*
18 * i8259 legacy interrupts used on Cobalt:
19 *
20 * 8 - RTC
21 * 9 - PCI
22 * 14 - IDE0
23 * 15 - IDE1
24 */
25#define COBALT_QUBE_SLOT_IRQ 9
26
27/*
28 * CPU IRQs are 16 ... 23
29 */
30#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE
31
32#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
33#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
34#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
35#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
36#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4)
37#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5)
38#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5)
39#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */
40
41/* 15/*
42 * PCI configuration space manifest constants. These are wired into 16 * PCI configuration space manifest constants. These are wired into
43 * the board layout according to the PCI spec to enable the software 17 * the board layout according to the PCI spec to enable the software
diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h
new file mode 100644
index 000000000000..179d0e850b59
--- /dev/null
+++ b/include/asm-mips/mach-cobalt/irq.h
@@ -0,0 +1,58 @@
1/*
2 * Cobalt IRQ definitions.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1997 Cobalt Microserver
9 * Copyright (C) 1997, 2003 Ralf Baechle
10 * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
11 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
12 */
13#ifndef _ASM_COBALT_IRQ_H
14#define _ASM_COBALT_IRQ_H
15
16/*
17 * i8259 interrupts used on Cobalt:
18 *
19 * 8 - RTC
20 * 9 - PCI slot
21 * 14 - IDE0
22 * 15 - IDE1(no connector on board)
23 */
24#define I8259A_IRQ_BASE 0
25
26#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9)
27
28/*
29 * CPU interrupts used on Cobalt:
30 *
31 * 0 - Software interrupt 0 (unused)
32 * 1 - Software interrupt 0 (unused)
33 * 2 - cascade GT64111
34 * 3 - ethernet or SCSI host controller
35 * 4 - ethernet
36 * 5 - 16550 UART
37 * 6 - cascade i8259
38 * 7 - CP0 counter (unused)
39 */
40#define MIPS_CPU_IRQ_BASE 16
41
42#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
43#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
44#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
45#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
46#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
47#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
48#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
49#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
50
51
52#define GT641XX_IRQ_BASE 24
53
54#include <asm/irq_gt641xx.h>
55
56#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1)
57
58#endif /* _ASM_COBALT_IRQ_H */