diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:05 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:05 -0400 |
| commit | 641e97f318870921d048154af6807e46e43c307a (patch) | |
| tree | 6e0984a1bc8932db848be3fdb104a92c97fe341a /include/asm-mips/mach-cobalt | |
| parent | 424b28ba4d25fc41abdb7e6fa90e132f0d9558fb (diff) | |
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.
Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-cobalt')
| -rw-r--r-- | include/asm-mips/mach-cobalt/cpu-feature-overrides.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h index d38f069d9e95..b3314cf53194 100644 --- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h +++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | #define cpu_has_3k_cache 0 | 14 | #define cpu_has_3k_cache 0 |
| 15 | #define cpu_has_4k_cache 1 | 15 | #define cpu_has_4k_cache 1 |
| 16 | #define cpu_has_tx39_cache 0 | 16 | #define cpu_has_tx39_cache 0 |
| 17 | #define cpu_has_sb1_cache 0 | ||
| 18 | #define cpu_has_fpu 1 | 17 | #define cpu_has_fpu 1 |
| 19 | #define cpu_has_32fpr 1 | 18 | #define cpu_has_32fpr 1 |
| 20 | #define cpu_has_counter 1 | 19 | #define cpu_has_counter 1 |