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authorRalf Baechle <ralf@linux-mips.org>2008-09-16 13:48:51 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-11 11:18:52 -0400
commit384740dc49ea651ba350704d13ff6be9976e37fe (patch)
treea6e80cad287ccae7a86d81bfa692fc96889c88ed /include/asm-mips/mach-au1x00
parente8c7c482347574ecdd45c43e32c332d5fc2ece61 (diff)
MIPS: Move headfiles to new location below arch/mips/include
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/mach-au1x00')
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h1772
-rw-r--r--include/asm-mips/mach-au1x00/au1000_dma.h458
-rw-r--r--include/asm-mips/mach-au1x00/au1000_gpio.h56
-rw-r--r--include/asm-mips/mach-au1x00/au1100_mmc.h208
-rw-r--r--include/asm-mips/mach-au1x00/au1550_spi.h15
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx.h43
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_dbdma.h386
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_ide.h194
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_psc.h505
-rw-r--r--include/asm-mips/mach-au1x00/gpio.h69
-rw-r--r--include/asm-mips/mach-au1x00/ioremap.h42
-rw-r--r--include/asm-mips/mach-au1x00/prom.h13
-rw-r--r--include/asm-mips/mach-au1x00/war.h25
13 files changed, 0 insertions, 3786 deletions
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
deleted file mode 100644
index 0d302bad4492..000000000000
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ /dev/null
@@ -1,1772 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30 /*
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
32 */
33
34#ifndef _AU1000_H_
35#define _AU1000_H_
36
37
38#ifndef _LANGUAGE_ASSEMBLY
39
40#include <linux/delay.h>
41#include <linux/types.h>
42
43#include <linux/io.h>
44#include <linux/irq.h>
45
46/* cpu pipeline flush */
47void static inline au_sync(void)
48{
49 __asm__ volatile ("sync");
50}
51
52void static inline au_sync_udelay(int us)
53{
54 __asm__ volatile ("sync");
55 udelay(us);
56}
57
58void static inline au_sync_delay(int ms)
59{
60 __asm__ volatile ("sync");
61 mdelay(ms);
62}
63
64void static inline au_writeb(u8 val, unsigned long reg)
65{
66 *(volatile u8 *)reg = val;
67}
68
69void static inline au_writew(u16 val, unsigned long reg)
70{
71 *(volatile u16 *)reg = val;
72}
73
74void static inline au_writel(u32 val, unsigned long reg)
75{
76 *(volatile u32 *)reg = val;
77}
78
79static inline u8 au_readb(unsigned long reg)
80{
81 return *(volatile u8 *)reg;
82}
83
84static inline u16 au_readw(unsigned long reg)
85{
86 return *(volatile u16 *)reg;
87}
88
89static inline u32 au_readl(unsigned long reg)
90{
91 return *(volatile u32 *)reg;
92}
93
94
95/* arch/mips/au1000/common/clocks.c */
96extern void set_au1x00_speed(unsigned int new_freq);
97extern unsigned int get_au1x00_speed(void);
98extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
99extern unsigned long get_au1x00_uart_baud_base(void);
100extern void set_au1x00_lcd_clock(void);
101extern unsigned int get_au1x00_lcd_clock(void);
102
103/*
104 * Every board describes its IRQ mapping with this table.
105 */
106struct au1xxx_irqmap {
107 int im_irq;
108 int im_type;
109 int im_request;
110};
111
112/*
113 * init_IRQ looks for a table with this name.
114 */
115extern struct au1xxx_irqmap au1xxx_irq_map[];
116
117#endif /* !defined (_LANGUAGE_ASSEMBLY) */
118
119/*
120 * SDRAM register offsets
121 */
122#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
123 defined(CONFIG_SOC_AU1100)
124#define MEM_SDMODE0 0x0000
125#define MEM_SDMODE1 0x0004
126#define MEM_SDMODE2 0x0008
127#define MEM_SDADDR0 0x000C
128#define MEM_SDADDR1 0x0010
129#define MEM_SDADDR2 0x0014
130#define MEM_SDREFCFG 0x0018
131#define MEM_SDPRECMD 0x001C
132#define MEM_SDAUTOREF 0x0020
133#define MEM_SDWRMD0 0x0024
134#define MEM_SDWRMD1 0x0028
135#define MEM_SDWRMD2 0x002C
136#define MEM_SDSLEEP 0x0030
137#define MEM_SDSMCKE 0x0034
138
139/*
140 * MEM_SDMODE register content definitions
141 */
142#define MEM_SDMODE_F (1 << 22)
143#define MEM_SDMODE_SR (1 << 21)
144#define MEM_SDMODE_BS (1 << 20)
145#define MEM_SDMODE_RS (3 << 18)
146#define MEM_SDMODE_CS (7 << 15)
147#define MEM_SDMODE_TRAS (15 << 11)
148#define MEM_SDMODE_TMRD (3 << 9)
149#define MEM_SDMODE_TWR (3 << 7)
150#define MEM_SDMODE_TRP (3 << 5)
151#define MEM_SDMODE_TRCD (3 << 3)
152#define MEM_SDMODE_TCL (7 << 0)
153
154#define MEM_SDMODE_BS_2Bank (0 << 20)
155#define MEM_SDMODE_BS_4Bank (1 << 20)
156#define MEM_SDMODE_RS_11Row (0 << 18)
157#define MEM_SDMODE_RS_12Row (1 << 18)
158#define MEM_SDMODE_RS_13Row (2 << 18)
159#define MEM_SDMODE_RS_N(N) ((N) << 18)
160#define MEM_SDMODE_CS_7Col (0 << 15)
161#define MEM_SDMODE_CS_8Col (1 << 15)
162#define MEM_SDMODE_CS_9Col (2 << 15)
163#define MEM_SDMODE_CS_10Col (3 << 15)
164#define MEM_SDMODE_CS_11Col (4 << 15)
165#define MEM_SDMODE_CS_N(N) ((N) << 15)
166#define MEM_SDMODE_TRAS_N(N) ((N) << 11)
167#define MEM_SDMODE_TMRD_N(N) ((N) << 9)
168#define MEM_SDMODE_TWR_N(N) ((N) << 7)
169#define MEM_SDMODE_TRP_N(N) ((N) << 5)
170#define MEM_SDMODE_TRCD_N(N) ((N) << 3)
171#define MEM_SDMODE_TCL_N(N) ((N) << 0)
172
173/*
174 * MEM_SDADDR register contents definitions
175 */
176#define MEM_SDADDR_E (1 << 20)
177#define MEM_SDADDR_CSBA (0x03FF << 10)
178#define MEM_SDADDR_CSMASK (0x03FF << 0)
179#define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
180#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
181
182/*
183 * MEM_SDREFCFG register content definitions
184 */
185#define MEM_SDREFCFG_TRC (15 << 28)
186#define MEM_SDREFCFG_TRPM (3 << 26)
187#define MEM_SDREFCFG_E (1 << 25)
188#define MEM_SDREFCFG_RE (0x1ffffff << 0)
189#define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
190#define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
191#define MEM_SDREFCFG_REF_N(N) (N)
192#endif
193
194/***********************************************************************/
195
196/*
197 * Au1550 SDRAM Register Offsets
198 */
199
200/***********************************************************************/
201
202#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
203#define MEM_SDMODE0 0x0800
204#define MEM_SDMODE1 0x0808
205#define MEM_SDMODE2 0x0810
206#define MEM_SDADDR0 0x0820
207#define MEM_SDADDR1 0x0828
208#define MEM_SDADDR2 0x0830
209#define MEM_SDCONFIGA 0x0840
210#define MEM_SDCONFIGB 0x0848
211#define MEM_SDSTAT 0x0850
212#define MEM_SDERRADDR 0x0858
213#define MEM_SDSTRIDE0 0x0860
214#define MEM_SDSTRIDE1 0x0868
215#define MEM_SDSTRIDE2 0x0870
216#define MEM_SDWRMD0 0x0880
217#define MEM_SDWRMD1 0x0888
218#define MEM_SDWRMD2 0x0890
219#define MEM_SDPRECMD 0x08C0
220#define MEM_SDAUTOREF 0x08C8
221#define MEM_SDSREF 0x08D0
222#define MEM_SDSLEEP MEM_SDSREF
223
224#endif
225
226/*
227 * Physical base addresses for integrated peripherals
228 */
229
230#ifdef CONFIG_SOC_AU1000
231#define MEM_PHYS_ADDR 0x14000000
232#define STATIC_MEM_PHYS_ADDR 0x14001000
233#define DMA0_PHYS_ADDR 0x14002000
234#define DMA1_PHYS_ADDR 0x14002100
235#define DMA2_PHYS_ADDR 0x14002200
236#define DMA3_PHYS_ADDR 0x14002300
237#define DMA4_PHYS_ADDR 0x14002400
238#define DMA5_PHYS_ADDR 0x14002500
239#define DMA6_PHYS_ADDR 0x14002600
240#define DMA7_PHYS_ADDR 0x14002700
241#define IC0_PHYS_ADDR 0x10400000
242#define IC1_PHYS_ADDR 0x11800000
243#define AC97_PHYS_ADDR 0x10000000
244#define USBH_PHYS_ADDR 0x10100000
245#define USBD_PHYS_ADDR 0x10200000
246#define IRDA_PHYS_ADDR 0x10300000
247#define MAC0_PHYS_ADDR 0x10500000
248#define MAC1_PHYS_ADDR 0x10510000
249#define MACEN_PHYS_ADDR 0x10520000
250#define MACDMA0_PHYS_ADDR 0x14004000
251#define MACDMA1_PHYS_ADDR 0x14004200
252#define I2S_PHYS_ADDR 0x11000000
253#define UART0_PHYS_ADDR 0x11100000
254#define UART1_PHYS_ADDR 0x11200000
255#define UART2_PHYS_ADDR 0x11300000
256#define UART3_PHYS_ADDR 0x11400000
257#define SSI0_PHYS_ADDR 0x11600000
258#define SSI1_PHYS_ADDR 0x11680000
259#define SYS_PHYS_ADDR 0x11900000
260#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
261#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
262#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
263#endif
264
265/********************************************************************/
266
267#ifdef CONFIG_SOC_AU1500
268#define MEM_PHYS_ADDR 0x14000000
269#define STATIC_MEM_PHYS_ADDR 0x14001000
270#define DMA0_PHYS_ADDR 0x14002000
271#define DMA1_PHYS_ADDR 0x14002100
272#define DMA2_PHYS_ADDR 0x14002200
273#define DMA3_PHYS_ADDR 0x14002300
274#define DMA4_PHYS_ADDR 0x14002400
275#define DMA5_PHYS_ADDR 0x14002500
276#define DMA6_PHYS_ADDR 0x14002600
277#define DMA7_PHYS_ADDR 0x14002700
278#define IC0_PHYS_ADDR 0x10400000
279#define IC1_PHYS_ADDR 0x11800000
280#define AC97_PHYS_ADDR 0x10000000
281#define USBH_PHYS_ADDR 0x10100000
282#define USBD_PHYS_ADDR 0x10200000
283#define PCI_PHYS_ADDR 0x14005000
284#define MAC0_PHYS_ADDR 0x11500000
285#define MAC1_PHYS_ADDR 0x11510000
286#define MACEN_PHYS_ADDR 0x11520000
287#define MACDMA0_PHYS_ADDR 0x14004000
288#define MACDMA1_PHYS_ADDR 0x14004200
289#define I2S_PHYS_ADDR 0x11000000
290#define UART0_PHYS_ADDR 0x11100000
291#define UART3_PHYS_ADDR 0x11400000
292#define GPIO2_PHYS_ADDR 0x11700000
293#define SYS_PHYS_ADDR 0x11900000
294#define PCI_MEM_PHYS_ADDR 0x400000000ULL
295#define PCI_IO_PHYS_ADDR 0x500000000ULL
296#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
297#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
298#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
299#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
300#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
301#endif
302
303/********************************************************************/
304
305#ifdef CONFIG_SOC_AU1100
306#define MEM_PHYS_ADDR 0x14000000
307#define STATIC_MEM_PHYS_ADDR 0x14001000
308#define DMA0_PHYS_ADDR 0x14002000
309#define DMA1_PHYS_ADDR 0x14002100
310#define DMA2_PHYS_ADDR 0x14002200
311#define DMA3_PHYS_ADDR 0x14002300
312#define DMA4_PHYS_ADDR 0x14002400
313#define DMA5_PHYS_ADDR 0x14002500
314#define DMA6_PHYS_ADDR 0x14002600
315#define DMA7_PHYS_ADDR 0x14002700
316#define IC0_PHYS_ADDR 0x10400000
317#define SD0_PHYS_ADDR 0x10600000
318#define SD1_PHYS_ADDR 0x10680000
319#define IC1_PHYS_ADDR 0x11800000
320#define AC97_PHYS_ADDR 0x10000000
321#define USBH_PHYS_ADDR 0x10100000
322#define USBD_PHYS_ADDR 0x10200000
323#define IRDA_PHYS_ADDR 0x10300000
324#define MAC0_PHYS_ADDR 0x10500000
325#define MACEN_PHYS_ADDR 0x10520000
326#define MACDMA0_PHYS_ADDR 0x14004000
327#define MACDMA1_PHYS_ADDR 0x14004200
328#define I2S_PHYS_ADDR 0x11000000
329#define UART0_PHYS_ADDR 0x11100000
330#define UART1_PHYS_ADDR 0x11200000
331#define UART3_PHYS_ADDR 0x11400000
332#define SSI0_PHYS_ADDR 0x11600000
333#define SSI1_PHYS_ADDR 0x11680000
334#define GPIO2_PHYS_ADDR 0x11700000
335#define SYS_PHYS_ADDR 0x11900000
336#define LCD_PHYS_ADDR 0x15000000
337#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
338#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
339#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
340#endif
341
342/***********************************************************************/
343
344#ifdef CONFIG_SOC_AU1550
345#define MEM_PHYS_ADDR 0x14000000
346#define STATIC_MEM_PHYS_ADDR 0x14001000
347#define IC0_PHYS_ADDR 0x10400000
348#define IC1_PHYS_ADDR 0x11800000
349#define USBH_PHYS_ADDR 0x14020000
350#define USBD_PHYS_ADDR 0x10200000
351#define PCI_PHYS_ADDR 0x14005000
352#define MAC0_PHYS_ADDR 0x10500000
353#define MAC1_PHYS_ADDR 0x10510000
354#define MACEN_PHYS_ADDR 0x10520000
355#define MACDMA0_PHYS_ADDR 0x14004000
356#define MACDMA1_PHYS_ADDR 0x14004200
357#define UART0_PHYS_ADDR 0x11100000
358#define UART1_PHYS_ADDR 0x11200000
359#define UART3_PHYS_ADDR 0x11400000
360#define GPIO2_PHYS_ADDR 0x11700000
361#define SYS_PHYS_ADDR 0x11900000
362#define DDMA_PHYS_ADDR 0x14002000
363#define PE_PHYS_ADDR 0x14008000
364#define PSC0_PHYS_ADDR 0x11A00000
365#define PSC1_PHYS_ADDR 0x11B00000
366#define PSC2_PHYS_ADDR 0x10A00000
367#define PSC3_PHYS_ADDR 0x10B00000
368#define PCI_MEM_PHYS_ADDR 0x400000000ULL
369#define PCI_IO_PHYS_ADDR 0x500000000ULL
370#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
371#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
372#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
373#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
374#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
375#endif
376
377/***********************************************************************/
378
379#ifdef CONFIG_SOC_AU1200
380#define MEM_PHYS_ADDR 0x14000000
381#define STATIC_MEM_PHYS_ADDR 0x14001000
382#define AES_PHYS_ADDR 0x10300000
383#define CIM_PHYS_ADDR 0x14004000
384#define IC0_PHYS_ADDR 0x10400000
385#define IC1_PHYS_ADDR 0x11800000
386#define USBM_PHYS_ADDR 0x14020000
387#define USBH_PHYS_ADDR 0x14020100
388#define UART0_PHYS_ADDR 0x11100000
389#define UART1_PHYS_ADDR 0x11200000
390#define GPIO2_PHYS_ADDR 0x11700000
391#define SYS_PHYS_ADDR 0x11900000
392#define DDMA_PHYS_ADDR 0x14002000
393#define PSC0_PHYS_ADDR 0x11A00000
394#define PSC1_PHYS_ADDR 0x11B00000
395#define SD0_PHYS_ADDR 0x10600000
396#define SD1_PHYS_ADDR 0x10680000
397#define LCD_PHYS_ADDR 0x15000000
398#define SWCNT_PHYS_ADDR 0x1110010C
399#define MAEFE_PHYS_ADDR 0x14012000
400#define MAEBE_PHYS_ADDR 0x14010000
401#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
402#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
403#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
404#endif
405
406/* Static Bus Controller */
407#define MEM_STCFG0 0xB4001000
408#define MEM_STTIME0 0xB4001004
409#define MEM_STADDR0 0xB4001008
410
411#define MEM_STCFG1 0xB4001010
412#define MEM_STTIME1 0xB4001014
413#define MEM_STADDR1 0xB4001018
414
415#define MEM_STCFG2 0xB4001020
416#define MEM_STTIME2 0xB4001024
417#define MEM_STADDR2 0xB4001028
418
419#define MEM_STCFG3 0xB4001030
420#define MEM_STTIME3 0xB4001034
421#define MEM_STADDR3 0xB4001038
422
423#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
424#define MEM_STNDCTL 0xB4001100
425#define MEM_STSTAT 0xB4001104
426
427#define MEM_STNAND_CMD 0x0
428#define MEM_STNAND_ADDR 0x4
429#define MEM_STNAND_DATA 0x20
430#endif
431
432/* Interrupt Controller 0 */
433#define IC0_CFG0RD 0xB0400040
434#define IC0_CFG0SET 0xB0400040
435#define IC0_CFG0CLR 0xB0400044
436
437#define IC0_CFG1RD 0xB0400048
438#define IC0_CFG1SET 0xB0400048
439#define IC0_CFG1CLR 0xB040004C
440
441#define IC0_CFG2RD 0xB0400050
442#define IC0_CFG2SET 0xB0400050
443#define IC0_CFG2CLR 0xB0400054
444
445#define IC0_REQ0INT 0xB0400054
446#define IC0_SRCRD 0xB0400058
447#define IC0_SRCSET 0xB0400058
448#define IC0_SRCCLR 0xB040005C
449#define IC0_REQ1INT 0xB040005C
450
451#define IC0_ASSIGNRD 0xB0400060
452#define IC0_ASSIGNSET 0xB0400060
453#define IC0_ASSIGNCLR 0xB0400064
454
455#define IC0_WAKERD 0xB0400068
456#define IC0_WAKESET 0xB0400068
457#define IC0_WAKECLR 0xB040006C
458
459#define IC0_MASKRD 0xB0400070
460#define IC0_MASKSET 0xB0400070
461#define IC0_MASKCLR 0xB0400074
462
463#define IC0_RISINGRD 0xB0400078
464#define IC0_RISINGCLR 0xB0400078
465#define IC0_FALLINGRD 0xB040007C
466#define IC0_FALLINGCLR 0xB040007C
467
468#define IC0_TESTBIT 0xB0400080
469
470/* Interrupt Controller 1 */
471#define IC1_CFG0RD 0xB1800040
472#define IC1_CFG0SET 0xB1800040
473#define IC1_CFG0CLR 0xB1800044
474
475#define IC1_CFG1RD 0xB1800048
476#define IC1_CFG1SET 0xB1800048
477#define IC1_CFG1CLR 0xB180004C
478
479#define IC1_CFG2RD 0xB1800050
480#define IC1_CFG2SET 0xB1800050
481#define IC1_CFG2CLR 0xB1800054
482
483#define IC1_REQ0INT 0xB1800054
484#define IC1_SRCRD 0xB1800058
485#define IC1_SRCSET 0xB1800058
486#define IC1_SRCCLR 0xB180005C
487#define IC1_REQ1INT 0xB180005C
488
489#define IC1_ASSIGNRD 0xB1800060
490#define IC1_ASSIGNSET 0xB1800060
491#define IC1_ASSIGNCLR 0xB1800064
492
493#define IC1_WAKERD 0xB1800068
494#define IC1_WAKESET 0xB1800068
495#define IC1_WAKECLR 0xB180006C
496
497#define IC1_MASKRD 0xB1800070
498#define IC1_MASKSET 0xB1800070
499#define IC1_MASKCLR 0xB1800074
500
501#define IC1_RISINGRD 0xB1800078
502#define IC1_RISINGCLR 0xB1800078
503#define IC1_FALLINGRD 0xB180007C
504#define IC1_FALLINGCLR 0xB180007C
505
506#define IC1_TESTBIT 0xB1800080
507
508/* Interrupt Configuration Modes */
509#define INTC_INT_DISABLED 0x0
510#define INTC_INT_RISE_EDGE 0x1
511#define INTC_INT_FALL_EDGE 0x2
512#define INTC_INT_RISE_AND_FALL_EDGE 0x3
513#define INTC_INT_HIGH_LEVEL 0x5
514#define INTC_INT_LOW_LEVEL 0x6
515#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
516
517/* Interrupt Numbers */
518/* Au1000 */
519#ifdef CONFIG_SOC_AU1000
520enum soc_au1000_ints {
521 AU1000_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
522 AU1000_UART0_INT = AU1000_FIRST_INT,
523 AU1000_UART1_INT, /* au1000 */
524 AU1000_UART2_INT, /* au1000 */
525 AU1000_UART3_INT,
526 AU1000_SSI0_INT, /* au1000 */
527 AU1000_SSI1_INT, /* au1000 */
528 AU1000_DMA_INT_BASE,
529
530 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
531 AU1000_TOY_MATCH0_INT,
532 AU1000_TOY_MATCH1_INT,
533 AU1000_TOY_MATCH2_INT,
534 AU1000_RTC_INT,
535 AU1000_RTC_MATCH0_INT,
536 AU1000_RTC_MATCH1_INT,
537 AU1000_RTC_MATCH2_INT,
538 AU1000_IRDA_TX_INT, /* au1000 */
539 AU1000_IRDA_RX_INT, /* au1000 */
540 AU1000_USB_DEV_REQ_INT,
541 AU1000_USB_DEV_SUS_INT,
542 AU1000_USB_HOST_INT,
543 AU1000_ACSYNC_INT,
544 AU1000_MAC0_DMA_INT,
545 AU1000_MAC1_DMA_INT,
546 AU1000_I2S_UO_INT, /* au1000 */
547 AU1000_AC97C_INT,
548 AU1000_GPIO_0,
549 AU1000_GPIO_1,
550 AU1000_GPIO_2,
551 AU1000_GPIO_3,
552 AU1000_GPIO_4,
553 AU1000_GPIO_5,
554 AU1000_GPIO_6,
555 AU1000_GPIO_7,
556 AU1000_GPIO_8,
557 AU1000_GPIO_9,
558 AU1000_GPIO_10,
559 AU1000_GPIO_11,
560 AU1000_GPIO_12,
561 AU1000_GPIO_13,
562 AU1000_GPIO_14,
563 AU1000_GPIO_15,
564 AU1000_GPIO_16,
565 AU1000_GPIO_17,
566 AU1000_GPIO_18,
567 AU1000_GPIO_19,
568 AU1000_GPIO_20,
569 AU1000_GPIO_21,
570 AU1000_GPIO_22,
571 AU1000_GPIO_23,
572 AU1000_GPIO_24,
573 AU1000_GPIO_25,
574 AU1000_GPIO_26,
575 AU1000_GPIO_27,
576 AU1000_GPIO_28,
577 AU1000_GPIO_29,
578 AU1000_GPIO_30,
579 AU1000_GPIO_31,
580};
581
582#define UART0_ADDR 0xB1100000
583#define UART1_ADDR 0xB1200000
584#define UART2_ADDR 0xB1300000
585#define UART3_ADDR 0xB1400000
586
587#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
588#define USB_HOST_CONFIG 0xB017FFFC
589
590#define AU1000_ETH0_BASE 0xB0500000
591#define AU1000_ETH1_BASE 0xB0510000
592#define AU1000_MAC0_ENABLE 0xB0520000
593#define AU1000_MAC1_ENABLE 0xB0520004
594#define NUM_ETH_INTERFACES 2
595#endif /* CONFIG_SOC_AU1000 */
596
597/* Au1500 */
598#ifdef CONFIG_SOC_AU1500
599enum soc_au1500_ints {
600 AU1500_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
601 AU1500_UART0_INT = AU1500_FIRST_INT,
602 AU1000_PCI_INTA, /* au1500 */
603 AU1000_PCI_INTB, /* au1500 */
604 AU1500_UART3_INT,
605 AU1000_PCI_INTC, /* au1500 */
606 AU1000_PCI_INTD, /* au1500 */
607 AU1000_DMA_INT_BASE,
608
609 AU1000_TOY_INT = AU1500_FIRST_INT + 14,
610 AU1000_TOY_MATCH0_INT,
611 AU1000_TOY_MATCH1_INT,
612 AU1000_TOY_MATCH2_INT,
613 AU1000_RTC_INT,
614 AU1000_RTC_MATCH0_INT,
615 AU1000_RTC_MATCH1_INT,
616 AU1000_RTC_MATCH2_INT,
617 AU1500_PCI_ERR_INT,
618 AU1500_RESERVED_INT,
619 AU1000_USB_DEV_REQ_INT,
620 AU1000_USB_DEV_SUS_INT,
621 AU1000_USB_HOST_INT,
622 AU1000_ACSYNC_INT,
623 AU1500_MAC0_DMA_INT,
624 AU1500_MAC1_DMA_INT,
625 AU1000_AC97C_INT = AU1500_FIRST_INT + 31,
626 AU1000_GPIO_0,
627 AU1000_GPIO_1,
628 AU1000_GPIO_2,
629 AU1000_GPIO_3,
630 AU1000_GPIO_4,
631 AU1000_GPIO_5,
632 AU1000_GPIO_6,
633 AU1000_GPIO_7,
634 AU1000_GPIO_8,
635 AU1000_GPIO_9,
636 AU1000_GPIO_10,
637 AU1000_GPIO_11,
638 AU1000_GPIO_12,
639 AU1000_GPIO_13,
640 AU1000_GPIO_14,
641 AU1000_GPIO_15,
642 AU1500_GPIO_200,
643 AU1500_GPIO_201,
644 AU1500_GPIO_202,
645 AU1500_GPIO_203,
646 AU1500_GPIO_20,
647 AU1500_GPIO_204,
648 AU1500_GPIO_205,
649 AU1500_GPIO_23,
650 AU1500_GPIO_24,
651 AU1500_GPIO_25,
652 AU1500_GPIO_26,
653 AU1500_GPIO_27,
654 AU1500_GPIO_28,
655 AU1500_GPIO_206,
656 AU1500_GPIO_207,
657 AU1500_GPIO_208_215,
658};
659
660/* shortcuts */
661#define INTA AU1000_PCI_INTA
662#define INTB AU1000_PCI_INTB
663#define INTC AU1000_PCI_INTC
664#define INTD AU1000_PCI_INTD
665
666#define UART0_ADDR 0xB1100000
667#define UART3_ADDR 0xB1400000
668
669#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
670#define USB_HOST_CONFIG 0xB017fffc
671
672#define AU1500_ETH0_BASE 0xB1500000
673#define AU1500_ETH1_BASE 0xB1510000
674#define AU1500_MAC0_ENABLE 0xB1520000
675#define AU1500_MAC1_ENABLE 0xB1520004
676#define NUM_ETH_INTERFACES 2
677#endif /* CONFIG_SOC_AU1500 */
678
679/* Au1100 */
680#ifdef CONFIG_SOC_AU1100
681enum soc_au1100_ints {
682 AU1100_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
683 AU1100_UART0_INT,
684 AU1100_UART1_INT,
685 AU1100_SD_INT,
686 AU1100_UART3_INT,
687 AU1000_SSI0_INT,
688 AU1000_SSI1_INT,
689 AU1000_DMA_INT_BASE,
690
691 AU1000_TOY_INT = AU1100_FIRST_INT + 14,
692 AU1000_TOY_MATCH0_INT,
693 AU1000_TOY_MATCH1_INT,
694 AU1000_TOY_MATCH2_INT,
695 AU1000_RTC_INT,
696 AU1000_RTC_MATCH0_INT,
697 AU1000_RTC_MATCH1_INT,
698 AU1000_RTC_MATCH2_INT,
699 AU1000_IRDA_TX_INT,
700 AU1000_IRDA_RX_INT,
701 AU1000_USB_DEV_REQ_INT,
702 AU1000_USB_DEV_SUS_INT,
703 AU1000_USB_HOST_INT,
704 AU1000_ACSYNC_INT,
705 AU1100_MAC0_DMA_INT,
706 AU1100_GPIO_208_215,
707 AU1100_LCD_INT,
708 AU1000_AC97C_INT,
709 AU1000_GPIO_0,
710 AU1000_GPIO_1,
711 AU1000_GPIO_2,
712 AU1000_GPIO_3,
713 AU1000_GPIO_4,
714 AU1000_GPIO_5,
715 AU1000_GPIO_6,
716 AU1000_GPIO_7,
717 AU1000_GPIO_8,
718 AU1000_GPIO_9,
719 AU1000_GPIO_10,
720 AU1000_GPIO_11,
721 AU1000_GPIO_12,
722 AU1000_GPIO_13,
723 AU1000_GPIO_14,
724 AU1000_GPIO_15,
725 AU1000_GPIO_16,
726 AU1000_GPIO_17,
727 AU1000_GPIO_18,
728 AU1000_GPIO_19,
729 AU1000_GPIO_20,
730 AU1000_GPIO_21,
731 AU1000_GPIO_22,
732 AU1000_GPIO_23,
733 AU1000_GPIO_24,
734 AU1000_GPIO_25,
735 AU1000_GPIO_26,
736 AU1000_GPIO_27,
737 AU1000_GPIO_28,
738 AU1000_GPIO_29,
739 AU1000_GPIO_30,
740 AU1000_GPIO_31,
741};
742
743#define UART0_ADDR 0xB1100000
744#define UART1_ADDR 0xB1200000
745#define UART3_ADDR 0xB1400000
746
747#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
748#define USB_HOST_CONFIG 0xB017FFFC
749
750#define AU1100_ETH0_BASE 0xB0500000
751#define AU1100_MAC0_ENABLE 0xB0520000
752#define NUM_ETH_INTERFACES 1
753#endif /* CONFIG_SOC_AU1100 */
754
755#ifdef CONFIG_SOC_AU1550
756enum soc_au1550_ints {
757 AU1550_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
758 AU1550_UART0_INT = AU1550_FIRST_INT,
759 AU1550_PCI_INTA,
760 AU1550_PCI_INTB,
761 AU1550_DDMA_INT,
762 AU1550_CRYPTO_INT,
763 AU1550_PCI_INTC,
764 AU1550_PCI_INTD,
765 AU1550_PCI_RST_INT,
766 AU1550_UART1_INT,
767 AU1550_UART3_INT,
768 AU1550_PSC0_INT,
769 AU1550_PSC1_INT,
770 AU1550_PSC2_INT,
771 AU1550_PSC3_INT,
772 AU1000_TOY_INT,
773 AU1000_TOY_MATCH0_INT,
774 AU1000_TOY_MATCH1_INT,
775 AU1000_TOY_MATCH2_INT,
776 AU1000_RTC_INT,
777 AU1000_RTC_MATCH0_INT,
778 AU1000_RTC_MATCH1_INT,
779 AU1000_RTC_MATCH2_INT,
780
781 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
782 AU1550_USB_DEV_REQ_INT,
783 AU1000_USB_DEV_REQ_INT = AU1550_USB_DEV_REQ_INT,
784 AU1550_USB_DEV_SUS_INT,
785 AU1000_USB_DEV_SUS_INT = AU1550_USB_DEV_SUS_INT,
786 AU1550_USB_HOST_INT,
787 AU1000_USB_HOST_INT = AU1550_USB_HOST_INT,
788 AU1550_MAC0_DMA_INT,
789 AU1550_MAC1_DMA_INT,
790 AU1000_GPIO_0 = AU1550_FIRST_INT + 32,
791 AU1000_GPIO_1,
792 AU1000_GPIO_2,
793 AU1000_GPIO_3,
794 AU1000_GPIO_4,
795 AU1000_GPIO_5,
796 AU1000_GPIO_6,
797 AU1000_GPIO_7,
798 AU1000_GPIO_8,
799 AU1000_GPIO_9,
800 AU1000_GPIO_10,
801 AU1000_GPIO_11,
802 AU1000_GPIO_12,
803 AU1000_GPIO_13,
804 AU1000_GPIO_14,
805 AU1000_GPIO_15,
806 AU1550_GPIO_200,
807 AU1500_GPIO_201_205, /* Logical or of GPIO201:205 */
808 AU1500_GPIO_16,
809 AU1500_GPIO_17,
810 AU1500_GPIO_20,
811 AU1500_GPIO_21,
812 AU1500_GPIO_22,
813 AU1500_GPIO_23,
814 AU1500_GPIO_24,
815 AU1500_GPIO_25,
816 AU1500_GPIO_26,
817 AU1500_GPIO_27,
818 AU1500_GPIO_28,
819 AU1500_GPIO_206,
820 AU1500_GPIO_207,
821 AU1500_GPIO_208_218, /* Logical or of GPIO208:218 */
822};
823
824/* shortcuts */
825#define INTA AU1550_PCI_INTA
826#define INTB AU1550_PCI_INTB
827#define INTC AU1550_PCI_INTC
828#define INTD AU1550_PCI_INTD
829
830#define UART0_ADDR 0xB1100000
831#define UART1_ADDR 0xB1200000
832#define UART3_ADDR 0xB1400000
833
834#define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
835#define USB_OHCI_LEN 0x00060000
836#define USB_HOST_CONFIG 0xB4027ffc
837
838#define AU1550_ETH0_BASE 0xB0500000
839#define AU1550_ETH1_BASE 0xB0510000
840#define AU1550_MAC0_ENABLE 0xB0520000
841#define AU1550_MAC1_ENABLE 0xB0520004
842#define NUM_ETH_INTERFACES 2
843#endif /* CONFIG_SOC_AU1550 */
844
845#ifdef CONFIG_SOC_AU1200
846enum soc_au1200_ints {
847 AU1200_FIRST_INT = MIPS_CPU_IRQ_BASE + 8,
848 AU1200_UART0_INT = AU1200_FIRST_INT,
849 AU1200_SWT_INT,
850 AU1200_SD_INT,
851 AU1200_DDMA_INT,
852 AU1200_MAE_BE_INT,
853 AU1200_GPIO_200,
854 AU1200_GPIO_201,
855 AU1200_GPIO_202,
856 AU1200_UART1_INT,
857 AU1200_MAE_FE_INT,
858 AU1200_PSC0_INT,
859 AU1200_PSC1_INT,
860 AU1200_AES_INT,
861 AU1200_CAMERA_INT,
862 AU1000_TOY_INT,
863 AU1000_TOY_MATCH0_INT,
864 AU1000_TOY_MATCH1_INT,
865 AU1000_TOY_MATCH2_INT,
866 AU1000_RTC_INT,
867 AU1000_RTC_MATCH0_INT,
868 AU1000_RTC_MATCH1_INT,
869 AU1000_RTC_MATCH2_INT,
870
871 AU1200_NAND_INT = AU1200_FIRST_INT + 23,
872 AU1200_GPIO_204,
873 AU1200_GPIO_205,
874 AU1200_GPIO_206,
875 AU1200_GPIO_207,
876 AU1200_GPIO_208_215, /* Logical OR of 208:215 */
877 AU1200_USB_INT,
878 AU1000_USB_HOST_INT = AU1200_USB_INT,
879 AU1200_LCD_INT,
880 AU1200_MAE_BOTH_INT,
881 AU1000_GPIO_0,
882 AU1000_GPIO_1,
883 AU1000_GPIO_2,
884 AU1000_GPIO_3,
885 AU1000_GPIO_4,
886 AU1000_GPIO_5,
887 AU1000_GPIO_6,
888 AU1000_GPIO_7,
889 AU1000_GPIO_8,
890 AU1000_GPIO_9,
891 AU1000_GPIO_10,
892 AU1000_GPIO_11,
893 AU1000_GPIO_12,
894 AU1000_GPIO_13,
895 AU1000_GPIO_14,
896 AU1000_GPIO_15,
897 AU1000_GPIO_16,
898 AU1000_GPIO_17,
899 AU1000_GPIO_18,
900 AU1000_GPIO_19,
901 AU1000_GPIO_20,
902 AU1000_GPIO_21,
903 AU1000_GPIO_22,
904 AU1000_GPIO_23,
905 AU1000_GPIO_24,
906 AU1000_GPIO_25,
907 AU1000_GPIO_26,
908 AU1000_GPIO_27,
909 AU1000_GPIO_28,
910 AU1000_GPIO_29,
911 AU1000_GPIO_30,
912 AU1000_GPIO_31,
913};
914
915#define UART0_ADDR 0xB1100000
916#define UART1_ADDR 0xB1200000
917
918#define USB_UOC_BASE 0x14020020
919#define USB_UOC_LEN 0x20
920#define USB_OHCI_BASE 0x14020100
921#define USB_OHCI_LEN 0x100
922#define USB_EHCI_BASE 0x14020200
923#define USB_EHCI_LEN 0x100
924#define USB_UDC_BASE 0x14022000
925#define USB_UDC_LEN 0x2000
926#define USB_MSR_BASE 0xB4020000
927#define USB_MSR_MCFG 4
928#define USBMSRMCFG_OMEMEN 0
929#define USBMSRMCFG_OBMEN 1
930#define USBMSRMCFG_EMEMEN 2
931#define USBMSRMCFG_EBMEN 3
932#define USBMSRMCFG_DMEMEN 4
933#define USBMSRMCFG_DBMEN 5
934#define USBMSRMCFG_GMEMEN 6
935#define USBMSRMCFG_OHCCLKEN 16
936#define USBMSRMCFG_EHCCLKEN 17
937#define USBMSRMCFG_UDCCLKEN 18
938#define USBMSRMCFG_PHYPLLEN 19
939#define USBMSRMCFG_RDCOMB 30
940#define USBMSRMCFG_PFEN 31
941
942#endif /* CONFIG_SOC_AU1200 */
943
944#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
945#define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
946#define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_BASE + 32)
947#define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
948
949#define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
950#define INTX 0xFF /* not valid */
951
952/* Programmable Counters 0 and 1 */
953#define SYS_BASE 0xB1900000
954#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
955# define SYS_CNTRL_E1S (1 << 23)
956# define SYS_CNTRL_T1S (1 << 20)
957# define SYS_CNTRL_M21 (1 << 19)
958# define SYS_CNTRL_M11 (1 << 18)
959# define SYS_CNTRL_M01 (1 << 17)
960# define SYS_CNTRL_C1S (1 << 16)
961# define SYS_CNTRL_BP (1 << 14)
962# define SYS_CNTRL_EN1 (1 << 13)
963# define SYS_CNTRL_BT1 (1 << 12)
964# define SYS_CNTRL_EN0 (1 << 11)
965# define SYS_CNTRL_BT0 (1 << 10)
966# define SYS_CNTRL_E0 (1 << 8)
967# define SYS_CNTRL_E0S (1 << 7)
968# define SYS_CNTRL_32S (1 << 5)
969# define SYS_CNTRL_T0S (1 << 4)
970# define SYS_CNTRL_M20 (1 << 3)
971# define SYS_CNTRL_M10 (1 << 2)
972# define SYS_CNTRL_M00 (1 << 1)
973# define SYS_CNTRL_C0S (1 << 0)
974
975/* Programmable Counter 0 Registers */
976#define SYS_TOYTRIM (SYS_BASE + 0)
977#define SYS_TOYWRITE (SYS_BASE + 4)
978#define SYS_TOYMATCH0 (SYS_BASE + 8)
979#define SYS_TOYMATCH1 (SYS_BASE + 0xC)
980#define SYS_TOYMATCH2 (SYS_BASE + 0x10)
981#define SYS_TOYREAD (SYS_BASE + 0x40)
982
983/* Programmable Counter 1 Registers */
984#define SYS_RTCTRIM (SYS_BASE + 0x44)
985#define SYS_RTCWRITE (SYS_BASE + 0x48)
986#define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
987#define SYS_RTCMATCH1 (SYS_BASE + 0x50)
988#define SYS_RTCMATCH2 (SYS_BASE + 0x54)
989#define SYS_RTCREAD (SYS_BASE + 0x58)
990
991/* I2S Controller */
992#define I2S_DATA 0xB1000000
993# define I2S_DATA_MASK 0xffffff
994#define I2S_CONFIG 0xB1000004
995# define I2S_CONFIG_XU (1 << 25)
996# define I2S_CONFIG_XO (1 << 24)
997# define I2S_CONFIG_RU (1 << 23)
998# define I2S_CONFIG_RO (1 << 22)
999# define I2S_CONFIG_TR (1 << 21)
1000# define I2S_CONFIG_TE (1 << 20)
1001# define I2S_CONFIG_TF (1 << 19)
1002# define I2S_CONFIG_RR (1 << 18)
1003# define I2S_CONFIG_RE (1 << 17)
1004# define I2S_CONFIG_RF (1 << 16)
1005# define I2S_CONFIG_PD (1 << 11)
1006# define I2S_CONFIG_LB (1 << 10)
1007# define I2S_CONFIG_IC (1 << 9)
1008# define I2S_CONFIG_FM_BIT 7
1009# define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1010# define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1011# define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1012# define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1013# define I2S_CONFIG_TN (1 << 6)
1014# define I2S_CONFIG_RN (1 << 5)
1015# define I2S_CONFIG_SZ_BIT 0
1016# define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1017
1018#define I2S_CONTROL 0xB1000008
1019# define I2S_CONTROL_D (1 << 1)
1020# define I2S_CONTROL_CE (1 << 0)
1021
1022/* USB Host Controller */
1023#ifndef USB_OHCI_LEN
1024#define USB_OHCI_LEN 0x00100000
1025#endif
1026
1027#ifndef CONFIG_SOC_AU1200
1028
1029/* USB Device Controller */
1030#define USBD_EP0RD 0xB0200000
1031#define USBD_EP0WR 0xB0200004
1032#define USBD_EP2WR 0xB0200008
1033#define USBD_EP3WR 0xB020000C
1034#define USBD_EP4RD 0xB0200010
1035#define USBD_EP5RD 0xB0200014
1036#define USBD_INTEN 0xB0200018
1037#define USBD_INTSTAT 0xB020001C
1038# define USBDEV_INT_SOF (1 << 12)
1039# define USBDEV_INT_HF_BIT 6
1040# define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1041# define USBDEV_INT_CMPLT_BIT 0
1042# define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1043#define USBD_CONFIG 0xB0200020
1044#define USBD_EP0CS 0xB0200024
1045#define USBD_EP2CS 0xB0200028
1046#define USBD_EP3CS 0xB020002C
1047#define USBD_EP4CS 0xB0200030
1048#define USBD_EP5CS 0xB0200034
1049# define USBDEV_CS_SU (1 << 14)
1050# define USBDEV_CS_NAK (1 << 13)
1051# define USBDEV_CS_ACK (1 << 12)
1052# define USBDEV_CS_BUSY (1 << 11)
1053# define USBDEV_CS_TSIZE_BIT 1
1054# define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1055# define USBDEV_CS_STALL (1 << 0)
1056#define USBD_EP0RDSTAT 0xB0200040
1057#define USBD_EP0WRSTAT 0xB0200044
1058#define USBD_EP2WRSTAT 0xB0200048
1059#define USBD_EP3WRSTAT 0xB020004C
1060#define USBD_EP4RDSTAT 0xB0200050
1061#define USBD_EP5RDSTAT 0xB0200054
1062# define USBDEV_FSTAT_FLUSH (1 << 6)
1063# define USBDEV_FSTAT_UF (1 << 5)
1064# define USBDEV_FSTAT_OF (1 << 4)
1065# define USBDEV_FSTAT_FCNT_BIT 0
1066# define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1067#define USBD_ENABLE 0xB0200058
1068# define USBDEV_ENABLE (1 << 1)
1069# define USBDEV_CE (1 << 0)
1070
1071#endif /* !CONFIG_SOC_AU1200 */
1072
1073/* Ethernet Controllers */
1074
1075/* 4 byte offsets from AU1000_ETH_BASE */
1076#define MAC_CONTROL 0x0
1077# define MAC_RX_ENABLE (1 << 2)
1078# define MAC_TX_ENABLE (1 << 3)
1079# define MAC_DEF_CHECK (1 << 5)
1080# define MAC_SET_BL(X) (((X) & 0x3) << 6)
1081# define MAC_AUTO_PAD (1 << 8)
1082# define MAC_DISABLE_RETRY (1 << 10)
1083# define MAC_DISABLE_BCAST (1 << 11)
1084# define MAC_LATE_COL (1 << 12)
1085# define MAC_HASH_MODE (1 << 13)
1086# define MAC_HASH_ONLY (1 << 15)
1087# define MAC_PASS_ALL (1 << 16)
1088# define MAC_INVERSE_FILTER (1 << 17)
1089# define MAC_PROMISCUOUS (1 << 18)
1090# define MAC_PASS_ALL_MULTI (1 << 19)
1091# define MAC_FULL_DUPLEX (1 << 20)
1092# define MAC_NORMAL_MODE 0
1093# define MAC_INT_LOOPBACK (1 << 21)
1094# define MAC_EXT_LOOPBACK (1 << 22)
1095# define MAC_DISABLE_RX_OWN (1 << 23)
1096# define MAC_BIG_ENDIAN (1 << 30)
1097# define MAC_RX_ALL (1 << 31)
1098#define MAC_ADDRESS_HIGH 0x4
1099#define MAC_ADDRESS_LOW 0x8
1100#define MAC_MCAST_HIGH 0xC
1101#define MAC_MCAST_LOW 0x10
1102#define MAC_MII_CNTRL 0x14
1103# define MAC_MII_BUSY (1 << 0)
1104# define MAC_MII_READ 0
1105# define MAC_MII_WRITE (1 << 1)
1106# define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1107# define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1108#define MAC_MII_DATA 0x18
1109#define MAC_FLOW_CNTRL 0x1C
1110# define MAC_FLOW_CNTRL_BUSY (1 << 0)
1111# define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1112# define MAC_PASS_CONTROL (1 << 2)
1113# define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1114#define MAC_VLAN1_TAG 0x20
1115#define MAC_VLAN2_TAG 0x24
1116
1117/* Ethernet Controller Enable */
1118
1119# define MAC_EN_CLOCK_ENABLE (1 << 0)
1120# define MAC_EN_RESET0 (1 << 1)
1121# define MAC_EN_TOSS (0 << 2)
1122# define MAC_EN_CACHEABLE (1 << 3)
1123# define MAC_EN_RESET1 (1 << 4)
1124# define MAC_EN_RESET2 (1 << 5)
1125# define MAC_DMA_RESET (1 << 6)
1126
1127/* Ethernet Controller DMA Channels */
1128
1129#define MAC0_TX_DMA_ADDR 0xB4004000
1130#define MAC1_TX_DMA_ADDR 0xB4004200
1131/* offsets from MAC_TX_RING_ADDR address */
1132#define MAC_TX_BUFF0_STATUS 0x0
1133# define TX_FRAME_ABORTED (1 << 0)
1134# define TX_JAB_TIMEOUT (1 << 1)
1135# define TX_NO_CARRIER (1 << 2)
1136# define TX_LOSS_CARRIER (1 << 3)
1137# define TX_EXC_DEF (1 << 4)
1138# define TX_LATE_COLL_ABORT (1 << 5)
1139# define TX_EXC_COLL (1 << 6)
1140# define TX_UNDERRUN (1 << 7)
1141# define TX_DEFERRED (1 << 8)
1142# define TX_LATE_COLL (1 << 9)
1143# define TX_COLL_CNT_MASK (0xF << 10)
1144# define TX_PKT_RETRY (1 << 31)
1145#define MAC_TX_BUFF0_ADDR 0x4
1146# define TX_DMA_ENABLE (1 << 0)
1147# define TX_T_DONE (1 << 1)
1148# define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1149#define MAC_TX_BUFF0_LEN 0x8
1150#define MAC_TX_BUFF1_STATUS 0x10
1151#define MAC_TX_BUFF1_ADDR 0x14
1152#define MAC_TX_BUFF1_LEN 0x18
1153#define MAC_TX_BUFF2_STATUS 0x20
1154#define MAC_TX_BUFF2_ADDR 0x24
1155#define MAC_TX_BUFF2_LEN 0x28
1156#define MAC_TX_BUFF3_STATUS 0x30
1157#define MAC_TX_BUFF3_ADDR 0x34
1158#define MAC_TX_BUFF3_LEN 0x38
1159
1160#define MAC0_RX_DMA_ADDR 0xB4004100
1161#define MAC1_RX_DMA_ADDR 0xB4004300
1162/* offsets from MAC_RX_RING_ADDR */
1163#define MAC_RX_BUFF0_STATUS 0x0
1164# define RX_FRAME_LEN_MASK 0x3fff
1165# define RX_WDOG_TIMER (1 << 14)
1166# define RX_RUNT (1 << 15)
1167# define RX_OVERLEN (1 << 16)
1168# define RX_COLL (1 << 17)
1169# define RX_ETHER (1 << 18)
1170# define RX_MII_ERROR (1 << 19)
1171# define RX_DRIBBLING (1 << 20)
1172# define RX_CRC_ERROR (1 << 21)
1173# define RX_VLAN1 (1 << 22)
1174# define RX_VLAN2 (1 << 23)
1175# define RX_LEN_ERROR (1 << 24)
1176# define RX_CNTRL_FRAME (1 << 25)
1177# define RX_U_CNTRL_FRAME (1 << 26)
1178# define RX_MCAST_FRAME (1 << 27)
1179# define RX_BCAST_FRAME (1 << 28)
1180# define RX_FILTER_FAIL (1 << 29)
1181# define RX_PACKET_FILTER (1 << 30)
1182# define RX_MISSED_FRAME (1 << 31)
1183
1184# define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1185 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1186 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1187#define MAC_RX_BUFF0_ADDR 0x4
1188# define RX_DMA_ENABLE (1 << 0)
1189# define RX_T_DONE (1 << 1)
1190# define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1191# define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1192#define MAC_RX_BUFF1_STATUS 0x10
1193#define MAC_RX_BUFF1_ADDR 0x14
1194#define MAC_RX_BUFF2_STATUS 0x20
1195#define MAC_RX_BUFF2_ADDR 0x24
1196#define MAC_RX_BUFF3_STATUS 0x30
1197#define MAC_RX_BUFF3_ADDR 0x34
1198
1199/* UARTS 0-3 */
1200#define UART_BASE UART0_ADDR
1201#ifdef CONFIG_SOC_AU1200
1202#define UART_DEBUG_BASE UART1_ADDR
1203#else
1204#define UART_DEBUG_BASE UART3_ADDR
1205#endif
1206
1207#define UART_RX 0 /* Receive buffer */
1208#define UART_TX 4 /* Transmit buffer */
1209#define UART_IER 8 /* Interrupt Enable Register */
1210#define UART_IIR 0xC /* Interrupt ID Register */
1211#define UART_FCR 0x10 /* FIFO Control Register */
1212#define UART_LCR 0x14 /* Line Control Register */
1213#define UART_MCR 0x18 /* Modem Control Register */
1214#define UART_LSR 0x1C /* Line Status Register */
1215#define UART_MSR 0x20 /* Modem Status Register */
1216#define UART_CLK 0x28 /* Baud Rate Clock Divider */
1217#define UART_MOD_CNTRL 0x100 /* Module Control */
1218
1219#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1220#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1221#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1222#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1223#define UART_FCR_TRIGGER_MASK 0xF0 /* Mask for the FIFO trigger range */
1224#define UART_FCR_R_TRIGGER_1 0x00 /* Mask for receive trigger set at 1 */
1225#define UART_FCR_R_TRIGGER_4 0x40 /* Mask for receive trigger set at 4 */
1226#define UART_FCR_R_TRIGGER_8 0x80 /* Mask for receive trigger set at 8 */
1227#define UART_FCR_R_TRIGGER_14 0xA0 /* Mask for receive trigger set at 14 */
1228#define UART_FCR_T_TRIGGER_0 0x00 /* Mask for transmit trigger set at 0 */
1229#define UART_FCR_T_TRIGGER_4 0x10 /* Mask for transmit trigger set at 4 */
1230#define UART_FCR_T_TRIGGER_8 0x20 /* Mask for transmit trigger set at 8 */
1231#define UART_FCR_T_TRIGGER_12 0x30 /* Mask for transmit trigger set at 12 */
1232
1233/*
1234 * These are the definitions for the Line Control Register
1235 */
1236#define UART_LCR_SBC 0x40 /* Set break control */
1237#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1238#define UART_LCR_EPAR 0x10 /* Even parity select */
1239#define UART_LCR_PARITY 0x08 /* Parity Enable */
1240#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
1241#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1242#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1243#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1244#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1245
1246/*
1247 * These are the definitions for the Line Status Register
1248 */
1249#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1250#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1251#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1252#define UART_LSR_FE 0x08 /* Frame error indicator */
1253#define UART_LSR_PE 0x04 /* Parity error indicator */
1254#define UART_LSR_OE 0x02 /* Overrun error indicator */
1255#define UART_LSR_DR 0x01 /* Receiver data ready */
1256
1257/*
1258 * These are the definitions for the Interrupt Identification Register
1259 */
1260#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1261#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1262#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1263#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1264#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1265#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1266
1267/*
1268 * These are the definitions for the Interrupt Enable Register
1269 */
1270#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1271#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1272#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1273#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1274
1275/*
1276 * These are the definitions for the Modem Control Register
1277 */
1278#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1279#define UART_MCR_OUT2 0x08 /* Out2 complement */
1280#define UART_MCR_OUT1 0x04 /* Out1 complement */
1281#define UART_MCR_RTS 0x02 /* RTS complement */
1282#define UART_MCR_DTR 0x01 /* DTR complement */
1283
1284/*
1285 * These are the definitions for the Modem Status Register
1286 */
1287#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1288#define UART_MSR_RI 0x40 /* Ring Indicator */
1289#define UART_MSR_DSR 0x20 /* Data Set Ready */
1290#define UART_MSR_CTS 0x10 /* Clear to Send */
1291#define UART_MSR_DDCD 0x08 /* Delta DCD */
1292#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1293#define UART_MSR_DDSR 0x02 /* Delta DSR */
1294#define UART_MSR_DCTS 0x01 /* Delta CTS */
1295#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1296
1297/* SSIO */
1298#define SSI0_STATUS 0xB1600000
1299# define SSI_STATUS_BF (1 << 4)
1300# define SSI_STATUS_OF (1 << 3)
1301# define SSI_STATUS_UF (1 << 2)
1302# define SSI_STATUS_D (1 << 1)
1303# define SSI_STATUS_B (1 << 0)
1304#define SSI0_INT 0xB1600004
1305# define SSI_INT_OI (1 << 3)
1306# define SSI_INT_UI (1 << 2)
1307# define SSI_INT_DI (1 << 1)
1308#define SSI0_INT_ENABLE 0xB1600008
1309# define SSI_INTE_OIE (1 << 3)
1310# define SSI_INTE_UIE (1 << 2)
1311# define SSI_INTE_DIE (1 << 1)
1312#define SSI0_CONFIG 0xB1600020
1313# define SSI_CONFIG_AO (1 << 24)
1314# define SSI_CONFIG_DO (1 << 23)
1315# define SSI_CONFIG_ALEN_BIT 20
1316# define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1317# define SSI_CONFIG_DLEN_BIT 16
1318# define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1319# define SSI_CONFIG_DD (1 << 11)
1320# define SSI_CONFIG_AD (1 << 10)
1321# define SSI_CONFIG_BM_BIT 8
1322# define SSI_CONFIG_BM_MASK (0x3 << 8)
1323# define SSI_CONFIG_CE (1 << 7)
1324# define SSI_CONFIG_DP (1 << 6)
1325# define SSI_CONFIG_DL (1 << 5)
1326# define SSI_CONFIG_EP (1 << 4)
1327#define SSI0_ADATA 0xB1600024
1328# define SSI_AD_D (1 << 24)
1329# define SSI_AD_ADDR_BIT 16
1330# define SSI_AD_ADDR_MASK (0xff << 16)
1331# define SSI_AD_DATA_BIT 0
1332# define SSI_AD_DATA_MASK (0xfff << 0)
1333#define SSI0_CLKDIV 0xB1600028
1334#define SSI0_CONTROL 0xB1600100
1335# define SSI_CONTROL_CD (1 << 1)
1336# define SSI_CONTROL_E (1 << 0)
1337
1338/* SSI1 */
1339#define SSI1_STATUS 0xB1680000
1340#define SSI1_INT 0xB1680004
1341#define SSI1_INT_ENABLE 0xB1680008
1342#define SSI1_CONFIG 0xB1680020
1343#define SSI1_ADATA 0xB1680024
1344#define SSI1_CLKDIV 0xB1680028
1345#define SSI1_ENABLE 0xB1680100
1346
1347/*
1348 * Register content definitions
1349 */
1350#define SSI_STATUS_BF (1 << 4)
1351#define SSI_STATUS_OF (1 << 3)
1352#define SSI_STATUS_UF (1 << 2)
1353#define SSI_STATUS_D (1 << 1)
1354#define SSI_STATUS_B (1 << 0)
1355
1356/* SSI_INT */
1357#define SSI_INT_OI (1 << 3)
1358#define SSI_INT_UI (1 << 2)
1359#define SSI_INT_DI (1 << 1)
1360
1361/* SSI_INTEN */
1362#define SSI_INTEN_OIE (1 << 3)
1363#define SSI_INTEN_UIE (1 << 2)
1364#define SSI_INTEN_DIE (1 << 1)
1365
1366#define SSI_CONFIG_AO (1 << 24)
1367#define SSI_CONFIG_DO (1 << 23)
1368#define SSI_CONFIG_ALEN (7 << 20)
1369#define SSI_CONFIG_DLEN (15 << 16)
1370#define SSI_CONFIG_DD (1 << 11)
1371#define SSI_CONFIG_AD (1 << 10)
1372#define SSI_CONFIG_BM (3 << 8)
1373#define SSI_CONFIG_CE (1 << 7)
1374#define SSI_CONFIG_DP (1 << 6)
1375#define SSI_CONFIG_DL (1 << 5)
1376#define SSI_CONFIG_EP (1 << 4)
1377#define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1378#define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1379#define SSI_CONFIG_BM_HI (0 << 8)
1380#define SSI_CONFIG_BM_LO (1 << 8)
1381#define SSI_CONFIG_BM_CY (2 << 8)
1382
1383#define SSI_ADATA_D (1 << 24)
1384#define SSI_ADATA_ADDR (0xFF << 16)
1385#define SSI_ADATA_DATA 0x0FFF
1386#define SSI_ADATA_ADDR_N(N) (N << 16)
1387
1388#define SSI_ENABLE_CD (1 << 1)
1389#define SSI_ENABLE_E (1 << 0)
1390
1391/* IrDA Controller */
1392#define IRDA_BASE 0xB0300000
1393#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1394#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1395#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1396#define IR_RING_SIZE (IRDA_BASE + 0x0C)
1397#define IR_RING_PROMPT (IRDA_BASE + 0x10)
1398#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1399#define IR_INT_CLEAR (IRDA_BASE + 0x18)
1400#define IR_CONFIG_1 (IRDA_BASE + 0x20)
1401# define IR_RX_INVERT_LED (1 << 0)
1402# define IR_TX_INVERT_LED (1 << 1)
1403# define IR_ST (1 << 2)
1404# define IR_SF (1 << 3)
1405# define IR_SIR (1 << 4)
1406# define IR_MIR (1 << 5)
1407# define IR_FIR (1 << 6)
1408# define IR_16CRC (1 << 7)
1409# define IR_TD (1 << 8)
1410# define IR_RX_ALL (1 << 9)
1411# define IR_DMA_ENABLE (1 << 10)
1412# define IR_RX_ENABLE (1 << 11)
1413# define IR_TX_ENABLE (1 << 12)
1414# define IR_LOOPBACK (1 << 14)
1415# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1416 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1417#define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1418#define IR_ENABLE (IRDA_BASE + 0x28)
1419# define IR_RX_STATUS (1 << 9)
1420# define IR_TX_STATUS (1 << 10)
1421#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1422#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1423#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1424#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1425#define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1426# define IR_MODE_INV (1 << 0)
1427# define IR_ONE_PIN (1 << 1)
1428#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1429
1430/* GPIO */
1431#define SYS_PINFUNC 0xB190002C
1432# define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1433# define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1434# define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1435# define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1436# define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1437# define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1438# define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1439# define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1440# define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1441# define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1442# define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1443# define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1444# define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1445# define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1446# define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1447# define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1448
1449/* Au1100 only */
1450# define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1451# define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1452# define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1453# define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1454
1455/* Au1550 only. Redefines lots of pins */
1456# define SYS_PF_PSC2_MASK (7 << 17)
1457# define SYS_PF_PSC2_AC97 0
1458# define SYS_PF_PSC2_SPI 0
1459# define SYS_PF_PSC2_I2S (1 << 17)
1460# define SYS_PF_PSC2_SMBUS (3 << 17)
1461# define SYS_PF_PSC2_GPIO (7 << 17)
1462# define SYS_PF_PSC3_MASK (7 << 20)
1463# define SYS_PF_PSC3_AC97 0
1464# define SYS_PF_PSC3_SPI 0
1465# define SYS_PF_PSC3_I2S (1 << 20)
1466# define SYS_PF_PSC3_SMBUS (3 << 20)
1467# define SYS_PF_PSC3_GPIO (7 << 20)
1468# define SYS_PF_PSC1_S1 (1 << 1)
1469# define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1470
1471/* Au1200 only */
1472#ifdef CONFIG_SOC_AU1200
1473#define SYS_PINFUNC_DMA (1 << 31)
1474#define SYS_PINFUNC_S0A (1 << 30)
1475#define SYS_PINFUNC_S1A (1 << 29)
1476#define SYS_PINFUNC_LP0 (1 << 28)
1477#define SYS_PINFUNC_LP1 (1 << 27)
1478#define SYS_PINFUNC_LD16 (1 << 26)
1479#define SYS_PINFUNC_LD8 (1 << 25)
1480#define SYS_PINFUNC_LD1 (1 << 24)
1481#define SYS_PINFUNC_LD0 (1 << 23)
1482#define SYS_PINFUNC_P1A (3 << 21)
1483#define SYS_PINFUNC_P1B (1 << 20)
1484#define SYS_PINFUNC_FS3 (1 << 19)
1485#define SYS_PINFUNC_P0A (3 << 17)
1486#define SYS_PINFUNC_CS (1 << 16)
1487#define SYS_PINFUNC_CIM (1 << 15)
1488#define SYS_PINFUNC_P1C (1 << 14)
1489#define SYS_PINFUNC_U1T (1 << 12)
1490#define SYS_PINFUNC_U1R (1 << 11)
1491#define SYS_PINFUNC_EX1 (1 << 10)
1492#define SYS_PINFUNC_EX0 (1 << 9)
1493#define SYS_PINFUNC_U0R (1 << 8)
1494#define SYS_PINFUNC_MC (1 << 7)
1495#define SYS_PINFUNC_S0B (1 << 6)
1496#define SYS_PINFUNC_S0C (1 << 5)
1497#define SYS_PINFUNC_P0B (1 << 4)
1498#define SYS_PINFUNC_U0T (1 << 3)
1499#define SYS_PINFUNC_S1B (1 << 2)
1500#endif
1501
1502#define SYS_TRIOUTRD 0xB1900100
1503#define SYS_TRIOUTCLR 0xB1900100
1504#define SYS_OUTPUTRD 0xB1900108
1505#define SYS_OUTPUTSET 0xB1900108
1506#define SYS_OUTPUTCLR 0xB190010C
1507#define SYS_PINSTATERD 0xB1900110
1508#define SYS_PININPUTEN 0xB1900110
1509
1510/* GPIO2, Au1500, Au1550 only */
1511#define GPIO2_BASE 0xB1700000
1512#define GPIO2_DIR (GPIO2_BASE + 0)
1513#define GPIO2_OUTPUT (GPIO2_BASE + 8)
1514#define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1515#define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1516#define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1517
1518/* Power Management */
1519#define SYS_SCRATCH0 0xB1900018
1520#define SYS_SCRATCH1 0xB190001C
1521#define SYS_WAKEMSK 0xB1900034
1522#define SYS_ENDIAN 0xB1900038
1523#define SYS_POWERCTRL 0xB190003C
1524#define SYS_WAKESRC 0xB190005C
1525#define SYS_SLPPWR 0xB1900078
1526#define SYS_SLEEP 0xB190007C
1527
1528/* Clock Controller */
1529#define SYS_FREQCTRL0 0xB1900020
1530# define SYS_FC_FRDIV2_BIT 22
1531# define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1532# define SYS_FC_FE2 (1 << 21)
1533# define SYS_FC_FS2 (1 << 20)
1534# define SYS_FC_FRDIV1_BIT 12
1535# define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1536# define SYS_FC_FE1 (1 << 11)
1537# define SYS_FC_FS1 (1 << 10)
1538# define SYS_FC_FRDIV0_BIT 2
1539# define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1540# define SYS_FC_FE0 (1 << 1)
1541# define SYS_FC_FS0 (1 << 0)
1542#define SYS_FREQCTRL1 0xB1900024
1543# define SYS_FC_FRDIV5_BIT 22
1544# define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1545# define SYS_FC_FE5 (1 << 21)
1546# define SYS_FC_FS5 (1 << 20)
1547# define SYS_FC_FRDIV4_BIT 12
1548# define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1549# define SYS_FC_FE4 (1 << 11)
1550# define SYS_FC_FS4 (1 << 10)
1551# define SYS_FC_FRDIV3_BIT 2
1552# define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1553# define SYS_FC_FE3 (1 << 1)
1554# define SYS_FC_FS3 (1 << 0)
1555#define SYS_CLKSRC 0xB1900028
1556# define SYS_CS_ME1_BIT 27
1557# define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1558# define SYS_CS_DE1 (1 << 26)
1559# define SYS_CS_CE1 (1 << 25)
1560# define SYS_CS_ME0_BIT 22
1561# define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1562# define SYS_CS_DE0 (1 << 21)
1563# define SYS_CS_CE0 (1 << 20)
1564# define SYS_CS_MI2_BIT 17
1565# define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1566# define SYS_CS_DI2 (1 << 16)
1567# define SYS_CS_CI2 (1 << 15)
1568#ifdef CONFIG_SOC_AU1100
1569# define SYS_CS_ML_BIT 7
1570# define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1571# define SYS_CS_DL (1 << 6)
1572# define SYS_CS_CL (1 << 5)
1573#else
1574# define SYS_CS_MUH_BIT 12
1575# define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1576# define SYS_CS_DUH (1 << 11)
1577# define SYS_CS_CUH (1 << 10)
1578# define SYS_CS_MUD_BIT 7
1579# define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1580# define SYS_CS_DUD (1 << 6)
1581# define SYS_CS_CUD (1 << 5)
1582#endif
1583# define SYS_CS_MIR_BIT 2
1584# define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1585# define SYS_CS_DIR (1 << 1)
1586# define SYS_CS_CIR (1 << 0)
1587
1588# define SYS_CS_MUX_AUX 0x1
1589# define SYS_CS_MUX_FQ0 0x2
1590# define SYS_CS_MUX_FQ1 0x3
1591# define SYS_CS_MUX_FQ2 0x4
1592# define SYS_CS_MUX_FQ3 0x5
1593# define SYS_CS_MUX_FQ4 0x6
1594# define SYS_CS_MUX_FQ5 0x7
1595#define SYS_CPUPLL 0xB1900060
1596#define SYS_AUXPLL 0xB1900064
1597
1598/* AC97 Controller */
1599#define AC97C_CONFIG 0xB0000000
1600# define AC97C_RECV_SLOTS_BIT 13
1601# define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1602# define AC97C_XMIT_SLOTS_BIT 3
1603# define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1604# define AC97C_SG (1 << 2)
1605# define AC97C_SYNC (1 << 1)
1606# define AC97C_RESET (1 << 0)
1607#define AC97C_STATUS 0xB0000004
1608# define AC97C_XU (1 << 11)
1609# define AC97C_XO (1 << 10)
1610# define AC97C_RU (1 << 9)
1611# define AC97C_RO (1 << 8)
1612# define AC97C_READY (1 << 7)
1613# define AC97C_CP (1 << 6)
1614# define AC97C_TR (1 << 5)
1615# define AC97C_TE (1 << 4)
1616# define AC97C_TF (1 << 3)
1617# define AC97C_RR (1 << 2)
1618# define AC97C_RE (1 << 1)
1619# define AC97C_RF (1 << 0)
1620#define AC97C_DATA 0xB0000008
1621#define AC97C_CMD 0xB000000C
1622# define AC97C_WD_BIT 16
1623# define AC97C_READ (1 << 7)
1624# define AC97C_INDEX_MASK 0x7f
1625#define AC97C_CNTRL 0xB0000010
1626# define AC97C_RS (1 << 1)
1627# define AC97C_CE (1 << 0)
1628
1629/* Secure Digital (SD) Controller */
1630#define SD0_XMIT_FIFO 0xB0600000
1631#define SD0_RECV_FIFO 0xB0600004
1632#define SD1_XMIT_FIFO 0xB0680000
1633#define SD1_RECV_FIFO 0xB0680004
1634
1635#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1636/* Au1500 PCI Controller */
1637#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1638#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1639#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1640# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1641 (1 << 25) | (1 << 26) | (1 << 27))
1642#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1643#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1644#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1645#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1646#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1647#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1648#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1649#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1650#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1651#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1652#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1653#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1654
1655#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1656
1657/*
1658 * All of our structures, like PCI resource, have 32-bit members.
1659 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1660 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1661 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1662 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1663 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1664 * ourselves and then adjust the device's resources.
1665 */
1666#define Au1500_EXT_CFG 0x600000000ULL
1667#define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1668#define Au1500_PCI_IO_START 0x500000000ULL
1669#define Au1500_PCI_IO_END 0x5000FFFFFULL
1670#define Au1500_PCI_MEM_START 0x440000000ULL
1671#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1672
1673#define PCI_IO_START 0x00001000
1674#define PCI_IO_END 0x000FFFFF
1675#define PCI_MEM_START 0x40000000
1676#define PCI_MEM_END 0x4FFFFFFF
1677
1678#define PCI_FIRST_DEVFN (0 << 3)
1679#define PCI_LAST_DEVFN (19 << 3)
1680
1681#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1682#define IOPORT_RESOURCE_END 0xffffffff
1683#define IOMEM_RESOURCE_START 0x10000000
1684#define IOMEM_RESOURCE_END 0xffffffff
1685
1686#else /* Au1000 and Au1100 and Au1200 */
1687
1688/* Don't allow any legacy ports probing */
1689#define IOPORT_RESOURCE_START 0x10000000
1690#define IOPORT_RESOURCE_END 0xffffffff
1691#define IOMEM_RESOURCE_START 0x10000000
1692#define IOMEM_RESOURCE_END 0xffffffff
1693
1694#define PCI_IO_START 0
1695#define PCI_IO_END 0
1696#define PCI_MEM_START 0
1697#define PCI_MEM_END 0
1698#define PCI_FIRST_DEVFN 0
1699#define PCI_LAST_DEVFN 0
1700
1701#endif
1702
1703#ifndef _LANGUAGE_ASSEMBLY
1704typedef volatile struct {
1705 /* 0x0000 */ u32 toytrim;
1706 /* 0x0004 */ u32 toywrite;
1707 /* 0x0008 */ u32 toymatch0;
1708 /* 0x000C */ u32 toymatch1;
1709 /* 0x0010 */ u32 toymatch2;
1710 /* 0x0014 */ u32 cntrctrl;
1711 /* 0x0018 */ u32 scratch0;
1712 /* 0x001C */ u32 scratch1;
1713 /* 0x0020 */ u32 freqctrl0;
1714 /* 0x0024 */ u32 freqctrl1;
1715 /* 0x0028 */ u32 clksrc;
1716 /* 0x002C */ u32 pinfunc;
1717 /* 0x0030 */ u32 reserved0;
1718 /* 0x0034 */ u32 wakemsk;
1719 /* 0x0038 */ u32 endian;
1720 /* 0x003C */ u32 powerctrl;
1721 /* 0x0040 */ u32 toyread;
1722 /* 0x0044 */ u32 rtctrim;
1723 /* 0x0048 */ u32 rtcwrite;
1724 /* 0x004C */ u32 rtcmatch0;
1725 /* 0x0050 */ u32 rtcmatch1;
1726 /* 0x0054 */ u32 rtcmatch2;
1727 /* 0x0058 */ u32 rtcread;
1728 /* 0x005C */ u32 wakesrc;
1729 /* 0x0060 */ u32 cpupll;
1730 /* 0x0064 */ u32 auxpll;
1731 /* 0x0068 */ u32 reserved1;
1732 /* 0x006C */ u32 reserved2;
1733 /* 0x0070 */ u32 reserved3;
1734 /* 0x0074 */ u32 reserved4;
1735 /* 0x0078 */ u32 slppwr;
1736 /* 0x007C */ u32 sleep;
1737 /* 0x0080 */ u32 reserved5[32];
1738 /* 0x0100 */ u32 trioutrd;
1739#define trioutclr trioutrd
1740 /* 0x0104 */ u32 reserved6;
1741 /* 0x0108 */ u32 outputrd;
1742#define outputset outputrd
1743 /* 0x010C */ u32 outputclr;
1744 /* 0x0110 */ u32 pinstaterd;
1745#define pininputen pinstaterd
1746} AU1X00_SYS;
1747
1748static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
1749
1750#endif
1751
1752/*
1753 * Processor information based on PRID.
1754 * Copied from PowerPC.
1755 */
1756#ifndef _LANGUAGE_ASSEMBLY
1757struct cpu_spec {
1758 /* CPU is matched via (PRID & prid_mask) == prid_value */
1759 unsigned int prid_mask;
1760 unsigned int prid_value;
1761
1762 char *cpu_name;
1763 unsigned char cpu_od; /* Set Config[OD] */
1764 unsigned char cpu_bclk; /* Enable BCLK switching */
1765 unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */
1766};
1767
1768extern struct cpu_spec cpu_specs[];
1769extern struct cpu_spec *cur_cpu_spec[];
1770#endif
1771
1772#endif
diff --git a/include/asm-mips/mach-au1x00/au1000_dma.h b/include/asm-mips/mach-au1x00/au1000_dma.h
deleted file mode 100644
index c333b4e1cd44..000000000000
--- a/include/asm-mips/mach-au1x00/au1000_dma.h
+++ /dev/null
@@ -1,458 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Defines for using and allocating DMA channels on the Alchemy
4 * Au1x00 MIPS processors.
5 *
6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 */
30#ifndef __ASM_AU1000_DMA_H
31#define __ASM_AU1000_DMA_H
32
33#include <linux/io.h> /* need byte IO */
34#include <linux/spinlock.h> /* And spinlocks */
35#include <linux/delay.h>
36#include <asm/system.h>
37
38#define NUM_AU1000_DMA_CHANNELS 8
39
40/* DMA Channel Base Addresses */
41#define DMA_CHANNEL_BASE 0xB4002000
42#define DMA_CHANNEL_LEN 0x00000100
43
44/* DMA Channel Register Offsets */
45#define DMA_MODE_SET 0x00000000
46#define DMA_MODE_READ DMA_MODE_SET
47#define DMA_MODE_CLEAR 0x00000004
48/* DMA Mode register bits follow */
49#define DMA_DAH_MASK (0x0f << 20)
50#define DMA_DID_BIT 16
51#define DMA_DID_MASK (0x0f << DMA_DID_BIT)
52#define DMA_DS (1 << 15)
53#define DMA_BE (1 << 13)
54#define DMA_DR (1 << 12)
55#define DMA_TS8 (1 << 11)
56#define DMA_DW_BIT 9
57#define DMA_DW_MASK (0x03 << DMA_DW_BIT)
58#define DMA_DW8 (0 << DMA_DW_BIT)
59#define DMA_DW16 (1 << DMA_DW_BIT)
60#define DMA_DW32 (2 << DMA_DW_BIT)
61#define DMA_NC (1 << 8)
62#define DMA_IE (1 << 7)
63#define DMA_HALT (1 << 6)
64#define DMA_GO (1 << 5)
65#define DMA_AB (1 << 4)
66#define DMA_D1 (1 << 3)
67#define DMA_BE1 (1 << 2)
68#define DMA_D0 (1 << 1)
69#define DMA_BE0 (1 << 0)
70
71#define DMA_PERIPHERAL_ADDR 0x00000008
72#define DMA_BUFFER0_START 0x0000000C
73#define DMA_BUFFER1_START 0x00000014
74#define DMA_BUFFER0_COUNT 0x00000010
75#define DMA_BUFFER1_COUNT 0x00000018
76#define DMA_BAH_BIT 16
77#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
78#define DMA_COUNT_BIT 0
79#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
80
81/* DMA Device IDs follow */
82enum {
83 DMA_ID_UART0_TX = 0,
84 DMA_ID_UART0_RX,
85 DMA_ID_GP04,
86 DMA_ID_GP05,
87 DMA_ID_AC97C_TX,
88 DMA_ID_AC97C_RX,
89 DMA_ID_UART3_TX,
90 DMA_ID_UART3_RX,
91 DMA_ID_USBDEV_EP0_RX,
92 DMA_ID_USBDEV_EP0_TX,
93 DMA_ID_USBDEV_EP2_TX,
94 DMA_ID_USBDEV_EP3_TX,
95 DMA_ID_USBDEV_EP4_RX,
96 DMA_ID_USBDEV_EP5_RX,
97 DMA_ID_I2S_TX,
98 DMA_ID_I2S_RX,
99 DMA_NUM_DEV
100};
101
102/* DMA Device ID's for 2nd bank (AU1100) follow */
103enum {
104 DMA_ID_SD0_TX = 0,
105 DMA_ID_SD0_RX,
106 DMA_ID_SD1_TX,
107 DMA_ID_SD1_RX,
108 DMA_NUM_DEV_BANK2
109};
110
111struct dma_chan {
112 int dev_id; /* this channel is allocated if >= 0, */
113 /* free otherwise */
114 unsigned int io;
115 const char *dev_str;
116 int irq;
117 void *irq_dev;
118 unsigned int fifo_addr;
119 unsigned int mode;
120};
121
122/* These are in arch/mips/au1000/common/dma.c */
123extern struct dma_chan au1000_dma_table[];
124extern int request_au1000_dma(int dev_id,
125 const char *dev_str,
126 irq_handler_t irqhandler,
127 unsigned long irqflags,
128 void *irq_dev_id);
129extern void free_au1000_dma(unsigned int dmanr);
130extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
131 int length, int *eof, void *data);
132extern void dump_au1000_dma_channel(unsigned int dmanr);
133extern spinlock_t au1000_dma_spin_lock;
134
135static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
136{
137 if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
138 au1000_dma_table[dmanr].dev_id < 0)
139 return NULL;
140 return &au1000_dma_table[dmanr];
141}
142
143static inline unsigned long claim_dma_lock(void)
144{
145 unsigned long flags;
146
147 spin_lock_irqsave(&au1000_dma_spin_lock, flags);
148 return flags;
149}
150
151static inline void release_dma_lock(unsigned long flags)
152{
153 spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
154}
155
156/*
157 * Set the DMA buffer enable bits in the mode register.
158 */
159static inline void enable_dma_buffer0(unsigned int dmanr)
160{
161 struct dma_chan *chan = get_dma_chan(dmanr);
162
163 if (!chan)
164 return;
165 au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
166}
167
168static inline void enable_dma_buffer1(unsigned int dmanr)
169{
170 struct dma_chan *chan = get_dma_chan(dmanr);
171
172 if (!chan)
173 return;
174 au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
175}
176static inline void enable_dma_buffers(unsigned int dmanr)
177{
178 struct dma_chan *chan = get_dma_chan(dmanr);
179
180 if (!chan)
181 return;
182 au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
183}
184
185static inline void start_dma(unsigned int dmanr)
186{
187 struct dma_chan *chan = get_dma_chan(dmanr);
188
189 if (!chan)
190 return;
191 au_writel(DMA_GO, chan->io + DMA_MODE_SET);
192}
193
194#define DMA_HALT_POLL 0x5000
195
196static inline void halt_dma(unsigned int dmanr)
197{
198 struct dma_chan *chan = get_dma_chan(dmanr);
199 int i;
200
201 if (!chan)
202 return;
203 au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
204
205 /* Poll the halt bit */
206 for (i = 0; i < DMA_HALT_POLL; i++)
207 if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
208 break;
209 if (i == DMA_HALT_POLL)
210 printk(KERN_INFO "halt_dma: HALT poll expired!\n");
211}
212
213static inline void disable_dma(unsigned int dmanr)
214{
215 struct dma_chan *chan = get_dma_chan(dmanr);
216
217 if (!chan)
218 return;
219
220 halt_dma(dmanr);
221
222 /* Now we can disable the buffers */
223 au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
224}
225
226static inline int dma_halted(unsigned int dmanr)
227{
228 struct dma_chan *chan = get_dma_chan(dmanr);
229
230 if (!chan)
231 return 1;
232 return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
233}
234
235/* Initialize a DMA channel. */
236static inline void init_dma(unsigned int dmanr)
237{
238 struct dma_chan *chan = get_dma_chan(dmanr);
239 u32 mode;
240
241 if (!chan)
242 return;
243
244 disable_dma(dmanr);
245
246 /* Set device FIFO address */
247 au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
248
249 mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
250 if (chan->irq)
251 mode |= DMA_IE;
252
253 au_writel(~mode, chan->io + DMA_MODE_CLEAR);
254 au_writel(mode, chan->io + DMA_MODE_SET);
255}
256
257/*
258 * Set mode for a specific DMA channel
259 */
260static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
261{
262 struct dma_chan *chan = get_dma_chan(dmanr);
263
264 if (!chan)
265 return;
266 /*
267 * set_dma_mode is only allowed to change endianess, direction,
268 * transfer size, device FIFO width, and coherency settings.
269 * Make sure anything else is masked off.
270 */
271 mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
272 chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
273 chan->mode |= mode;
274}
275
276static inline unsigned int get_dma_mode(unsigned int dmanr)
277{
278 struct dma_chan *chan = get_dma_chan(dmanr);
279
280 if (!chan)
281 return 0;
282 return chan->mode;
283}
284
285static inline int get_dma_active_buffer(unsigned int dmanr)
286{
287 struct dma_chan *chan = get_dma_chan(dmanr);
288
289 if (!chan)
290 return -1;
291 return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
292}
293
294/*
295 * Set the device FIFO address for a specific DMA channel - only
296 * applicable to GPO4 and GPO5. All the other devices have fixed
297 * FIFO addresses.
298 */
299static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
300{
301 struct dma_chan *chan = get_dma_chan(dmanr);
302
303 if (!chan)
304 return;
305
306 if (chan->mode & DMA_DS) /* second bank of device IDs */
307 return;
308
309 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
310 return;
311
312 au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
313}
314
315/*
316 * Clear the DMA buffer done bits in the mode register.
317 */
318static inline void clear_dma_done0(unsigned int dmanr)
319{
320 struct dma_chan *chan = get_dma_chan(dmanr);
321
322 if (!chan)
323 return;
324 au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
325}
326
327static inline void clear_dma_done1(unsigned int dmanr)
328{
329 struct dma_chan *chan = get_dma_chan(dmanr);
330
331 if (!chan)
332 return;
333 au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
334}
335
336/*
337 * This does nothing - not applicable to Au1000 DMA.
338 */
339static inline void set_dma_page(unsigned int dmanr, char pagenr)
340{
341}
342
343/*
344 * Set Buffer 0 transfer address for specific DMA channel.
345 */
346static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
347{
348 struct dma_chan *chan = get_dma_chan(dmanr);
349
350 if (!chan)
351 return;
352 au_writel(a, chan->io + DMA_BUFFER0_START);
353}
354
355/*
356 * Set Buffer 1 transfer address for specific DMA channel.
357 */
358static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
359{
360 struct dma_chan *chan = get_dma_chan(dmanr);
361
362 if (!chan)
363 return;
364 au_writel(a, chan->io + DMA_BUFFER1_START);
365}
366
367
368/*
369 * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
370 */
371static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
372{
373 struct dma_chan *chan = get_dma_chan(dmanr);
374
375 if (!chan)
376 return;
377 count &= DMA_COUNT_MASK;
378 au_writel(count, chan->io + DMA_BUFFER0_COUNT);
379}
380
381/*
382 * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
383 */
384static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
385{
386 struct dma_chan *chan = get_dma_chan(dmanr);
387
388 if (!chan)
389 return;
390 count &= DMA_COUNT_MASK;
391 au_writel(count, chan->io + DMA_BUFFER1_COUNT);
392}
393
394/*
395 * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
396 */
397static inline void set_dma_count(unsigned int dmanr, unsigned int count)
398{
399 struct dma_chan *chan = get_dma_chan(dmanr);
400
401 if (!chan)
402 return;
403 count &= DMA_COUNT_MASK;
404 au_writel(count, chan->io + DMA_BUFFER0_COUNT);
405 au_writel(count, chan->io + DMA_BUFFER1_COUNT);
406}
407
408/*
409 * Returns which buffer has its done bit set in the mode register.
410 * Returns -1 if neither or both done bits set.
411 */
412static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
413{
414 struct dma_chan *chan = get_dma_chan(dmanr);
415
416 if (!chan)
417 return 0;
418 return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
419}
420
421
422/*
423 * Returns the DMA channel's Buffer Done IRQ number.
424 */
425static inline int get_dma_done_irq(unsigned int dmanr)
426{
427 struct dma_chan *chan = get_dma_chan(dmanr);
428
429 if (!chan)
430 return -1;
431 return chan->irq;
432}
433
434/*
435 * Get DMA residue count. Returns the number of _bytes_ left to transfer.
436 */
437static inline int get_dma_residue(unsigned int dmanr)
438{
439 int curBufCntReg, count;
440 struct dma_chan *chan = get_dma_chan(dmanr);
441
442 if (!chan)
443 return 0;
444
445 curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
446 DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
447
448 count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
449
450 if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
451 count <<= 1;
452 else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
453 count <<= 2;
454
455 return count;
456}
457
458#endif /* __ASM_AU1000_DMA_H */
diff --git a/include/asm-mips/mach-au1x00/au1000_gpio.h b/include/asm-mips/mach-au1x00/au1000_gpio.h
deleted file mode 100644
index d8c96fda5549..000000000000
--- a/include/asm-mips/mach-au1x00/au1000_gpio.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * FILE NAME au1000_gpio.h
3 *
4 * BRIEF MODULE DESCRIPTION
5 * API to Alchemy Au1xx0 GPIO device.
6 *
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Steve Longerbeam
9 *
10 * Copyright 2001, 2008 MontaVista Software Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#ifndef __AU1000_GPIO_H
34#define __AU1000_GPIO_H
35
36#include <linux/ioctl.h>
37
38#define AU1000GPIO_IOC_MAGIC 'A'
39
40#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
41#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
42#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
43#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
44#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
45#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
46
47#ifdef __KERNEL__
48extern u32 get_au1000_avail_gpio_mask(void);
49extern int au1000gpio_tristate(u32 data);
50extern int au1000gpio_in(u32 *data);
51extern int au1000gpio_set(u32 data);
52extern int au1000gpio_clear(u32 data);
53extern int au1000gpio_out(u32 data);
54#endif
55
56#endif
diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h
deleted file mode 100644
index c35e20918490..000000000000
--- a/include/asm-mips/mach-au1x00/au1100_mmc.h
+++ /dev/null
@@ -1,208 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Defines for using the MMC/SD controllers on the
4 * Alchemy Au1100 mips processor.
5 *
6 * Copyright (c) 2003 Embedded Edge, LLC.
7 * Author: Embedded Edge, LLC.
8 * dan@embeddededge.com or tim@embeddededge.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31/*
32 * AU1100 MMC/SD definitions.
33 *
34 * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary"
35 * June, 2003
36 */
37
38#ifndef __ASM_AU1100_MMC_H
39#define __ASM_AU1100_MMC_H
40
41#include <linux/leds.h>
42
43struct au1xmmc_platform_data {
44 int(*cd_setup)(void *mmc_host, int on);
45 int(*card_inserted)(void *mmc_host);
46 int(*card_readonly)(void *mmc_host);
47 void(*set_power)(void *mmc_host, int state);
48 struct led_classdev *led;
49};
50
51#define SD0_BASE 0xB0600000
52#define SD1_BASE 0xB0680000
53
54
55/*
56 * Register offsets.
57 */
58#define SD_TXPORT (0x0000)
59#define SD_RXPORT (0x0004)
60#define SD_CONFIG (0x0008)
61#define SD_ENABLE (0x000C)
62#define SD_CONFIG2 (0x0010)
63#define SD_BLKSIZE (0x0014)
64#define SD_STATUS (0x0018)
65#define SD_DEBUG (0x001C)
66#define SD_CMD (0x0020)
67#define SD_CMDARG (0x0024)
68#define SD_RESP3 (0x0028)
69#define SD_RESP2 (0x002C)
70#define SD_RESP1 (0x0030)
71#define SD_RESP0 (0x0034)
72#define SD_TIMEOUT (0x0038)
73
74
75/*
76 * SD_TXPORT bit definitions.
77 */
78#define SD_TXPORT_TXD (0x000000ff)
79
80
81/*
82 * SD_RXPORT bit definitions.
83 */
84#define SD_RXPORT_RXD (0x000000ff)
85
86
87/*
88 * SD_CONFIG bit definitions.
89 */
90#define SD_CONFIG_DIV (0x000001ff)
91#define SD_CONFIG_DE (0x00000200)
92#define SD_CONFIG_NE (0x00000400)
93#define SD_CONFIG_TU (0x00000800)
94#define SD_CONFIG_TO (0x00001000)
95#define SD_CONFIG_RU (0x00002000)
96#define SD_CONFIG_RO (0x00004000)
97#define SD_CONFIG_I (0x00008000)
98#define SD_CONFIG_CR (0x00010000)
99#define SD_CONFIG_RAT (0x00020000)
100#define SD_CONFIG_DD (0x00040000)
101#define SD_CONFIG_DT (0x00080000)
102#define SD_CONFIG_SC (0x00100000)
103#define SD_CONFIG_RC (0x00200000)
104#define SD_CONFIG_WC (0x00400000)
105#define SD_CONFIG_xxx (0x00800000)
106#define SD_CONFIG_TH (0x01000000)
107#define SD_CONFIG_TE (0x02000000)
108#define SD_CONFIG_TA (0x04000000)
109#define SD_CONFIG_RH (0x08000000)
110#define SD_CONFIG_RA (0x10000000)
111#define SD_CONFIG_RF (0x20000000)
112#define SD_CONFIG_CD (0x40000000)
113#define SD_CONFIG_SI (0x80000000)
114
115
116/*
117 * SD_ENABLE bit definitions.
118 */
119#define SD_ENABLE_CE (0x00000001)
120#define SD_ENABLE_R (0x00000002)
121
122
123/*
124 * SD_CONFIG2 bit definitions.
125 */
126#define SD_CONFIG2_EN (0x00000001)
127#define SD_CONFIG2_FF (0x00000002)
128#define SD_CONFIG2_xx1 (0x00000004)
129#define SD_CONFIG2_DF (0x00000008)
130#define SD_CONFIG2_DC (0x00000010)
131#define SD_CONFIG2_xx2 (0x000000e0)
132#define SD_CONFIG2_WB (0x00000100)
133#define SD_CONFIG2_RW (0x00000200)
134
135
136/*
137 * SD_BLKSIZE bit definitions.
138 */
139#define SD_BLKSIZE_BS (0x000007ff)
140#define SD_BLKSIZE_BS_SHIFT (0)
141#define SD_BLKSIZE_BC (0x01ff0000)
142#define SD_BLKSIZE_BC_SHIFT (16)
143
144
145/*
146 * SD_STATUS bit definitions.
147 */
148#define SD_STATUS_DCRCW (0x00000007)
149#define SD_STATUS_xx1 (0x00000008)
150#define SD_STATUS_CB (0x00000010)
151#define SD_STATUS_DB (0x00000020)
152#define SD_STATUS_CF (0x00000040)
153#define SD_STATUS_D3 (0x00000080)
154#define SD_STATUS_xx2 (0x00000300)
155#define SD_STATUS_NE (0x00000400)
156#define SD_STATUS_TU (0x00000800)
157#define SD_STATUS_TO (0x00001000)
158#define SD_STATUS_RU (0x00002000)
159#define SD_STATUS_RO (0x00004000)
160#define SD_STATUS_I (0x00008000)
161#define SD_STATUS_CR (0x00010000)
162#define SD_STATUS_RAT (0x00020000)
163#define SD_STATUS_DD (0x00040000)
164#define SD_STATUS_DT (0x00080000)
165#define SD_STATUS_SC (0x00100000)
166#define SD_STATUS_RC (0x00200000)
167#define SD_STATUS_WC (0x00400000)
168#define SD_STATUS_xx3 (0x00800000)
169#define SD_STATUS_TH (0x01000000)
170#define SD_STATUS_TE (0x02000000)
171#define SD_STATUS_TA (0x04000000)
172#define SD_STATUS_RH (0x08000000)
173#define SD_STATUS_RA (0x10000000)
174#define SD_STATUS_RF (0x20000000)
175#define SD_STATUS_CD (0x40000000)
176#define SD_STATUS_SI (0x80000000)
177
178
179/*
180 * SD_CMD bit definitions.
181 */
182#define SD_CMD_GO (0x00000001)
183#define SD_CMD_RY (0x00000002)
184#define SD_CMD_xx1 (0x0000000c)
185#define SD_CMD_CT_MASK (0x000000f0)
186#define SD_CMD_CT_0 (0x00000000)
187#define SD_CMD_CT_1 (0x00000010)
188#define SD_CMD_CT_2 (0x00000020)
189#define SD_CMD_CT_3 (0x00000030)
190#define SD_CMD_CT_4 (0x00000040)
191#define SD_CMD_CT_5 (0x00000050)
192#define SD_CMD_CT_6 (0x00000060)
193#define SD_CMD_CT_7 (0x00000070)
194#define SD_CMD_CI (0x0000ff00)
195#define SD_CMD_CI_SHIFT (8)
196#define SD_CMD_RT_MASK (0x00ff0000)
197#define SD_CMD_RT_0 (0x00000000)
198#define SD_CMD_RT_1 (0x00010000)
199#define SD_CMD_RT_2 (0x00020000)
200#define SD_CMD_RT_3 (0x00030000)
201#define SD_CMD_RT_4 (0x00040000)
202#define SD_CMD_RT_5 (0x00050000)
203#define SD_CMD_RT_6 (0x00060000)
204#define SD_CMD_RT_1B (0x00810000)
205
206
207#endif /* __ASM_AU1100_MMC_H */
208
diff --git a/include/asm-mips/mach-au1x00/au1550_spi.h b/include/asm-mips/mach-au1x00/au1550_spi.h
deleted file mode 100644
index 08e1958e9410..000000000000
--- a/include/asm-mips/mach-au1x00/au1550_spi.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
3 */
4
5#ifndef _AU1550_SPI_H_
6#define _AU1550_SPI_H_
7
8struct au1550_spi_info {
9 u32 mainclk_hz; /* main input clock frequency of PSC */
10 u16 num_chipselect; /* number of chipselects supported */
11 void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
12 void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
13};
14
15#endif
diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/include/asm-mips/mach-au1x00/au1xxx.h
deleted file mode 100644
index 1b3655090ed3..000000000000
--- a/include/asm-mips/mach-au1x00/au1xxx.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _AU1XXX_H_
24#define _AU1XXX_H_
25
26#include <asm/mach-au1x00/au1000.h>
27
28#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
29 defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
30#include <asm/mach-db1x00/db1x00.h>
31
32#elif defined(CONFIG_MIPS_PB1550)
33#include <asm/mach-pb1x00/pb1550.h>
34
35#elif defined(CONFIG_MIPS_PB1200)
36#include <asm/mach-pb1x00/pb1200.h>
37
38#elif defined(CONFIG_MIPS_DB1200)
39#include <asm/mach-db1x00/db1200.h>
40
41#endif
42
43#endif /* _AU1XXX_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
deleted file mode 100644
index 44a67bf05dc1..000000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ /dev/null
@@ -1,386 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1550 Descriptor
5 * Based DMA Controller.
6 *
7 * Copyright 2004 Embedded Edge, LLC
8 * dan@embeddededge.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31/*
32 * Specifics for the Au1xxx Descriptor-Based DMA Controller,
33 * first seen in the AU1550 part.
34 */
35#ifndef _AU1000_DBDMA_H_
36#define _AU1000_DBDMA_H_
37
38#ifndef _LANGUAGE_ASSEMBLY
39
40/*
41 * The DMA base addresses.
42 * The channels are every 256 bytes (0x0100) from the channel 0 base.
43 * Interrupt status/enable is bits 15:0 for channels 15 to zero.
44 */
45#define DDMA_GLOBAL_BASE 0xb4003000
46#define DDMA_CHANNEL_BASE 0xb4002000
47
48typedef volatile struct dbdma_global {
49 u32 ddma_config;
50 u32 ddma_intstat;
51 u32 ddma_throttle;
52 u32 ddma_inten;
53} dbdma_global_t;
54
55/* General Configuration. */
56#define DDMA_CONFIG_AF (1 << 2)
57#define DDMA_CONFIG_AH (1 << 1)
58#define DDMA_CONFIG_AL (1 << 0)
59
60#define DDMA_THROTTLE_EN (1 << 31)
61
62/* The structure of a DMA Channel. */
63typedef volatile struct au1xxx_dma_channel {
64 u32 ddma_cfg; /* See below */
65 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
66 u32 ddma_statptr; /* word aligned pointer to status word */
67 u32 ddma_dbell; /* A write activates channel operation */
68 u32 ddma_irq; /* If bit 0 set, interrupt pending */
69 u32 ddma_stat; /* See below */
70 u32 ddma_bytecnt; /* Byte count, valid only when chan idle */
71 /* Remainder, up to the 256 byte boundary, is reserved. */
72} au1x_dma_chan_t;
73
74#define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */
75#define DDMA_CFG_SP (1 << 8) /* source DMA polarity */
76#define DDMA_CFG_DED (1 << 7) /* destination DMA level/edge detect */
77#define DDMA_CFG_DP (1 << 6) /* destination DMA polarity */
78#define DDMA_CFG_SYNC (1 << 5) /* Sync static bus controller */
79#define DDMA_CFG_PPR (1 << 4) /* PCI posted read/write control */
80#define DDMA_CFG_DFN (1 << 3) /* Descriptor fetch non-coherent */
81#define DDMA_CFG_SBE (1 << 2) /* Source big endian */
82#define DDMA_CFG_DBE (1 << 1) /* Destination big endian */
83#define DDMA_CFG_EN (1 << 0) /* Channel enable */
84
85/*
86 * Always set when descriptor processing done, regardless of
87 * interrupt enable state. Reflected in global intstat, don't
88 * clear this until global intstat is read/used.
89 */
90#define DDMA_IRQ_IN (1 << 0)
91
92#define DDMA_STAT_DB (1 << 2) /* Doorbell pushed */
93#define DDMA_STAT_V (1 << 1) /* Descriptor valid */
94#define DDMA_STAT_H (1 << 0) /* Channel Halted */
95
96/*
97 * "Standard" DDMA Descriptor.
98 * Must be 32-byte aligned.
99 */
100typedef volatile struct au1xxx_ddma_desc {
101 u32 dscr_cmd0; /* See below */
102 u32 dscr_cmd1; /* See below */
103 u32 dscr_source0; /* source phys address */
104 u32 dscr_source1; /* See below */
105 u32 dscr_dest0; /* Destination address */
106 u32 dscr_dest1; /* See below */
107 u32 dscr_stat; /* completion status */
108 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
109 /*
110 * First 32 bytes are HW specific!!!
111 * Lets have some SW data following -- make sure it's 32 bytes.
112 */
113 u32 sw_status;
114 u32 sw_context;
115 u32 sw_reserved[6];
116} au1x_ddma_desc_t;
117
118#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */
119#define DSCR_CMD0_MEM (1 << 30) /* mem-mem transfer */
120#define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */
121#define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */
122#define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */
123#define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */
124#define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */
125#define DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */
126#define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */
127#define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */
128#define DSCR_CMD0_SM (0x1 << 10) /* Stride mode */
129#define DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */
130#define DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */
131#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
132#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
133
134#define SW_STATUS_INUSE (1 << 0)
135
136/* Command 0 device IDs. */
137#ifdef CONFIG_SOC_AU1550
138#define DSCR_CMD0_UART0_TX 0
139#define DSCR_CMD0_UART0_RX 1
140#define DSCR_CMD0_UART3_TX 2
141#define DSCR_CMD0_UART3_RX 3
142#define DSCR_CMD0_DMA_REQ0 4
143#define DSCR_CMD0_DMA_REQ1 5
144#define DSCR_CMD0_DMA_REQ2 6
145#define DSCR_CMD0_DMA_REQ3 7
146#define DSCR_CMD0_USBDEV_RX0 8
147#define DSCR_CMD0_USBDEV_TX0 9
148#define DSCR_CMD0_USBDEV_TX1 10
149#define DSCR_CMD0_USBDEV_TX2 11
150#define DSCR_CMD0_USBDEV_RX3 12
151#define DSCR_CMD0_USBDEV_RX4 13
152#define DSCR_CMD0_PSC0_TX 14
153#define DSCR_CMD0_PSC0_RX 15
154#define DSCR_CMD0_PSC1_TX 16
155#define DSCR_CMD0_PSC1_RX 17
156#define DSCR_CMD0_PSC2_TX 18
157#define DSCR_CMD0_PSC2_RX 19
158#define DSCR_CMD0_PSC3_TX 20
159#define DSCR_CMD0_PSC3_RX 21
160#define DSCR_CMD0_PCI_WRITE 22
161#define DSCR_CMD0_NAND_FLASH 23
162#define DSCR_CMD0_MAC0_RX 24
163#define DSCR_CMD0_MAC0_TX 25
164#define DSCR_CMD0_MAC1_RX 26
165#define DSCR_CMD0_MAC1_TX 27
166#endif /* CONFIG_SOC_AU1550 */
167
168#ifdef CONFIG_SOC_AU1200
169#define DSCR_CMD0_UART0_TX 0
170#define DSCR_CMD0_UART0_RX 1
171#define DSCR_CMD0_UART1_TX 2
172#define DSCR_CMD0_UART1_RX 3
173#define DSCR_CMD0_DMA_REQ0 4
174#define DSCR_CMD0_DMA_REQ1 5
175#define DSCR_CMD0_MAE_BE 6
176#define DSCR_CMD0_MAE_FE 7
177#define DSCR_CMD0_SDMS_TX0 8
178#define DSCR_CMD0_SDMS_RX0 9
179#define DSCR_CMD0_SDMS_TX1 10
180#define DSCR_CMD0_SDMS_RX1 11
181#define DSCR_CMD0_AES_TX 13
182#define DSCR_CMD0_AES_RX 12
183#define DSCR_CMD0_PSC0_TX 14
184#define DSCR_CMD0_PSC0_RX 15
185#define DSCR_CMD0_PSC1_TX 16
186#define DSCR_CMD0_PSC1_RX 17
187#define DSCR_CMD0_CIM_RXA 18
188#define DSCR_CMD0_CIM_RXB 19
189#define DSCR_CMD0_CIM_RXC 20
190#define DSCR_CMD0_MAE_BOTH 21
191#define DSCR_CMD0_LCD 22
192#define DSCR_CMD0_NAND_FLASH 23
193#define DSCR_CMD0_PSC0_SYNC 24
194#define DSCR_CMD0_PSC1_SYNC 25
195#define DSCR_CMD0_CIM_SYNC 26
196#endif /* CONFIG_SOC_AU1200 */
197
198#define DSCR_CMD0_THROTTLE 30
199#define DSCR_CMD0_ALWAYS 31
200#define DSCR_NDEV_IDS 32
201/* This macro is used to find/create custom device types */
202#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
203 ((d) & 0xFF))
204#define DSCR_CUSTOM2DEV_ID(x) ((x) & 0xFF)
205
206#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
207#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
208
209/* Source/Destination transfer width. */
210#define DSCR_CMD0_BYTE 0
211#define DSCR_CMD0_HALFWORD 1
212#define DSCR_CMD0_WORD 2
213
214#define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
215#define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
216
217/* DDMA Descriptor Type. */
218#define DSCR_CMD0_STANDARD 0
219#define DSCR_CMD0_LITERAL 1
220#define DSCR_CMD0_CMP_BRANCH 2
221
222#define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
223
224/* Status Instruction. */
225#define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
226#define DSCR_CMD0_ST_CURRENT 1 /* Write current status */
227#define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */
228#define DSCR_CMD0_ST_BYTECNT 3 /* Write remaining byte count */
229
230#define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
231
232/* Descriptor Command 1. */
233#define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
234#define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
235#define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
236#define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
237
238/* Flag description. */
239#define DSCR_CMD1_FL_MEM_STRIDE0 0
240#define DSCR_CMD1_FL_MEM_STRIDE1 1
241#define DSCR_CMD1_FL_MEM_STRIDE2 2
242
243#define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
244
245/* Source1, 1-dimensional stride. */
246#define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */
247#define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */
248#define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
249#define DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14)
250#define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
251#define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
252
253/* Dest1, 1-dimensional stride. */
254#define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */
255#define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */
256#define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
257#define DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14)
258#define DSCR_DEST1_DS_MASK (0x3fff << 0) /* Stride */
259#define DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0)
260
261#define DSCR_xTS_SIZE1 0
262#define DSCR_xTS_SIZE2 1
263#define DSCR_xTS_SIZE4 2
264#define DSCR_xTS_SIZE8 3
265#define DSCR_SRC1_STS(x) (((x) & 3) << 30)
266#define DSCR_DEST1_DTS(x) (((x) & 3) << 30)
267
268#define DSCR_xAM_INCREMENT 0
269#define DSCR_xAM_DECREMENT 1
270#define DSCR_xAM_STATIC 2
271#define DSCR_xAM_BURST 3
272#define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
273#define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
274
275/* The next descriptor pointer. */
276#define DSCR_NXTPTR_MASK (0x07ffffff)
277#define DSCR_NXTPTR(x) ((x) >> 5)
278#define DSCR_GET_NXTPTR(x) ((x) << 5)
279#define DSCR_NXTPTR_MS (1 << 27)
280
281/* The number of DBDMA channels. */
282#define NUM_DBDMA_CHANS 16
283
284/*
285 * DDMA API definitions
286 * FIXME: may not fit to this header file
287 */
288typedef struct dbdma_device_table {
289 u32 dev_id;
290 u32 dev_flags;
291 u32 dev_tsize;
292 u32 dev_devwidth;
293 u32 dev_physaddr; /* If FIFO */
294 u32 dev_intlevel;
295 u32 dev_intpolarity;
296} dbdev_tab_t;
297
298
299typedef struct dbdma_chan_config {
300 spinlock_t lock;
301
302 u32 chan_flags;
303 u32 chan_index;
304 dbdev_tab_t *chan_src;
305 dbdev_tab_t *chan_dest;
306 au1x_dma_chan_t *chan_ptr;
307 au1x_ddma_desc_t *chan_desc_base;
308 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
309 void *chan_callparam;
310 void (*chan_callback)(int, void *);
311} chan_tab_t;
312
313#define DEV_FLAGS_INUSE (1 << 0)
314#define DEV_FLAGS_ANYUSE (1 << 1)
315#define DEV_FLAGS_OUT (1 << 2)
316#define DEV_FLAGS_IN (1 << 3)
317#define DEV_FLAGS_BURSTABLE (1 << 4)
318#define DEV_FLAGS_SYNC (1 << 5)
319/* end DDMA API definitions */
320
321/*
322 * External functions for drivers to use.
323 * Use this to allocate a DBDMA channel. The device IDs are one of
324 * the DSCR_CMD0 devices IDs, which is usually redefined to a more
325 * meaningful name. The 'callback' is called during DMA completion
326 * interrupt.
327 */
328extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
329 void (*callback)(int, void *),
330 void *callparam);
331
332#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
333
334/* Set the device width of an in/out FIFO. */
335u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
336
337/* Allocate a ring of descriptors for DBDMA. */
338u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
339
340/* Put buffers on source/destination descriptors. */
341u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
342u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
343
344/* Get a buffer from the destination descriptor. */
345u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
346
347void au1xxx_dbdma_stop(u32 chanid);
348void au1xxx_dbdma_start(u32 chanid);
349void au1xxx_dbdma_reset(u32 chanid);
350u32 au1xxx_get_dma_residue(u32 chanid);
351
352void au1xxx_dbdma_chan_free(u32 chanid);
353void au1xxx_dbdma_dump(u32 chanid);
354
355u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
356
357u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
358extern void au1xxx_ddma_del_device(u32 devid);
359void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
360
361/*
362 * Some compatibilty macros -- needed to make changes to API
363 * without breaking existing drivers.
364 */
365#define au1xxx_dbdma_put_source(chanid, buf, nbytes) \
366 _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
367#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags) \
368 _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
369#define put_source_flags(chanid, buf, nbytes, flags) \
370 au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
371
372#define au1xxx_dbdma_put_dest(chanid, buf, nbytes) \
373 _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
374#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags) \
375 _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
376#define put_dest_flags(chanid, buf, nbytes, flags) \
377 au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
378
379/*
380 * Flags for the put_source/put_dest functions.
381 */
382#define DDMA_FLAGS_IE (1 << 0)
383#define DDMA_FLAGS_NOIE (1 << 1)
384
385#endif /* _LANGUAGE_ASSEMBLY */
386#endif /* _AU1000_DBDMA_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
deleted file mode 100644
index 60638b8969ba..000000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ /dev/null
@@ -1,194 +0,0 @@
1/*
2 * include/asm-mips/mach-au1x00/au1xxx_ide.h version 01.30.00 Aug. 02 2005
3 *
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
6 *
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
8 *
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
12 * version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 *
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
31 */
32
33#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
34#define DMA_WAIT_TIMEOUT 100
35#define NUM_DESCRIPTORS PRD_ENTRIES
36#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
37#define NUM_DESCRIPTORS 2
38#endif
39
40#ifndef AU1XXX_ATA_RQSIZE
41#define AU1XXX_ATA_RQSIZE 128
42#endif
43
44/* Disable Burstable-Support for DBDMA */
45#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
46#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON 0
47#endif
48
49#ifdef CONFIG_PM
50/*
51 * This will enable the device to be powered up when write() or read()
52 * is called. If this is not defined, the driver will return -EBUSY.
53 */
54#define WAKE_ON_ACCESS 1
55
56typedef struct {
57 spinlock_t lock; /* Used to block on state transitions */
58 au1xxx_power_dev_t *dev; /* Power Managers device structure */
59 unsigned stopped; /* Used to signal device is stopped */
60} pm_state;
61#endif
62
63typedef struct {
64 u32 tx_dev_id, rx_dev_id, target_dev_id;
65 u32 tx_chan, rx_chan;
66 void *tx_desc_head, *rx_desc_head;
67 ide_hwif_t *hwif;
68#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
69 ide_drive_t *drive;
70 struct dbdma_cmd *dma_table_cpu;
71 dma_addr_t dma_table_dma;
72#endif
73 int irq;
74 u32 regbase;
75#ifdef CONFIG_PM
76 pm_state pm;
77#endif
78} _auide_hwif;
79
80/******************************************************************************/
81/* PIO Mode timing calculation : */
82/* */
83/* Static Bus Spec ATA Spec */
84/* Tcsoe = t1 */
85/* Toecs = t9 */
86/* Twcs = t9 */
87/* Tcsh = t2i | t2 */
88/* Tcsoff = t2i | t2 */
89/* Twp = t2 */
90/* Tcsw = t1 */
91/* Tpm = 0 */
92/* Ta = t1+t2 */
93/******************************************************************************/
94
95#define TCSOE_MASK (0x07 << 29)
96#define TOECS_MASK (0x07 << 26)
97#define TWCS_MASK (0x07 << 28)
98#define TCSH_MASK (0x0F << 24)
99#define TCSOFF_MASK (0x07 << 20)
100#define TWP_MASK (0x3F << 14)
101#define TCSW_MASK (0x0F << 10)
102#define TPM_MASK (0x0F << 6)
103#define TA_MASK (0x3F << 0)
104#define TS_MASK (1 << 8)
105
106/* Timing parameters PIO mode 0 */
107#define SBC_IDE_PIO0_TCSOE (0x04 << 29)
108#define SBC_IDE_PIO0_TOECS (0x01 << 26)
109#define SBC_IDE_PIO0_TWCS (0x02 << 28)
110#define SBC_IDE_PIO0_TCSH (0x08 << 24)
111#define SBC_IDE_PIO0_TCSOFF (0x07 << 20)
112#define SBC_IDE_PIO0_TWP (0x10 << 14)
113#define SBC_IDE_PIO0_TCSW (0x04 << 10)
114#define SBC_IDE_PIO0_TPM (0x00 << 6)
115#define SBC_IDE_PIO0_TA (0x15 << 0)
116/* Timing parameters PIO mode 1 */
117#define SBC_IDE_PIO1_TCSOE (0x03 << 29)
118#define SBC_IDE_PIO1_TOECS (0x01 << 26)
119#define SBC_IDE_PIO1_TWCS (0x01 << 28)
120#define SBC_IDE_PIO1_TCSH (0x06 << 24)
121#define SBC_IDE_PIO1_TCSOFF (0x06 << 20)
122#define SBC_IDE_PIO1_TWP (0x08 << 14)
123#define SBC_IDE_PIO1_TCSW (0x03 << 10)
124#define SBC_IDE_PIO1_TPM (0x00 << 6)
125#define SBC_IDE_PIO1_TA (0x0B << 0)
126/* Timing parameters PIO mode 2 */
127#define SBC_IDE_PIO2_TCSOE (0x05 << 29)
128#define SBC_IDE_PIO2_TOECS (0x01 << 26)
129#define SBC_IDE_PIO2_TWCS (0x01 << 28)
130#define SBC_IDE_PIO2_TCSH (0x07 << 24)
131#define SBC_IDE_PIO2_TCSOFF (0x07 << 20)
132#define SBC_IDE_PIO2_TWP (0x1F << 14)
133#define SBC_IDE_PIO2_TCSW (0x05 << 10)
134#define SBC_IDE_PIO2_TPM (0x00 << 6)
135#define SBC_IDE_PIO2_TA (0x22 << 0)
136/* Timing parameters PIO mode 3 */
137#define SBC_IDE_PIO3_TCSOE (0x05 << 29)
138#define SBC_IDE_PIO3_TOECS (0x01 << 26)
139#define SBC_IDE_PIO3_TWCS (0x01 << 28)
140#define SBC_IDE_PIO3_TCSH (0x0D << 24)
141#define SBC_IDE_PIO3_TCSOFF (0x0D << 20)
142#define SBC_IDE_PIO3_TWP (0x15 << 14)
143#define SBC_IDE_PIO3_TCSW (0x05 << 10)
144#define SBC_IDE_PIO3_TPM (0x00 << 6)
145#define SBC_IDE_PIO3_TA (0x1A << 0)
146/* Timing parameters PIO mode 4 */
147#define SBC_IDE_PIO4_TCSOE (0x04 << 29)
148#define SBC_IDE_PIO4_TOECS (0x01 << 26)
149#define SBC_IDE_PIO4_TWCS (0x01 << 28)
150#define SBC_IDE_PIO4_TCSH (0x04 << 24)
151#define SBC_IDE_PIO4_TCSOFF (0x04 << 20)
152#define SBC_IDE_PIO4_TWP (0x0D << 14)
153#define SBC_IDE_PIO4_TCSW (0x03 << 10)
154#define SBC_IDE_PIO4_TPM (0x00 << 6)
155#define SBC_IDE_PIO4_TA (0x12 << 0)
156/* Timing parameters MDMA mode 0 */
157#define SBC_IDE_MDMA0_TCSOE (0x03 << 29)
158#define SBC_IDE_MDMA0_TOECS (0x01 << 26)
159#define SBC_IDE_MDMA0_TWCS (0x01 << 28)
160#define SBC_IDE_MDMA0_TCSH (0x07 << 24)
161#define SBC_IDE_MDMA0_TCSOFF (0x07 << 20)
162#define SBC_IDE_MDMA0_TWP (0x0C << 14)
163#define SBC_IDE_MDMA0_TCSW (0x03 << 10)
164#define SBC_IDE_MDMA0_TPM (0x00 << 6)
165#define SBC_IDE_MDMA0_TA (0x0F << 0)
166/* Timing parameters MDMA mode 1 */
167#define SBC_IDE_MDMA1_TCSOE (0x05 << 29)
168#define SBC_IDE_MDMA1_TOECS (0x01 << 26)
169#define SBC_IDE_MDMA1_TWCS (0x01 << 28)
170#define SBC_IDE_MDMA1_TCSH (0x05 << 24)
171#define SBC_IDE_MDMA1_TCSOFF (0x05 << 20)
172#define SBC_IDE_MDMA1_TWP (0x0F << 14)
173#define SBC_IDE_MDMA1_TCSW (0x05 << 10)
174#define SBC_IDE_MDMA1_TPM (0x00 << 6)
175#define SBC_IDE_MDMA1_TA (0x15 << 0)
176/* Timing parameters MDMA mode 2 */
177#define SBC_IDE_MDMA2_TCSOE (0x04 << 29)
178#define SBC_IDE_MDMA2_TOECS (0x01 << 26)
179#define SBC_IDE_MDMA2_TWCS (0x01 << 28)
180#define SBC_IDE_MDMA2_TCSH (0x04 << 24)
181#define SBC_IDE_MDMA2_TCSOFF (0x04 << 20)
182#define SBC_IDE_MDMA2_TWP (0x0D << 14)
183#define SBC_IDE_MDMA2_TCSW (0x04 << 10)
184#define SBC_IDE_MDMA2_TPM (0x00 << 6)
185#define SBC_IDE_MDMA2_TA (0x12 << 0)
186
187#define SBC_IDE_TIMING(mode) \
188 (SBC_IDE_##mode##_TWCS | \
189 SBC_IDE_##mode##_TCSH | \
190 SBC_IDE_##mode##_TCSOFF | \
191 SBC_IDE_##mode##_TWP | \
192 SBC_IDE_##mode##_TCSW | \
193 SBC_IDE_##mode##_TPM | \
194 SBC_IDE_##mode##_TA)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
deleted file mode 100644
index 892b7f168eb4..000000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ /dev/null
@@ -1,505 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2004 Embedded Edge, LLC
7 * dan@embeddededge.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30/* Specifics for the Au1xxx Programmable Serial Controllers, first
31 * seen in the AU1550 part.
32 */
33#ifndef _AU1000_PSC_H_
34#define _AU1000_PSC_H_
35
36/* The PSC base addresses. */
37#ifdef CONFIG_SOC_AU1550
38#define PSC0_BASE_ADDR 0xb1a00000
39#define PSC1_BASE_ADDR 0xb1b00000
40#define PSC2_BASE_ADDR 0xb0a00000
41#define PSC3_BASE_ADDR 0xb0b00000
42#endif
43
44#ifdef CONFIG_SOC_AU1200
45#define PSC0_BASE_ADDR 0xb1a00000
46#define PSC1_BASE_ADDR 0xb1b00000
47#endif
48
49/*
50 * The PSC select and control registers are common to all protocols.
51 */
52#define PSC_SEL_OFFSET 0x00000000
53#define PSC_CTRL_OFFSET 0x00000004
54
55#define PSC_SEL_CLK_MASK (3 << 4)
56#define PSC_SEL_CLK_INTCLK (0 << 4)
57#define PSC_SEL_CLK_EXTCLK (1 << 4)
58#define PSC_SEL_CLK_SERCLK (2 << 4)
59
60#define PSC_SEL_PS_MASK 0x00000007
61#define PSC_SEL_PS_DISABLED 0
62#define PSC_SEL_PS_SPIMODE 2
63#define PSC_SEL_PS_I2SMODE 3
64#define PSC_SEL_PS_AC97MODE 4
65#define PSC_SEL_PS_SMBUSMODE 5
66
67#define PSC_CTRL_DISABLE 0
68#define PSC_CTRL_SUSPEND 2
69#define PSC_CTRL_ENABLE 3
70
71/* AC97 Registers. */
72#define PSC_AC97CFG_OFFSET 0x00000008
73#define PSC_AC97MSK_OFFSET 0x0000000c
74#define PSC_AC97PCR_OFFSET 0x00000010
75#define PSC_AC97STAT_OFFSET 0x00000014
76#define PSC_AC97EVNT_OFFSET 0x00000018
77#define PSC_AC97TXRX_OFFSET 0x0000001c
78#define PSC_AC97CDC_OFFSET 0x00000020
79#define PSC_AC97RST_OFFSET 0x00000024
80#define PSC_AC97GPO_OFFSET 0x00000028
81#define PSC_AC97GPI_OFFSET 0x0000002c
82
83#define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET)
84#define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET)
85#define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
86#define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
87#define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
88#define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
89#define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
90#define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
91#define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
92#define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
93#define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
94#define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
95
96/* AC97 Config Register. */
97#define PSC_AC97CFG_RT_MASK (3 << 30)
98#define PSC_AC97CFG_RT_FIFO1 (0 << 30)
99#define PSC_AC97CFG_RT_FIFO2 (1 << 30)
100#define PSC_AC97CFG_RT_FIFO4 (2 << 30)
101#define PSC_AC97CFG_RT_FIFO8 (3 << 30)
102
103#define PSC_AC97CFG_TT_MASK (3 << 28)
104#define PSC_AC97CFG_TT_FIFO1 (0 << 28)
105#define PSC_AC97CFG_TT_FIFO2 (1 << 28)
106#define PSC_AC97CFG_TT_FIFO4 (2 << 28)
107#define PSC_AC97CFG_TT_FIFO8 (3 << 28)
108
109#define PSC_AC97CFG_DD_DISABLE (1 << 27)
110#define PSC_AC97CFG_DE_ENABLE (1 << 26)
111#define PSC_AC97CFG_SE_ENABLE (1 << 25)
112
113#define PSC_AC97CFG_LEN_MASK (0xf << 21)
114#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
115#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
116#define PSC_AC97CFG_GE_ENABLE (1)
117
118/* Enable slots 3-12. */
119#define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11))
120#define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1))
121
122/*
123 * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
124 * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the
125 * arithmetic in the macro.
126 */
127#define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21)
128#define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2)
129
130/* AC97 Mask Register. */
131#define PSC_AC97MSK_GR (1 << 25)
132#define PSC_AC97MSK_CD (1 << 24)
133#define PSC_AC97MSK_RR (1 << 13)
134#define PSC_AC97MSK_RO (1 << 12)
135#define PSC_AC97MSK_RU (1 << 11)
136#define PSC_AC97MSK_TR (1 << 10)
137#define PSC_AC97MSK_TO (1 << 9)
138#define PSC_AC97MSK_TU (1 << 8)
139#define PSC_AC97MSK_RD (1 << 5)
140#define PSC_AC97MSK_TD (1 << 4)
141#define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
142 PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
143 PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
144 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
145 PSC_AC97MSK_RD | PSC_AC97MSK_TD)
146
147/* AC97 Protocol Control Register. */
148#define PSC_AC97PCR_RC (1 << 6)
149#define PSC_AC97PCR_RP (1 << 5)
150#define PSC_AC97PCR_RS (1 << 4)
151#define PSC_AC97PCR_TC (1 << 2)
152#define PSC_AC97PCR_TP (1 << 1)
153#define PSC_AC97PCR_TS (1 << 0)
154
155/* AC97 Status register (read only). */
156#define PSC_AC97STAT_CB (1 << 26)
157#define PSC_AC97STAT_CP (1 << 25)
158#define PSC_AC97STAT_CR (1 << 24)
159#define PSC_AC97STAT_RF (1 << 13)
160#define PSC_AC97STAT_RE (1 << 12)
161#define PSC_AC97STAT_RR (1 << 11)
162#define PSC_AC97STAT_TF (1 << 10)
163#define PSC_AC97STAT_TE (1 << 9)
164#define PSC_AC97STAT_TR (1 << 8)
165#define PSC_AC97STAT_RB (1 << 5)
166#define PSC_AC97STAT_TB (1 << 4)
167#define PSC_AC97STAT_DI (1 << 2)
168#define PSC_AC97STAT_DR (1 << 1)
169#define PSC_AC97STAT_SR (1 << 0)
170
171/* AC97 Event Register. */
172#define PSC_AC97EVNT_GR (1 << 25)
173#define PSC_AC97EVNT_CD (1 << 24)
174#define PSC_AC97EVNT_RR (1 << 13)
175#define PSC_AC97EVNT_RO (1 << 12)
176#define PSC_AC97EVNT_RU (1 << 11)
177#define PSC_AC97EVNT_TR (1 << 10)
178#define PSC_AC97EVNT_TO (1 << 9)
179#define PSC_AC97EVNT_TU (1 << 8)
180#define PSC_AC97EVNT_RD (1 << 5)
181#define PSC_AC97EVNT_TD (1 << 4)
182
183/* CODEC Command Register. */
184#define PSC_AC97CDC_RD (1 << 25)
185#define PSC_AC97CDC_ID_MASK (3 << 23)
186#define PSC_AC97CDC_INDX_MASK (0x7f << 16)
187#define PSC_AC97CDC_ID(x) (((x) & 0x03) << 23)
188#define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16)
189
190/* AC97 Reset Control Register. */
191#define PSC_AC97RST_RST (1 << 1)
192#define PSC_AC97RST_SNC (1 << 0)
193
194/* PSC in I2S Mode. */
195typedef struct psc_i2s {
196 u32 psc_sel;
197 u32 psc_ctrl;
198 u32 psc_i2scfg;
199 u32 psc_i2smsk;
200 u32 psc_i2spcr;
201 u32 psc_i2sstat;
202 u32 psc_i2sevent;
203 u32 psc_i2stxrx;
204 u32 psc_i2sudf;
205} psc_i2s_t;
206
207#define PSC_I2SCFG_OFFSET 0x08
208#define PSC_I2SMASK_OFFSET 0x0C
209#define PSC_I2SPCR_OFFSET 0x10
210#define PSC_I2SSTAT_OFFSET 0x14
211#define PSC_I2SEVENT_OFFSET 0x18
212#define PSC_I2SRXTX_OFFSET 0x1C
213#define PSC_I2SUDF_OFFSET 0x20
214
215/* I2S Config Register. */
216#define PSC_I2SCFG_RT_MASK (3 << 30)
217#define PSC_I2SCFG_RT_FIFO1 (0 << 30)
218#define PSC_I2SCFG_RT_FIFO2 (1 << 30)
219#define PSC_I2SCFG_RT_FIFO4 (2 << 30)
220#define PSC_I2SCFG_RT_FIFO8 (3 << 30)
221
222#define PSC_I2SCFG_TT_MASK (3 << 28)
223#define PSC_I2SCFG_TT_FIFO1 (0 << 28)
224#define PSC_I2SCFG_TT_FIFO2 (1 << 28)
225#define PSC_I2SCFG_TT_FIFO4 (2 << 28)
226#define PSC_I2SCFG_TT_FIFO8 (3 << 28)
227
228#define PSC_I2SCFG_DD_DISABLE (1 << 27)
229#define PSC_I2SCFG_DE_ENABLE (1 << 26)
230#define PSC_I2SCFG_SET_WS(x) (((((x) / 2) - 1) & 0x7f) << 16)
231#define PSC_I2SCFG_WS(n) ((n & 0xFF) << 16)
232#define PSC_I2SCFG_WS_MASK (PSC_I2SCFG_WS(0x3F))
233#define PSC_I2SCFG_WI (1 << 15)
234
235#define PSC_I2SCFG_DIV_MASK (3 << 13)
236#define PSC_I2SCFG_DIV2 (0 << 13)
237#define PSC_I2SCFG_DIV4 (1 << 13)
238#define PSC_I2SCFG_DIV8 (2 << 13)
239#define PSC_I2SCFG_DIV16 (3 << 13)
240
241#define PSC_I2SCFG_BI (1 << 12)
242#define PSC_I2SCFG_BUF (1 << 11)
243#define PSC_I2SCFG_MLJ (1 << 10)
244#define PSC_I2SCFG_XM (1 << 9)
245
246/* The word length equation is simply LEN+1. */
247#define PSC_I2SCFG_SET_LEN(x) ((((x) - 1) & 0x1f) << 4)
248#define PSC_I2SCFG_GET_LEN(x) ((((x) >> 4) & 0x1f) + 1)
249
250#define PSC_I2SCFG_LB (1 << 2)
251#define PSC_I2SCFG_MLF (1 << 1)
252#define PSC_I2SCFG_MS (1 << 0)
253
254/* I2S Mask Register. */
255#define PSC_I2SMSK_RR (1 << 13)
256#define PSC_I2SMSK_RO (1 << 12)
257#define PSC_I2SMSK_RU (1 << 11)
258#define PSC_I2SMSK_TR (1 << 10)
259#define PSC_I2SMSK_TO (1 << 9)
260#define PSC_I2SMSK_TU (1 << 8)
261#define PSC_I2SMSK_RD (1 << 5)
262#define PSC_I2SMSK_TD (1 << 4)
263#define PSC_I2SMSK_ALLMASK (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
264 PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
265 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
266 PSC_I2SMSK_RD | PSC_I2SMSK_TD)
267
268/* I2S Protocol Control Register. */
269#define PSC_I2SPCR_RC (1 << 6)
270#define PSC_I2SPCR_RP (1 << 5)
271#define PSC_I2SPCR_RS (1 << 4)
272#define PSC_I2SPCR_TC (1 << 2)
273#define PSC_I2SPCR_TP (1 << 1)
274#define PSC_I2SPCR_TS (1 << 0)
275
276/* I2S Status register (read only). */
277#define PSC_I2SSTAT_RF (1 << 13)
278#define PSC_I2SSTAT_RE (1 << 12)
279#define PSC_I2SSTAT_RR (1 << 11)
280#define PSC_I2SSTAT_TF (1 << 10)
281#define PSC_I2SSTAT_TE (1 << 9)
282#define PSC_I2SSTAT_TR (1 << 8)
283#define PSC_I2SSTAT_RB (1 << 5)
284#define PSC_I2SSTAT_TB (1 << 4)
285#define PSC_I2SSTAT_DI (1 << 2)
286#define PSC_I2SSTAT_DR (1 << 1)
287#define PSC_I2SSTAT_SR (1 << 0)
288
289/* I2S Event Register. */
290#define PSC_I2SEVNT_RR (1 << 13)
291#define PSC_I2SEVNT_RO (1 << 12)
292#define PSC_I2SEVNT_RU (1 << 11)
293#define PSC_I2SEVNT_TR (1 << 10)
294#define PSC_I2SEVNT_TO (1 << 9)
295#define PSC_I2SEVNT_TU (1 << 8)
296#define PSC_I2SEVNT_RD (1 << 5)
297#define PSC_I2SEVNT_TD (1 << 4)
298
299/* PSC in SPI Mode. */
300typedef struct psc_spi {
301 u32 psc_sel;
302 u32 psc_ctrl;
303 u32 psc_spicfg;
304 u32 psc_spimsk;
305 u32 psc_spipcr;
306 u32 psc_spistat;
307 u32 psc_spievent;
308 u32 psc_spitxrx;
309} psc_spi_t;
310
311/* SPI Config Register. */
312#define PSC_SPICFG_RT_MASK (3 << 30)
313#define PSC_SPICFG_RT_FIFO1 (0 << 30)
314#define PSC_SPICFG_RT_FIFO2 (1 << 30)
315#define PSC_SPICFG_RT_FIFO4 (2 << 30)
316#define PSC_SPICFG_RT_FIFO8 (3 << 30)
317
318#define PSC_SPICFG_TT_MASK (3 << 28)
319#define PSC_SPICFG_TT_FIFO1 (0 << 28)
320#define PSC_SPICFG_TT_FIFO2 (1 << 28)
321#define PSC_SPICFG_TT_FIFO4 (2 << 28)
322#define PSC_SPICFG_TT_FIFO8 (3 << 28)
323
324#define PSC_SPICFG_DD_DISABLE (1 << 27)
325#define PSC_SPICFG_DE_ENABLE (1 << 26)
326#define PSC_SPICFG_CLR_BAUD(x) ((x) & ~((0x3f) << 15))
327#define PSC_SPICFG_SET_BAUD(x) (((x) & 0x3f) << 15)
328
329#define PSC_SPICFG_SET_DIV(x) (((x) & 0x03) << 13)
330#define PSC_SPICFG_DIV2 0
331#define PSC_SPICFG_DIV4 1
332#define PSC_SPICFG_DIV8 2
333#define PSC_SPICFG_DIV16 3
334
335#define PSC_SPICFG_BI (1 << 12)
336#define PSC_SPICFG_PSE (1 << 11)
337#define PSC_SPICFG_CGE (1 << 10)
338#define PSC_SPICFG_CDE (1 << 9)
339
340#define PSC_SPICFG_CLR_LEN(x) ((x) & ~((0x1f) << 4))
341#define PSC_SPICFG_SET_LEN(x) (((x-1) & 0x1f) << 4)
342
343#define PSC_SPICFG_LB (1 << 3)
344#define PSC_SPICFG_MLF (1 << 1)
345#define PSC_SPICFG_MO (1 << 0)
346
347/* SPI Mask Register. */
348#define PSC_SPIMSK_MM (1 << 16)
349#define PSC_SPIMSK_RR (1 << 13)
350#define PSC_SPIMSK_RO (1 << 12)
351#define PSC_SPIMSK_RU (1 << 11)
352#define PSC_SPIMSK_TR (1 << 10)
353#define PSC_SPIMSK_TO (1 << 9)
354#define PSC_SPIMSK_TU (1 << 8)
355#define PSC_SPIMSK_SD (1 << 5)
356#define PSC_SPIMSK_MD (1 << 4)
357#define PSC_SPIMSK_ALLMASK (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
358 PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
359 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
360 PSC_SPIMSK_MD)
361
362/* SPI Protocol Control Register. */
363#define PSC_SPIPCR_RC (1 << 6)
364#define PSC_SPIPCR_SP (1 << 5)
365#define PSC_SPIPCR_SS (1 << 4)
366#define PSC_SPIPCR_TC (1 << 2)
367#define PSC_SPIPCR_MS (1 << 0)
368
369/* SPI Status register (read only). */
370#define PSC_SPISTAT_RF (1 << 13)
371#define PSC_SPISTAT_RE (1 << 12)
372#define PSC_SPISTAT_RR (1 << 11)
373#define PSC_SPISTAT_TF (1 << 10)
374#define PSC_SPISTAT_TE (1 << 9)
375#define PSC_SPISTAT_TR (1 << 8)
376#define PSC_SPISTAT_SB (1 << 5)
377#define PSC_SPISTAT_MB (1 << 4)
378#define PSC_SPISTAT_DI (1 << 2)
379#define PSC_SPISTAT_DR (1 << 1)
380#define PSC_SPISTAT_SR (1 << 0)
381
382/* SPI Event Register. */
383#define PSC_SPIEVNT_MM (1 << 16)
384#define PSC_SPIEVNT_RR (1 << 13)
385#define PSC_SPIEVNT_RO (1 << 12)
386#define PSC_SPIEVNT_RU (1 << 11)
387#define PSC_SPIEVNT_TR (1 << 10)
388#define PSC_SPIEVNT_TO (1 << 9)
389#define PSC_SPIEVNT_TU (1 << 8)
390#define PSC_SPIEVNT_SD (1 << 5)
391#define PSC_SPIEVNT_MD (1 << 4)
392
393/* Transmit register control. */
394#define PSC_SPITXRX_LC (1 << 29)
395#define PSC_SPITXRX_SR (1 << 28)
396
397/* PSC in SMBus (I2C) Mode. */
398typedef struct psc_smb {
399 u32 psc_sel;
400 u32 psc_ctrl;
401 u32 psc_smbcfg;
402 u32 psc_smbmsk;
403 u32 psc_smbpcr;
404 u32 psc_smbstat;
405 u32 psc_smbevnt;
406 u32 psc_smbtxrx;
407 u32 psc_smbtmr;
408} psc_smb_t;
409
410/* SMBus Config Register. */
411#define PSC_SMBCFG_RT_MASK (3 << 30)
412#define PSC_SMBCFG_RT_FIFO1 (0 << 30)
413#define PSC_SMBCFG_RT_FIFO2 (1 << 30)
414#define PSC_SMBCFG_RT_FIFO4 (2 << 30)
415#define PSC_SMBCFG_RT_FIFO8 (3 << 30)
416
417#define PSC_SMBCFG_TT_MASK (3 << 28)
418#define PSC_SMBCFG_TT_FIFO1 (0 << 28)
419#define PSC_SMBCFG_TT_FIFO2 (1 << 28)
420#define PSC_SMBCFG_TT_FIFO4 (2 << 28)
421#define PSC_SMBCFG_TT_FIFO8 (3 << 28)
422
423#define PSC_SMBCFG_DD_DISABLE (1 << 27)
424#define PSC_SMBCFG_DE_ENABLE (1 << 26)
425
426#define PSC_SMBCFG_SET_DIV(x) (((x) & 0x03) << 13)
427#define PSC_SMBCFG_DIV2 0
428#define PSC_SMBCFG_DIV4 1
429#define PSC_SMBCFG_DIV8 2
430#define PSC_SMBCFG_DIV16 3
431
432#define PSC_SMBCFG_GCE (1 << 9)
433#define PSC_SMBCFG_SFM (1 << 8)
434
435#define PSC_SMBCFG_SET_SLV(x) (((x) & 0x7f) << 1)
436
437/* SMBus Mask Register. */
438#define PSC_SMBMSK_DN (1 << 30)
439#define PSC_SMBMSK_AN (1 << 29)
440#define PSC_SMBMSK_AL (1 << 28)
441#define PSC_SMBMSK_RR (1 << 13)
442#define PSC_SMBMSK_RO (1 << 12)
443#define PSC_SMBMSK_RU (1 << 11)
444#define PSC_SMBMSK_TR (1 << 10)
445#define PSC_SMBMSK_TO (1 << 9)
446#define PSC_SMBMSK_TU (1 << 8)
447#define PSC_SMBMSK_SD (1 << 5)
448#define PSC_SMBMSK_MD (1 << 4)
449#define PSC_SMBMSK_ALLMASK (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
450 PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
451 PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
452 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
453 PSC_SMBMSK_MD)
454
455/* SMBus Protocol Control Register. */
456#define PSC_SMBPCR_DC (1 << 2)
457#define PSC_SMBPCR_MS (1 << 0)
458
459/* SMBus Status register (read only). */
460#define PSC_SMBSTAT_BB (1 << 28)
461#define PSC_SMBSTAT_RF (1 << 13)
462#define PSC_SMBSTAT_RE (1 << 12)
463#define PSC_SMBSTAT_RR (1 << 11)
464#define PSC_SMBSTAT_TF (1 << 10)
465#define PSC_SMBSTAT_TE (1 << 9)
466#define PSC_SMBSTAT_TR (1 << 8)
467#define PSC_SMBSTAT_SB (1 << 5)
468#define PSC_SMBSTAT_MB (1 << 4)
469#define PSC_SMBSTAT_DI (1 << 2)
470#define PSC_SMBSTAT_DR (1 << 1)
471#define PSC_SMBSTAT_SR (1 << 0)
472
473/* SMBus Event Register. */
474#define PSC_SMBEVNT_DN (1 << 30)
475#define PSC_SMBEVNT_AN (1 << 29)
476#define PSC_SMBEVNT_AL (1 << 28)
477#define PSC_SMBEVNT_RR (1 << 13)
478#define PSC_SMBEVNT_RO (1 << 12)
479#define PSC_SMBEVNT_RU (1 << 11)
480#define PSC_SMBEVNT_TR (1 << 10)
481#define PSC_SMBEVNT_TO (1 << 9)
482#define PSC_SMBEVNT_TU (1 << 8)
483#define PSC_SMBEVNT_SD (1 << 5)
484#define PSC_SMBEVNT_MD (1 << 4)
485#define PSC_SMBEVNT_ALLCLR (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
486 PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
487 PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
488 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
489 PSC_SMBEVNT_MD)
490
491/* Transmit register control. */
492#define PSC_SMBTXRX_RSR (1 << 28)
493#define PSC_SMBTXRX_STP (1 << 29)
494#define PSC_SMBTXRX_DATAMASK 0xff
495
496/* SMBus protocol timers register. */
497#define PSC_SMBTMR_SET_TH(x) (((x) & 0x03) << 30)
498#define PSC_SMBTMR_SET_PS(x) (((x) & 0x1f) << 25)
499#define PSC_SMBTMR_SET_PU(x) (((x) & 0x1f) << 20)
500#define PSC_SMBTMR_SET_SH(x) (((x) & 0x1f) << 15)
501#define PSC_SMBTMR_SET_SU(x) (((x) & 0x1f) << 10)
502#define PSC_SMBTMR_SET_CL(x) (((x) & 0x1f) << 5)
503#define PSC_SMBTMR_SET_CH(x) (((x) & 0x1f) << 0)
504
505#endif /* _AU1000_PSC_H_ */
diff --git a/include/asm-mips/mach-au1x00/gpio.h b/include/asm-mips/mach-au1x00/gpio.h
deleted file mode 100644
index 2dc61e009a08..000000000000
--- a/include/asm-mips/mach-au1x00/gpio.h
+++ /dev/null
@@ -1,69 +0,0 @@
1#ifndef _AU1XXX_GPIO_H_
2#define _AU1XXX_GPIO_H_
3
4#include <linux/types.h>
5
6#define AU1XXX_GPIO_BASE 200
7
8struct au1x00_gpio2 {
9 u32 dir;
10 u32 reserved;
11 u32 output;
12 u32 pinstate;
13 u32 inten;
14 u32 enable;
15};
16
17extern int au1xxx_gpio_get_value(unsigned gpio);
18extern void au1xxx_gpio_set_value(unsigned gpio, int value);
19extern int au1xxx_gpio_direction_input(unsigned gpio);
20extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
21
22
23/* Wrappers for the arch-neutral GPIO API */
24
25static inline int gpio_request(unsigned gpio, const char *label)
26{
27 /* Not yet implemented */
28 return 0;
29}
30
31static inline void gpio_free(unsigned gpio)
32{
33 /* Not yet implemented */
34}
35
36static inline int gpio_direction_input(unsigned gpio)
37{
38 return au1xxx_gpio_direction_input(gpio);
39}
40
41static inline int gpio_direction_output(unsigned gpio, int value)
42{
43 return au1xxx_gpio_direction_output(gpio, value);
44}
45
46static inline int gpio_get_value(unsigned gpio)
47{
48 return au1xxx_gpio_get_value(gpio);
49}
50
51static inline void gpio_set_value(unsigned gpio, int value)
52{
53 au1xxx_gpio_set_value(gpio, value);
54}
55
56static inline int gpio_to_irq(unsigned gpio)
57{
58 return gpio;
59}
60
61static inline int irq_to_gpio(unsigned irq)
62{
63 return irq;
64}
65
66/* For cansleep */
67#include <asm-generic/gpio.h>
68
69#endif /* _AU1XXX_GPIO_H_ */
diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h
deleted file mode 100644
index 364cea2dc71f..000000000000
--- a/include/asm-mips/mach-au1x00/ioremap.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * include/asm-mips/mach-au1x00/ioremap.h
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifndef __ASM_MACH_AU1X00_IOREMAP_H
10#define __ASM_MACH_AU1X00_IOREMAP_H
11
12#include <linux/types.h>
13
14#ifdef CONFIG_64BIT_PHYS_ADDR
15extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
16#else
17static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
18{
19 return phys_addr;
20}
21#endif
22
23/*
24 * Allow physical addresses to be fixed up to help 36-bit peripherals.
25 */
26static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
27{
28 return __fixup_bigphys_addr(phys_addr, size);
29}
30
31static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
32 unsigned long flags)
33{
34 return NULL;
35}
36
37static inline int plat_iounmap(const volatile void __iomem *addr)
38{
39 return 0;
40}
41
42#endif /* __ASM_MACH_AU1X00_IOREMAP_H */
diff --git a/include/asm-mips/mach-au1x00/prom.h b/include/asm-mips/mach-au1x00/prom.h
deleted file mode 100644
index e38715577c51..000000000000
--- a/include/asm-mips/mach-au1x00/prom.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __AU1X00_PROM_H
2#define __AU1X00_PROM_H
3
4extern int prom_argc;
5extern char **prom_argv;
6extern char **prom_envp;
7
8extern void prom_init_cmdline(void);
9extern char *prom_getcmdline(void);
10extern char *prom_getenv(char *envname);
11extern int prom_get_ethernet_addr(char *ethernet_addr);
12
13#endif
diff --git a/include/asm-mips/mach-au1x00/war.h b/include/asm-mips/mach-au1x00/war.h
deleted file mode 100644
index dd57d03d68ba..000000000000
--- a/include/asm-mips/mach-au1x00/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H
9#define __ASM_MIPS_MACH_AU1X00_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 14:49:37 -0500