Base Au1200 2.6 support.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 497 insertions, 59 deletions

diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 148bae2fa7d3..28b04a5f67cf 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -162,27 +162,355 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
 #endif
 
-/* SDRAM Controller */
+/*
+ * SDRAM Register Offsets
+ */
 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
-#define MEM_SDMODE0                0xB4000000
-#define MEM_SDMODE1                0xB4000004
-#define MEM_SDMODE2                0xB4000008
+#define MEM_SDMODE0             (0x0000)
+#define MEM_SDMODE1             (0x0004)
+#define MEM_SDMODE2             (0x0008)
+#define MEM_SDADDR0             (0x000C)
+#define MEM_SDADDR1             (0x0010)
+#define MEM_SDADDR2             (0x0014)
+#define MEM_SDREFCFG    (0x0018)
+#define MEM_SDPRECMD    (0x001C)
+#define MEM_SDAUTOREF   (0x0020)
+#define MEM_SDWRMD0             (0x0024)
+#define MEM_SDWRMD1             (0x0028)
+#define MEM_SDWRMD2             (0x002C)
+#define MEM_SDSLEEP             (0x0030)
+#define MEM_SDSMCKE             (0x0034)
+
+#ifndef ASSEMBLER
+/*typedef volatile struct
+{
+        uint32 sdmode0;
+        uint32 sdmode1;
+        uint32 sdmode2;
+        uint32 sdaddr0;
+        uint32 sdaddr1;
+        uint32 sdaddr2;
+        uint32 sdrefcfg;
+        uint32 sdautoref;
+        uint32 sdwrmd0;
+        uint32 sdwrmd1;
+        uint32 sdwrmd2;
+        uint32 sdsleep;
+        uint32 sdsmcke;
+
+} AU1X00_SDRAM;*/
+#endif
+
+/*
+ * MEM_SDMODE register content definitions
+ */
+#define MEM_SDMODE_F            (1<<22)
+#define MEM_SDMODE_SR           (1<<21)
+#define MEM_SDMODE_BS           (1<<20)
+#define MEM_SDMODE_RS           (3<<18)
+#define MEM_SDMODE_CS           (7<<15)
+#define MEM_SDMODE_TRAS         (15<<11)
+#define MEM_SDMODE_TMRD         (3<<9)
+#define MEM_SDMODE_TWR          (3<<7)
+#define MEM_SDMODE_TRP          (3<<5)
+#define MEM_SDMODE_TRCD         (3<<3)
+#define MEM_SDMODE_TCL          (7<<0)
+
+#define MEM_SDMODE_BS_2Bank     (0<<20)
+#define MEM_SDMODE_BS_4Bank     (1<<20)
+#define MEM_SDMODE_RS_11Row     (0<<18)
+#define MEM_SDMODE_RS_12Row     (1<<18)
+#define MEM_SDMODE_RS_13Row     (2<<18)
+#define MEM_SDMODE_RS_N(N)      ((N)<<18)
+#define MEM_SDMODE_CS_7Col      (0<<15)
+#define MEM_SDMODE_CS_8Col      (1<<15)
+#define MEM_SDMODE_CS_9Col      (2<<15)
+#define MEM_SDMODE_CS_10Col     (3<<15)
+#define MEM_SDMODE_CS_11Col     (4<<15)
+#define MEM_SDMODE_CS_N(N)              ((N)<<15)
+#define MEM_SDMODE_TRAS_N(N)    ((N)<<11)
+#define MEM_SDMODE_TMRD_N(N)    ((N)<<9)
+#define MEM_SDMODE_TWR_N(N)             ((N)<<7)
+#define MEM_SDMODE_TRP_N(N)             ((N)<<5)
+#define MEM_SDMODE_TRCD_N(N)    ((N)<<3)
+#define MEM_SDMODE_TCL_N(N)             ((N)<<0)
+
+/*
+ * MEM_SDADDR register contents definitions
+ */
+#define MEM_SDADDR_E                    (1<<20)
+#define MEM_SDADDR_CSBA                 (0x03FF<<10)
+#define MEM_SDADDR_CSMASK               (0x03FF<<0)
+#define MEM_SDADDR_CSBA_N(N)    ((N)&(0x03FF<<22)>>12)
+#define MEM_SDADDR_CSMASK_N(N)  ((N)&(0x03FF<<22)>>22)
+
+/*
+ * MEM_SDREFCFG register content definitions
+ */
+#define MEM_SDREFCFG_TRC                (15<<28)
+#define MEM_SDREFCFG_TRPM               (3<<26)
+#define MEM_SDREFCFG_E                  (1<<25)
+#define MEM_SDREFCFG_RE                 (0x1ffffff<<0)
+#define MEM_SDREFCFG_TRC_N(N)   ((N)<<MEM_SDREFCFG_TRC)
+#define MEM_SDREFCFG_TRPM_N(N)  ((N)<<MEM_SDREFCFG_TRPM)
+#define MEM_SDREFCFG_REF_N(N)   (N)
+#endif
 
-#define MEM_SDADDR0                0xB400000C
-#define MEM_SDADDR1                0xB4000010
-#define MEM_SDADDR2                0xB4000014
+/***********************************************************************/
 
-#define MEM_SDREFCFG               0xB4000018
-#define MEM_SDPRECMD               0xB400001C
-#define MEM_SDAUTOREF              0xB4000020
+/*
+ * Au1550 SDRAM Register Offsets
+ */
 
-#define MEM_SDWRMD0                0xB4000024
-#define MEM_SDWRMD1                0xB4000028
-#define MEM_SDWRMD2                0xB400002C
+/***********************************************************************/
 
-#define MEM_SDSLEEP                0xB4000030
-#define MEM_SDSMCKE                0xB4000034
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+#define MEM_SDMODE0             (0x0800)
+#define MEM_SDMODE1             (0x0808)
+#define MEM_SDMODE2             (0x0810)
+#define MEM_SDADDR0             (0x0820)
+#define MEM_SDADDR1             (0x0828)
+#define MEM_SDADDR2             (0x0830)
+#define MEM_SDCONFIGA   (0x0840)
+#define MEM_SDCONFIGB   (0x0848)
+#define MEM_SDSTAT              (0x0850)
+#define MEM_SDERRADDR   (0x0858)
+#define MEM_SDSTRIDE0   (0x0860)
+#define MEM_SDSTRIDE1   (0x0868)
+#define MEM_SDSTRIDE2   (0x0870)
+#define MEM_SDWRMD0             (0x0880)
+#define MEM_SDWRMD1             (0x0888)
+#define MEM_SDWRMD2             (0x0890)
+#define MEM_SDPRECMD    (0x08C0)
+#define MEM_SDAUTOREF   (0x08C8)
+#define MEM_SDSREF              (0x08D0)
+#define MEM_SDSLEEP             MEM_SDSREF
+
+#ifndef ASSEMBLER
+/*typedef volatile struct
+{
+        uint32 sdmode0;
+        uint32 reserved0;
+        uint32 sdmode1;
+        uint32 reserved1;
+        uint32 sdmode2;
+        uint32 reserved2[3];
+        uint32 sdaddr0;
+        uint32 reserved3;
+        uint32 sdaddr1;
+        uint32 reserved4;
+        uint32 sdaddr2;
+        uint32 reserved5[3];
+        uint32 sdconfiga;
+        uint32 reserved6;
+        uint32 sdconfigb;
+        uint32 reserved7;
+        uint32 sdstat;
+        uint32 reserved8;
+        uint32 sderraddr;
+        uint32 reserved9;
+        uint32 sdstride0;
+        uint32 reserved10;
+        uint32 sdstride1;
+        uint32 reserved11;
+        uint32 sdstride2;
+        uint32 reserved12[3];
+        uint32 sdwrmd0;
+        uint32 reserved13;
+        uint32 sdwrmd1;
+        uint32 reserved14;
+        uint32 sdwrmd2;
+        uint32 reserved15[11];
+        uint32 sdprecmd;
+        uint32 reserved16;
+        uint32 sdautoref;
+        uint32 reserved17;
+        uint32 sdsref;
+
+} AU1550_SDRAM;*/
 #endif
+#endif
+
+/*
+ * Physical base addresses for integrated peripherals
+ */
+
+#ifdef CONFIG_SOC_AU1000
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define IRDA_PHYS_ADDR          0x10300000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MAC1_PHYS_ADDR          0x10510000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART2_PHYS_ADDR         0x11300000
+#define UART3_PHYS_ADDR         0x11400000
+#define SSI0_PHYS_ADDR          0x11600000
+#define SSI1_PHYS_ADDR          0x11680000
+#define SYS_PHYS_ADDR           0x11900000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#endif
+
+/********************************************************************/
+
+#ifdef CONFIG_SOC_AU1500
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR           0x14005000
+#define MAC0_PHYS_ADDR          0x11500000
+#define MAC1_PHYS_ADDR          0x11510000
+#define MACEN_PHYS_ADDR         0x11520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define PCI_MEM_PHYS_ADDR     0x400000000
+#define PCI_IO_PHYS_ADDR      0x500000000
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#endif
+
+/********************************************************************/
+
+#ifdef CONFIG_SOC_AU1100
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define DMA0_PHYS_ADDR          0x14002000
+#define DMA1_PHYS_ADDR          0x14002100
+#define DMA2_PHYS_ADDR          0x14002200
+#define DMA3_PHYS_ADDR          0x14002300
+#define DMA4_PHYS_ADDR          0x14002400
+#define DMA5_PHYS_ADDR          0x14002500
+#define DMA6_PHYS_ADDR          0x14002600
+#define DMA7_PHYS_ADDR          0x14002700
+#define IC0_PHYS_ADDR           0x10400000
+#define SD0_PHYS_ADDR           0x10600000
+#define SD1_PHYS_ADDR           0x10680000
+#define IC1_PHYS_ADDR           0x11800000
+#define AC97_PHYS_ADDR          0x10000000
+#define USBH_PHYS_ADDR          0x10100000
+#define USBD_PHYS_ADDR          0x10200000
+#define IRDA_PHYS_ADDR          0x10300000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define I2S_PHYS_ADDR           0x11000000
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART3_PHYS_ADDR         0x11400000
+#define SSI0_PHYS_ADDR          0x11600000
+#define SSI1_PHYS_ADDR          0x11680000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define LCD_PHYS_ADDR           0x15000000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#endif
+
+/***********************************************************************/
+
+#ifdef CONFIG_SOC_AU1550
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define USBH_PHYS_ADDR          0x14020000
+#define USBD_PHYS_ADDR          0x10200000
+#define PCI_PHYS_ADDR           0x14005000
+#define MAC0_PHYS_ADDR          0x10500000
+#define MAC1_PHYS_ADDR          0x10510000
+#define MACEN_PHYS_ADDR         0x10520000
+#define MACDMA0_PHYS_ADDR       0x14004000
+#define MACDMA1_PHYS_ADDR       0x14004200
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define UART3_PHYS_ADDR         0x11400000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define DDMA_PHYS_ADDR          0x14002000
+#define PE_PHYS_ADDR            0x14008000
+#define PSC0_PHYS_ADDR          0x11A00000
+#define PSC1_PHYS_ADDR          0x11B00000
+#define PSC2_PHYS_ADDR          0x10A00000
+#define PSC3_PHYS_ADDR          0x10B00000
+#define PCI_MEM_PHYS_ADDR     0x400000000
+#define PCI_IO_PHYS_ADDR      0x500000000
+#define PCI_CONFIG0_PHYS_ADDR 0x600000000
+#define PCI_CONFIG1_PHYS_ADDR 0x680000000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#endif
+
+/***********************************************************************/
+
+#ifdef CONFIG_SOC_AU1200
+#define MEM_PHYS_ADDR           0x14000000
+#define STATIC_MEM_PHYS_ADDR    0x14001000
+#define AES_PHYS_ADDR           0x10300000
+#define CIM_PHYS_ADDR           0x14004000
+#define IC0_PHYS_ADDR           0x10400000
+#define IC1_PHYS_ADDR           0x11800000
+#define USBM_PHYS_ADDR          0x14020000
+#define USBH_PHYS_ADDR          0x14020100
+#define UART0_PHYS_ADDR         0x11100000
+#define UART1_PHYS_ADDR         0x11200000
+#define GPIO2_PHYS_ADDR         0x11700000
+#define SYS_PHYS_ADDR           0x11900000
+#define DDMA_PHYS_ADDR          0x14002000
+#define PSC0_PHYS_ADDR          0x11A00000
+#define PSC1_PHYS_ADDR          0x11B00000
+#define PCMCIA_IO_PHYS_ADDR   0xF00000000
+#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
+#define PCMCIA_MEM_PHYS_ADDR  0xF80000000
+#define SD0_PHYS_ADDR           0x10600000
+#define SD1_PHYS_ADDR           0x10680000
+#define LCD_PHYS_ADDR           0x15000000
+#define SWCNT_PHYS_ADDR         0x1110010C
+#define MAEFE_PHYS_ADDR         0x14012000
+#define MAEBE_PHYS_ADDR         0x14010000
+#endif
+
 
 /* Static Bus Controller */
 #define MEM_STCFG0                 0xB4001000
@@ -369,7 +697,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1000_MAC0_ENABLE       0xB0520000
 #define AU1000_MAC1_ENABLE       0xB0520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1000
+#endif /* CONFIG_SOC_AU1000 */
 
 /* Au1500 */
 #ifdef CONFIG_SOC_AU1500
@@ -440,7 +768,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1500_MAC0_ENABLE       0xB1520000
 #define AU1500_MAC1_ENABLE       0xB1520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1500
+#endif /* CONFIG_SOC_AU1500 */
 
 /* Au1100 */
 #ifdef CONFIG_SOC_AU1100
@@ -485,6 +813,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1000_GPIO_13            45
 #define AU1000_GPIO_14            46
 #define AU1000_GPIO_15            47
+#define AU1000_GPIO_16            48
+#define AU1000_GPIO_17            49
+#define AU1000_GPIO_18            50
+#define AU1000_GPIO_19            51
+#define AU1000_GPIO_20            52
+#define AU1000_GPIO_21            53
+#define AU1000_GPIO_22            54
+#define AU1000_GPIO_23            55
+#define AU1000_GPIO_24            56
+#define AU1000_GPIO_25            57
+#define AU1000_GPIO_26            58
+#define AU1000_GPIO_27            59
+#define AU1000_GPIO_28            60
+#define AU1000_GPIO_29            61
+#define AU1000_GPIO_30            62
+#define AU1000_GPIO_31            63
 
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
@@ -496,7 +840,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1100_ETH0_BASE          0xB0500000
 #define AU1100_MAC0_ENABLE       0xB0520000
 #define NUM_ETH_INTERFACES 1
-#endif // CONFIG_SOC_AU1100
+#endif /* CONFIG_SOC_AU1100 */
 
 #ifdef CONFIG_SOC_AU1550
 #define AU1550_UART0_INT          0
@@ -513,14 +857,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1550_PSC1_INT           11
 #define AU1550_PSC2_INT           12
 #define AU1550_PSC3_INT           13
-#define AU1550_TOY_INT                    14
-#define AU1550_TOY_MATCH0_INT     15
-#define AU1550_TOY_MATCH1_INT     16
-#define AU1550_TOY_MATCH2_INT     17
-#define AU1550_RTC_INT            18
-#define AU1550_RTC_MATCH0_INT     19
-#define AU1550_RTC_MATCH1_INT     20
-#define AU1550_RTC_MATCH2_INT     21
+#define AU1000_TOY_INT                    14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
 #define AU1550_NAND_INT           23
 #define AU1550_USB_DEV_REQ_INT    24
 #define AU1550_USB_DEV_SUS_INT    25
@@ -575,7 +919,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1550_MAC0_ENABLE       0xB0520000
 #define AU1550_MAC1_ENABLE       0xB0520004
 #define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1550
+#endif /* CONFIG_SOC_AU1550 */
 
 #ifdef CONFIG_SOC_AU1200
 #define AU1200_UART0_INT          0
@@ -592,14 +936,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1200_PSC1_INT           11
 #define AU1200_AES_INT            12
 #define AU1200_CAMERA_INT         13
-#define AU1200_TOY_INT                    14
-#define AU1200_TOY_MATCH0_INT     15
-#define AU1200_TOY_MATCH1_INT     16
-#define AU1200_TOY_MATCH2_INT     17
-#define AU1200_RTC_INT            18
-#define AU1200_RTC_MATCH0_INT     19
-#define AU1200_RTC_MATCH1_INT     20
-#define AU1200_RTC_MATCH2_INT     21
+#define AU1000_TOY_INT                    14
+#define AU1000_TOY_MATCH0_INT     15
+#define AU1000_TOY_MATCH1_INT     16
+#define AU1000_TOY_MATCH2_INT     17
+#define AU1000_RTC_INT            18
+#define AU1000_RTC_MATCH0_INT     19
+#define AU1000_RTC_MATCH1_INT     20
+#define AU1000_RTC_MATCH2_INT     21
 #define AU1200_NAND_INT           23
 #define AU1200_GPIO_204           24
 #define AU1200_GPIO_205           25
@@ -607,6 +951,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define AU1200_GPIO_207           27
 #define AU1200_GPIO_208_215       28 // Logical OR of 208:215
 #define AU1200_USB_INT            29
+#define AU1000_USB_HOST_INT               AU1200_USB_INT
 #define AU1200_LCD_INT            30
 #define AU1200_MAE_BOTH_INT       31
 #define AU1000_GPIO_0             32
@@ -645,21 +990,36 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define UART0_ADDR                0xB1100000
 #define UART1_ADDR                0xB1200000
 
-#define USB_OHCI_BASE             0x14020000 // phys addr for ioremap
-#define USB_HOST_CONFIG           0xB4027ffc
-
-// these are here for prototyping on au1550 (do not exist on au1200)
-#define AU1200_ETH0_BASE      0xB0500000
-#define AU1200_ETH1_BASE      0xB0510000
-#define AU1200_MAC0_ENABLE       0xB0520000
-#define AU1200_MAC1_ENABLE       0xB0520004
-#define NUM_ETH_INTERFACES 2
-#endif // CONFIG_SOC_AU1200
+#define USB_UOC_BASE              0x14020020
+#define USB_UOC_LEN               0x20
+#define USB_OHCI_BASE             0x14020100
+#define USB_OHCI_LEN              0x100
+#define USB_EHCI_BASE             0x14020200
+#define USB_EHCI_LEN              0x100
+#define USB_UDC_BASE              0x14022000
+#define USB_UDC_LEN               0x2000
+#define USB_MSR_BASE                      0xB4020000
+#define USB_MSR_MCFG              4
+#define USBMSRMCFG_OMEMEN         0
+#define USBMSRMCFG_OBMEN          1
+#define USBMSRMCFG_EMEMEN         2
+#define USBMSRMCFG_EBMEN          3
+#define USBMSRMCFG_DMEMEN         4
+#define USBMSRMCFG_DBMEN          5
+#define USBMSRMCFG_GMEMEN         6
+#define USBMSRMCFG_OHCCLKEN       16
+#define USBMSRMCFG_EHCCLKEN       17
+#define USBMSRMCFG_UDCCLKEN       18
+#define USBMSRMCFG_PHYPLLEN       19
+#define USBMSRMCFG_RDCOMB         30
+#define USBMSRMCFG_PFEN           31
+
+#endif /* CONFIG_SOC_AU1200 */
 
 #define AU1000_LAST_INTC0_INT     31
+#define AU1000_LAST_INTC1_INT     63
 #define AU1000_MAX_INTR           63
 
-
 /* Programmable Counters 0 and 1 */
 #define SYS_BASE                   0xB1900000
 #define SYS_COUNTER_CNTRL          (SYS_BASE + 0x14)
@@ -730,6 +1090,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
   #define I2S_CONTROL_D         (1<<1)
   #define I2S_CONTROL_CE        (1<<0)
 
+#ifndef CONFIG_SOC_AU1200
+
 /* USB Host Controller */
 #define USB_OHCI_LEN              0x00100000
 
@@ -775,6 +1137,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
   #define USBDEV_ENABLE (1<<1)
   #define USBDEV_CE     (1<<0)
 
+#endif /* !CONFIG_SOC_AU1200 */
+
 /* Ethernet Controllers  */
 
 /* 4 byte offsets from AU1000_ETH_BASE */
@@ -1173,6 +1537,37 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
   #define SYS_PF_PSC1_S1                (1 << 1)
   #define SYS_PF_MUST_BE_SET            ((1 << 5) | (1 << 2))
 
+/* Au1200 Only */
+#ifdef CONFIG_SOC_AU1200
+#define SYS_PINFUNC_DMA         (1<<31)
+#define SYS_PINFUNC_S0A         (1<<30)
+#define SYS_PINFUNC_S1A         (1<<29)
+#define SYS_PINFUNC_LP0         (1<<28)
+#define SYS_PINFUNC_LP1         (1<<27)
+#define SYS_PINFUNC_LD16        (1<<26)
+#define SYS_PINFUNC_LD8         (1<<25)
+#define SYS_PINFUNC_LD1         (1<<24)
+#define SYS_PINFUNC_LD0         (1<<23)
+#define SYS_PINFUNC_P1A         (3<<21)
+#define SYS_PINFUNC_P1B         (1<<20)
+#define SYS_PINFUNC_FS3         (1<<19)
+#define SYS_PINFUNC_P0A         (3<<17)
+#define SYS_PINFUNC_CS          (1<<16)
+#define SYS_PINFUNC_CIM         (1<<15)
+#define SYS_PINFUNC_P1C         (1<<14)
+#define SYS_PINFUNC_U1T         (1<<12)
+#define SYS_PINFUNC_U1R         (1<<11)
+#define SYS_PINFUNC_EX1         (1<<10)
+#define SYS_PINFUNC_EX0         (1<<9)
+#define SYS_PINFUNC_U0R         (1<<8)
+#define SYS_PINFUNC_MC          (1<<7)
+#define SYS_PINFUNC_S0B         (1<<6)
+#define SYS_PINFUNC_S0C         (1<<5)
+#define SYS_PINFUNC_P0B         (1<<4)
+#define SYS_PINFUNC_U0T         (1<<3)
+#define SYS_PINFUNC_S1B         (1<<2)
+#endif
+
 #define SYS_TRIOUTRD              0xB1900100
 #define SYS_TRIOUTCLR             0xB1900100
 #define SYS_OUTPUTRD              0xB1900108
@@ -1300,7 +1695,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
 #define SD1_XMIT_FIFO   0xB0680000
 #define SD1_RECV_FIFO   0xB0680004
 
-
 #if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
 /* Au1500 PCI Controller */
 #define Au1500_CFG_BASE           0xB4005000 // virtual, kseg0 addr
@@ -1363,36 +1757,77 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
                       _ctl_; })
 
 
-#else /* Au1000 and Au1100 */
+#else /* Au1000 and Au1100 and Au1200 */
 
 /* don't allow any legacy ports probing */
-#define IOPORT_RESOURCE_START 0x10000000;
+#define IOPORT_RESOURCE_START 0x10000000
 #define IOPORT_RESOURCE_END   0xffffffff
 #define IOMEM_RESOURCE_START  0x10000000
 #define IOMEM_RESOURCE_END    0xffffffff
 
-#ifdef CONFIG_MIPS_PB1000
-#define PCI_IO_START      0x10000000
-#define PCI_IO_END        0x1000ffff
-#define PCI_MEM_START     0x18000000
-#define PCI_MEM_END       0x18ffffff
-#define PCI_FIRST_DEVFN   0
-#define PCI_LAST_DEVFN    1
-#else
-/* no PCI bus controller */
 #define PCI_IO_START    0
 #define PCI_IO_END      0
 #define PCI_MEM_START   0
 #define PCI_MEM_END     0
 #define PCI_FIRST_DEVFN 0
 #define PCI_LAST_DEVFN  0
-#endif
 
 #endif
 
+#ifndef _LANGUAGE_ASSEMBLY
+typedef volatile struct
+{
+        /* 0x0000 */ u32 toytrim;
+        /* 0x0004 */ u32 toywrite;
+        /* 0x0008 */ u32 toymatch0;
+        /* 0x000C */ u32 toymatch1;
+        /* 0x0010 */ u32 toymatch2;
+        /* 0x0014 */ u32 cntrctrl;
+        /* 0x0018 */ u32 scratch0;
+        /* 0x001C */ u32 scratch1;
+        /* 0x0020 */ u32 freqctrl0;
+        /* 0x0024 */ u32 freqctrl1;
+        /* 0x0028 */ u32 clksrc;
+        /* 0x002C */ u32 pinfunc;
+        /* 0x0030 */ u32 reserved0;
+        /* 0x0034 */ u32 wakemsk;
+        /* 0x0038 */ u32 endian;
+        /* 0x003C */ u32 powerctrl;
+        /* 0x0040 */ u32 toyread;
+        /* 0x0044 */ u32 rtctrim;
+        /* 0x0048 */ u32 rtcwrite;
+        /* 0x004C */ u32 rtcmatch0;
+        /* 0x0050 */ u32 rtcmatch1;
+        /* 0x0054 */ u32 rtcmatch2;
+        /* 0x0058 */ u32 rtcread;
+        /* 0x005C */ u32 wakesrc;
+        /* 0x0060 */ u32 cpupll;
+        /* 0x0064 */ u32 auxpll;
+        /* 0x0068 */ u32 reserved1;
+        /* 0x006C */ u32 reserved2;
+        /* 0x0070 */ u32 reserved3;
+        /* 0x0074 */ u32 reserved4;
+        /* 0x0078 */ u32 slppwr;
+        /* 0x007C */ u32 sleep;
+        /* 0x0080 */ u32 reserved5[32];
+        /* 0x0100 */ u32 trioutrd;
+#define trioutclr trioutrd
+        /* 0x0104 */ u32 reserved6;
+        /* 0x0108 */ u32 outputrd;
+#define outputset outputrd
+        /* 0x010C */ u32 outputclr;
+        /* 0x0110 */ u32 pinstaterd;
+#define pininputen pinstaterd
+
+} AU1X00_SYS;
+
+static AU1X00_SYS* const sys  = (AU1X00_SYS *)SYS_BASE;
+
+#endif
 /* Processor information base on prid.
  * Copied from PowerPC.
  */
+#ifndef _LANGUAGE_ASSEMBLY
 struct cpu_spec {
         /* CPU is matched via (PRID & prid_mask) == prid_value */
         unsigned int    prid_mask;
@@ -1406,3 +1841,6 @@ struct cpu_spec {
 extern struct cpu_spec          cpu_specs[];
 extern struct cpu_spec          *cur_cpu_spec[];
 #endif
+
+#endif
+