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authorRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:05 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:05 -0400
commit641e97f318870921d048154af6807e46e43c307a (patch)
tree6e0984a1bc8932db848be3fdb104a92c97fe341a /include/asm-mips/linkage.h
parent424b28ba4d25fc41abdb7e6fa90e132f0d9558fb (diff)
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/linkage.h')
-rw-r--r--include/asm-mips/linkage.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-mips/linkage.h b/include/asm-mips/linkage.h
index b6185d3cfe68..e9a940d1b0c6 100644
--- a/include/asm-mips/linkage.h
+++ b/include/asm-mips/linkage.h
@@ -5,4 +5,6 @@
5#include <asm/asm.h> 5#include <asm/asm.h>
6#endif 6#endif
7 7
8#define __weak __attribute__((weak))
9
8#endif 10#endif