[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.

It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/include/asm-mips/linkage.h b/include/asm-mips/linkage.h
index b6185d3cfe68..e9a940d1b0c6 100644
--- a/include/asm-mips/linkage.h
+++ b/include/asm-mips/linkage.h
@@ -5,4 +5,6 @@
 #include <asm/asm.h>
 #endif
 
+#define __weak __attribute__((weak))
+
 #endif