aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-mips/jmr3927
diff options
context:
space:
mode:
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-07-10 11:31:36 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-15 13:44:35 -0400
commit22b1d707ffc99faebd86257ad19d5bb9fc624734 (patch)
tree9bd0bcd3878611d74db29e17f3c6e951f4656e61 /include/asm-mips/jmr3927
parent14476007c90005c8992b786c15a59cca31f53268 (diff)
[MIPS] TXx9: Reorganize code
Move arch/mips/{jmr3927,tx4927,tx4938} into arch/mips/txx9/ tree. This will help more code sharing and maintainance. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/jmr3927')
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h177
-rw-r--r--include/asm-mips/jmr3927/tx3927.h319
-rw-r--r--include/asm-mips/jmr3927/txx927.h121
3 files changed, 0 insertions, 617 deletions
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
deleted file mode 100644
index a162268f17df..000000000000
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ /dev/null
@@ -1,177 +0,0 @@
1/*
2 * Defines for the TJSYS JMR-TX3927
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000-2001 Toshiba Corporation
9 */
10#ifndef __ASM_TX3927_JMR3927_H
11#define __ASM_TX3927_JMR3927_H
12
13#include <asm/jmr3927/tx3927.h>
14#include <asm/addrspace.h>
15#include <asm/system.h>
16#include <asm/txx9irq.h>
17
18/* CS */
19#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
20#define JMR3927_ROMCE1 0x1e000000 /* 4M */
21#define JMR3927_ROMCE2 0x14000000 /* 16M */
22#define JMR3927_ROMCE3 0x10000000 /* 64M */
23#define JMR3927_ROMCE5 0x1d000000 /* 4M */
24#define JMR3927_SDCS0 0x00000000 /* 32M */
25#define JMR3927_SDCS1 0x02000000 /* 32M */
26/* PCI Direct Mappings */
27
28#define JMR3927_PCIMEM 0x08000000
29#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */
30#define JMR3927_PCIIO 0x15000000
31#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */
32
33#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
34#define JMR3927_PORT_BASE KSEG1
35
36/* Address map (virtual address) */
37#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
38#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
39#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
40#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
41#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
42
43#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000)
44#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
45#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000)
46#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
47#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000)
48#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000)
49#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000)
50#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000)
51#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000)
52#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
53#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
54
55/* Flash ROM */
56#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
57#define JMR3927_FLASH_SIZE 0x00400000
58
59/* bits for IOC_REV/IOC_BREV (high byte) */
60#define JMR3927_IDT_MASK 0xfc
61#define JMR3927_REV_MASK 0x03
62#define JMR3927_IOC_IDT 0xe0
63
64/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
65#define JMR3927_IOC_INTB_PCIA 0
66#define JMR3927_IOC_INTB_PCIB 1
67#define JMR3927_IOC_INTB_PCIC 2
68#define JMR3927_IOC_INTB_PCID 3
69#define JMR3927_IOC_INTB_MODEM 4
70#define JMR3927_IOC_INTB_INT6 5
71#define JMR3927_IOC_INTB_INT7 6
72#define JMR3927_IOC_INTB_SOFT 7
73#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA)
74#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB)
75#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC)
76#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID)
77#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM)
78#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6)
79#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7)
80#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT)
81
82/* bits for IOC_RESET (high byte) */
83#define JMR3927_IOC_RESET_CPU 1
84#define JMR3927_IOC_RESET_PCI 2
85
86#if defined(__BIG_ENDIAN)
87#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
88#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
89#elif defined(__LITTLE_ENDIAN)
90#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d))
91#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1))
92#else
93#error "No Endian"
94#endif
95
96/* LED macro */
97#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
98
99#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
100
101/* DIPSW4 macro */
102#define jmr3927_dipsw1() (gpio_get_value(11) == 0)
103#define jmr3927_dipsw2() (gpio_get_value(10) == 0)
104#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
105#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
106
107/*
108 * IRQ mappings
109 */
110
111/* These are the virtual IRQ numbers, we divide all IRQ's into
112 * 'spaces', the 'space' determines where and how to enable/disable
113 * that particular IRQ on an JMR machine. Add new 'spaces' as new
114 * IRQ hardware is supported.
115 */
116#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
117#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
118
119#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
120#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
121#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
122
123#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
124#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
125#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2)
126#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3)
127#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4)
128#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5)
129#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
130#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
131#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
132#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
133#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
134#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
135#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
136#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
137#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
138#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
139#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
140#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
141#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
142#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
143#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
144
145/* IOC (PCI, MODEM) */
146#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
147/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
148#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
149
150/* Clocks */
151#define JMR3927_CORECLK 132710400 /* 132.7MHz */
152#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
153#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
154
155/*
156 * TX3927 Pin Configuration:
157 *
158 * PCFG bits Avail Dead
159 * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3]
160 * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4]
161 * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF,
162 * GDBGE* PIO[2:1]
163 * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12]
164 * SELTMR[2:0]:000 TIMER[1:0]
165 * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6],
166 * DMAREQ[1],DMAACK[1]
167 * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8]
168 * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14]
169 * SELDONE:1 DMADONE PIO[7]
170 *
171 * Usable pins are:
172 * RXD[1;0],TXD[1:0],CTS[0],RTS[0],
173 * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
174 * INT[3:0]
175 */
176
177#endif /* __ASM_TX3927_JMR3927_H */
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
deleted file mode 100644
index fb580333c102..000000000000
--- a/include/asm-mips/jmr3927/tx3927.h
+++ /dev/null
@@ -1,319 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Toshiba Corporation
7 */
8#ifndef __ASM_TX3927_H
9#define __ASM_TX3927_H
10
11#include <asm/jmr3927/txx927.h>
12
13#define TX3927_SDRAMC_REG 0xfffe8000
14#define TX3927_ROMC_REG 0xfffe9000
15#define TX3927_DMA_REG 0xfffeb000
16#define TX3927_IRC_REG 0xfffec000
17#define TX3927_PCIC_REG 0xfffed000
18#define TX3927_CCFG_REG 0xfffee000
19#define TX3927_NR_TMR 3
20#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100)
21#define TX3927_NR_SIO 2
22#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100)
23#define TX3927_PIO_REG 0xfffef500
24
25struct tx3927_sdramc_reg {
26 volatile unsigned long cr[8];
27 volatile unsigned long tr[3];
28 volatile unsigned long cmd;
29 volatile unsigned long smrs[2];
30};
31
32struct tx3927_romc_reg {
33 volatile unsigned long cr[8];
34};
35
36struct tx3927_dma_reg {
37 struct tx3927_dma_ch_reg {
38 volatile unsigned long cha;
39 volatile unsigned long sar;
40 volatile unsigned long dar;
41 volatile unsigned long cntr;
42 volatile unsigned long sair;
43 volatile unsigned long dair;
44 volatile unsigned long ccr;
45 volatile unsigned long csr;
46 } ch[4];
47 volatile unsigned long dbr[8];
48 volatile unsigned long tdhr;
49 volatile unsigned long mcr;
50 volatile unsigned long unused0;
51};
52
53#include <asm/byteorder.h>
54
55#ifdef __BIG_ENDIAN
56#define endian_def_s2(e1, e2) \
57 volatile unsigned short e1, e2
58#define endian_def_sb2(e1, e2, e3) \
59 volatile unsigned short e1;volatile unsigned char e2, e3
60#define endian_def_b2s(e1, e2, e3) \
61 volatile unsigned char e1, e2;volatile unsigned short e3
62#define endian_def_b4(e1, e2, e3, e4) \
63 volatile unsigned char e1, e2, e3, e4
64#else
65#define endian_def_s2(e1, e2) \
66 volatile unsigned short e2, e1
67#define endian_def_sb2(e1, e2, e3) \
68 volatile unsigned char e3, e2;volatile unsigned short e1
69#define endian_def_b2s(e1, e2, e3) \
70 volatile unsigned short e3;volatile unsigned char e2, e1
71#define endian_def_b4(e1, e2, e3, e4) \
72 volatile unsigned char e4, e3, e2, e1
73#endif
74
75struct tx3927_pcic_reg {
76 endian_def_s2(did, vid);
77 endian_def_s2(pcistat, pcicmd);
78 endian_def_b4(cc, scc, rpli, rid);
79 endian_def_b4(unused0, ht, mlt, cls);
80 volatile unsigned long ioba; /* +10 */
81 volatile unsigned long mba;
82 volatile unsigned long unused1[5];
83 endian_def_s2(svid, ssvid);
84 volatile unsigned long unused2; /* +30 */
85 endian_def_sb2(unused3, unused4, capptr);
86 volatile unsigned long unused5;
87 endian_def_b4(ml, mg, ip, il);
88 volatile unsigned long unused6; /* +40 */
89 volatile unsigned long istat;
90 volatile unsigned long iim;
91 volatile unsigned long rrt;
92 volatile unsigned long unused7[3]; /* +50 */
93 volatile unsigned long ipbmma;
94 volatile unsigned long ipbioma; /* +60 */
95 volatile unsigned long ilbmma;
96 volatile unsigned long ilbioma;
97 volatile unsigned long unused8[9];
98 volatile unsigned long tc; /* +90 */
99 volatile unsigned long tstat;
100 volatile unsigned long tim;
101 volatile unsigned long tccmd;
102 volatile unsigned long pcirrt; /* +a0 */
103 volatile unsigned long pcirrt_cmd;
104 volatile unsigned long pcirrdt;
105 volatile unsigned long unused9[3];
106 volatile unsigned long tlboap;
107 volatile unsigned long tlbiap;
108 volatile unsigned long tlbmma; /* +c0 */
109 volatile unsigned long tlbioma;
110 volatile unsigned long sc_msg;
111 volatile unsigned long sc_be;
112 volatile unsigned long tbl; /* +d0 */
113 volatile unsigned long unused10[3];
114 volatile unsigned long pwmng; /* +e0 */
115 volatile unsigned long pwmngs;
116 volatile unsigned long unused11[6];
117 volatile unsigned long req_trace; /* +100 */
118 volatile unsigned long pbapmc;
119 volatile unsigned long pbapms;
120 volatile unsigned long pbapmim;
121 volatile unsigned long bm; /* +110 */
122 volatile unsigned long cpcibrs;
123 volatile unsigned long cpcibgs;
124 volatile unsigned long pbacs;
125 volatile unsigned long iobas; /* +120 */
126 volatile unsigned long mbas;
127 volatile unsigned long lbc;
128 volatile unsigned long lbstat;
129 volatile unsigned long lbim; /* +130 */
130 volatile unsigned long pcistatim;
131 volatile unsigned long ica;
132 volatile unsigned long icd;
133 volatile unsigned long iiadp; /* +140 */
134 volatile unsigned long iscdp;
135 volatile unsigned long mmas;
136 volatile unsigned long iomas;
137 volatile unsigned long ipciaddr; /* +150 */
138 volatile unsigned long ipcidata;
139 volatile unsigned long ipcibe;
140};
141
142struct tx3927_ccfg_reg {
143 volatile unsigned long ccfg;
144 volatile unsigned long crir;
145 volatile unsigned long pcfg;
146 volatile unsigned long tear;
147 volatile unsigned long pdcr;
148};
149
150/*
151 * SDRAMC
152 */
153
154/*
155 * ROMC
156 */
157
158/*
159 * DMA
160 */
161/* bits for MCR */
162#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
163#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
164#define TX3927_DMA_MCR_RSFIF 0x00000080
165#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
166#define TX3927_DMA_MCR_LE 0x00000004
167#define TX3927_DMA_MCR_RPRT 0x00000002
168#define TX3927_DMA_MCR_MSTEN 0x00000001
169
170/* bits for CCRn */
171#define TX3927_DMA_CCR_DBINH 0x04000000
172#define TX3927_DMA_CCR_SBINH 0x02000000
173#define TX3927_DMA_CCR_CHRST 0x01000000
174#define TX3927_DMA_CCR_RVBYTE 0x00800000
175#define TX3927_DMA_CCR_ACKPOL 0x00400000
176#define TX3927_DMA_CCR_REQPL 0x00200000
177#define TX3927_DMA_CCR_EGREQ 0x00100000
178#define TX3927_DMA_CCR_CHDN 0x00080000
179#define TX3927_DMA_CCR_DNCTL 0x00060000
180#define TX3927_DMA_CCR_EXTRQ 0x00010000
181#define TX3927_DMA_CCR_INTRQD 0x0000e000
182#define TX3927_DMA_CCR_INTENE 0x00001000
183#define TX3927_DMA_CCR_INTENC 0x00000800
184#define TX3927_DMA_CCR_INTENT 0x00000400
185#define TX3927_DMA_CCR_CHNEN 0x00000200
186#define TX3927_DMA_CCR_XFACT 0x00000100
187#define TX3927_DMA_CCR_SNOP 0x00000080
188#define TX3927_DMA_CCR_DSTINC 0x00000040
189#define TX3927_DMA_CCR_SRCINC 0x00000020
190#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
191#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
192#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
193#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
194#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
195#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
196#define TX3927_DMA_CCR_MEMIO 0x00000002
197#define TX3927_DMA_CCR_ONEAD 0x00000001
198
199/* bits for CSRn */
200#define TX3927_DMA_CSR_CHNACT 0x00000100
201#define TX3927_DMA_CSR_ABCHC 0x00000080
202#define TX3927_DMA_CSR_NCHNC 0x00000040
203#define TX3927_DMA_CSR_NTRNFC 0x00000020
204#define TX3927_DMA_CSR_EXTDN 0x00000010
205#define TX3927_DMA_CSR_CFERR 0x00000008
206#define TX3927_DMA_CSR_CHERR 0x00000004
207#define TX3927_DMA_CSR_DESERR 0x00000002
208#define TX3927_DMA_CSR_SORERR 0x00000001
209
210/*
211 * IRC
212 */
213#define TX3927_IR_INT0 0
214#define TX3927_IR_INT1 1
215#define TX3927_IR_INT2 2
216#define TX3927_IR_INT3 3
217#define TX3927_IR_INT4 4
218#define TX3927_IR_INT5 5
219#define TX3927_IR_SIO0 6
220#define TX3927_IR_SIO1 7
221#define TX3927_IR_SIO(ch) (6 + (ch))
222#define TX3927_IR_DMA 8
223#define TX3927_IR_PIO 9
224#define TX3927_IR_PCI 10
225#define TX3927_IR_TMR(ch) (13 + (ch))
226#define TX3927_NUM_IR 16
227
228/*
229 * PCIC
230 */
231/* bits for PCICMD */
232/* see PCI_COMMAND_XXX in linux/pci.h */
233
234/* bits for PCISTAT */
235/* see PCI_STATUS_XXX in linux/pci.h */
236#define PCI_STATUS_NEW_CAP 0x0010
237
238/* bits for TC */
239#define TX3927_PCIC_TC_OF16E 0x00000020
240#define TX3927_PCIC_TC_IF8E 0x00000010
241#define TX3927_PCIC_TC_OF8E 0x00000008
242
243/* bits for IOBA/MBA */
244/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
245
246/* bits for PBAPMC */
247#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
248#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
249#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
250
251/* bits for LBSTAT/LBIM */
252#define TX3927_PCIC_LBIM_ALL 0x0000003e
253
254/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
255#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
256
257/* bits for LBC */
258#define TX3927_PCIC_LBC_IBSE 0x00004000
259#define TX3927_PCIC_LBC_TIBSE 0x00002000
260#define TX3927_PCIC_LBC_TMFBSE 0x00001000
261#define TX3927_PCIC_LBC_HRST 0x00000800
262#define TX3927_PCIC_LBC_SRST 0x00000400
263#define TX3927_PCIC_LBC_EPCAD 0x00000200
264#define TX3927_PCIC_LBC_MSDSE 0x00000100
265#define TX3927_PCIC_LBC_CRR 0x00000080
266#define TX3927_PCIC_LBC_ILMDE 0x00000040
267#define TX3927_PCIC_LBC_ILIDE 0x00000020
268
269#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
270#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
271
272/*
273 * CCFG
274 */
275/* CCFG : Chip Configuration */
276#define TX3927_CCFG_TLBOFF 0x00020000
277#define TX3927_CCFG_BEOW 0x00010000
278#define TX3927_CCFG_WR 0x00008000
279#define TX3927_CCFG_TOE 0x00004000
280#define TX3927_CCFG_PCIXARB 0x00002000
281#define TX3927_CCFG_PCI3 0x00001000
282#define TX3927_CCFG_PSNP 0x00000800
283#define TX3927_CCFG_PPRI 0x00000400
284#define TX3927_CCFG_PLLM 0x00000030
285#define TX3927_CCFG_ENDIAN 0x00000004
286#define TX3927_CCFG_HALT 0x00000002
287#define TX3927_CCFG_ACEHOLD 0x00000001
288
289/* PCFG : Pin Configuration */
290#define TX3927_PCFG_SYSCLKEN 0x08000000
291#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
292#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
293#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
294#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
295#define TX3927_PCFG_SELALL 0x0003ffff
296#define TX3927_PCFG_SELCS 0x00020000
297#define TX3927_PCFG_SELDSF 0x00010000
298#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
299#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
300#define TX3927_PCFG_SELSIO_ALL 0x00003000
301#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
302#define TX3927_PCFG_SELTMR_ALL 0x00000e00
303#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
304#define TX3927_PCFG_SELDONE 0x00000100
305#define TX3927_PCFG_INTDMA_ALL 0x000000f0
306#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
307#define TX3927_PCFG_SELDMA_ALL 0x0000000f
308#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
309
310#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
311#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
312#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
313#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
314#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
315#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
316#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
317#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
318
319#endif /* __ASM_TX3927_H */
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h
deleted file mode 100644
index 25dcf2feb095..000000000000
--- a/include/asm-mips/jmr3927/txx927.h
+++ /dev/null
@@ -1,121 +0,0 @@
1/*
2 * Common definitions for TX3927/TX4927
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Toshiba Corporation
9 */
10#ifndef __ASM_TXX927_H
11#define __ASM_TXX927_H
12
13struct txx927_sio_reg {
14 volatile unsigned long lcr;
15 volatile unsigned long dicr;
16 volatile unsigned long disr;
17 volatile unsigned long cisr;
18 volatile unsigned long fcr;
19 volatile unsigned long flcr;
20 volatile unsigned long bgr;
21 volatile unsigned long tfifo;
22 volatile unsigned long rfifo;
23};
24
25/*
26 * SIO
27 */
28/* SILCR : Line Control */
29#define TXx927_SILCR_SCS_MASK 0x00000060
30#define TXx927_SILCR_SCS_IMCLK 0x00000000
31#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020
32#define TXx927_SILCR_SCS_SCLK 0x00000040
33#define TXx927_SILCR_SCS_SCLK_BG 0x00000060
34#define TXx927_SILCR_UEPS 0x00000010
35#define TXx927_SILCR_UPEN 0x00000008
36#define TXx927_SILCR_USBL_MASK 0x00000004
37#define TXx927_SILCR_USBL_1BIT 0x00000004
38#define TXx927_SILCR_USBL_2BIT 0x00000000
39#define TXx927_SILCR_UMODE_MASK 0x00000003
40#define TXx927_SILCR_UMODE_8BIT 0x00000000
41#define TXx927_SILCR_UMODE_7BIT 0x00000001
42
43/* SIDICR : DMA/Int. Control */
44#define TXx927_SIDICR_TDE 0x00008000
45#define TXx927_SIDICR_RDE 0x00004000
46#define TXx927_SIDICR_TIE 0x00002000
47#define TXx927_SIDICR_RIE 0x00001000
48#define TXx927_SIDICR_SPIE 0x00000800
49#define TXx927_SIDICR_CTSAC 0x00000600
50#define TXx927_SIDICR_STIE_MASK 0x0000003f
51#define TXx927_SIDICR_STIE_OERS 0x00000020
52#define TXx927_SIDICR_STIE_CTSS 0x00000010
53#define TXx927_SIDICR_STIE_RBRKD 0x00000008
54#define TXx927_SIDICR_STIE_TRDY 0x00000004
55#define TXx927_SIDICR_STIE_TXALS 0x00000002
56#define TXx927_SIDICR_STIE_UBRKD 0x00000001
57
58/* SIDISR : DMA/Int. Status */
59#define TXx927_SIDISR_UBRK 0x00008000
60#define TXx927_SIDISR_UVALID 0x00004000
61#define TXx927_SIDISR_UFER 0x00002000
62#define TXx927_SIDISR_UPER 0x00001000
63#define TXx927_SIDISR_UOER 0x00000800
64#define TXx927_SIDISR_ERI 0x00000400
65#define TXx927_SIDISR_TOUT 0x00000200
66#define TXx927_SIDISR_TDIS 0x00000100
67#define TXx927_SIDISR_RDIS 0x00000080
68#define TXx927_SIDISR_STIS 0x00000040
69#define TXx927_SIDISR_RFDN_MASK 0x0000001f
70
71/* SICISR : Change Int. Status */
72#define TXx927_SICISR_OERS 0x00000020
73#define TXx927_SICISR_CTSS 0x00000010
74#define TXx927_SICISR_RBRKD 0x00000008
75#define TXx927_SICISR_TRDY 0x00000004
76#define TXx927_SICISR_TXALS 0x00000002
77#define TXx927_SICISR_UBRKD 0x00000001
78
79/* SIFCR : FIFO Control */
80#define TXx927_SIFCR_SWRST 0x00008000
81#define TXx927_SIFCR_RDIL_MASK 0x00000180
82#define TXx927_SIFCR_RDIL_1 0x00000000
83#define TXx927_SIFCR_RDIL_4 0x00000080
84#define TXx927_SIFCR_RDIL_8 0x00000100
85#define TXx927_SIFCR_RDIL_12 0x00000180
86#define TXx927_SIFCR_RDIL_MAX 0x00000180
87#define TXx927_SIFCR_TDIL_MASK 0x00000018
88#define TXx927_SIFCR_TDIL_MASK 0x00000018
89#define TXx927_SIFCR_TDIL_1 0x00000000
90#define TXx927_SIFCR_TDIL_4 0x00000001
91#define TXx927_SIFCR_TDIL_8 0x00000010
92#define TXx927_SIFCR_TDIL_MAX 0x00000010
93#define TXx927_SIFCR_TFRST 0x00000004
94#define TXx927_SIFCR_RFRST 0x00000002
95#define TXx927_SIFCR_FRSTE 0x00000001
96#define TXx927_SIO_TX_FIFO 8
97#define TXx927_SIO_RX_FIFO 16
98
99/* SIFLCR : Flow Control */
100#define TXx927_SIFLCR_RCS 0x00001000
101#define TXx927_SIFLCR_TES 0x00000800
102#define TXx927_SIFLCR_RTSSC 0x00000200
103#define TXx927_SIFLCR_RSDE 0x00000100
104#define TXx927_SIFLCR_TSDE 0x00000080
105#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e
106#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e
107#define TXx927_SIFLCR_TBRK 0x00000001
108
109/* SIBGR : Baudrate Control */
110#define TXx927_SIBGR_BCLK_MASK 0x00000300
111#define TXx927_SIBGR_BCLK_T0 0x00000000
112#define TXx927_SIBGR_BCLK_T2 0x00000100
113#define TXx927_SIBGR_BCLK_T4 0x00000200
114#define TXx927_SIBGR_BCLK_T6 0x00000300
115#define TXx927_SIBGR_BRD_MASK 0x000000ff
116
117/*
118 * PIO
119 */
120
121#endif /* __ASM_TXX927_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 00:44:42 -0500