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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-mips/jmr3927
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-mips/jmr3927')
-rw-r--r--include/asm-mips/jmr3927/irq.h62
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h325
-rw-r--r--include/asm-mips/jmr3927/tx3927.h365
-rw-r--r--include/asm-mips/jmr3927/txx927.h175
4 files changed, 927 insertions, 0 deletions
diff --git a/include/asm-mips/jmr3927/irq.h b/include/asm-mips/jmr3927/irq.h
new file mode 100644
index 000000000000..b0c325a22343
--- /dev/null
+++ b/include/asm-mips/jmr3927/irq.h
@@ -0,0 +1,62 @@
1/*
2 * linux/include/asm-mips/tx3927/irq.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 Toshiba Corporation
9 */
10#ifndef __ASM_TX3927_IRQ_H
11#define __ASM_TX3927_IRQ_H
12
13#ifndef __ASSEMBLY__
14
15#include <linux/config.h>
16#include <asm/irq.h>
17
18struct tb_irq_space {
19 struct tb_irq_space* next;
20 int start_irqno;
21 int nr_irqs;
22 void (*mask_func)(int irq_nr, int space_id);
23 void (*unmask_func)(int irq_no, int space_id);
24 const char *name;
25 int space_id;
26 int can_share;
27};
28extern struct tb_irq_space* tb_irq_spaces;
29
30static __inline__ void add_tb_irq_space(struct tb_irq_space* sp)
31{
32 sp->next = tb_irq_spaces;
33 tb_irq_spaces = sp;
34}
35
36
37struct pt_regs;
38extern void
39toshibaboards_spurious(struct pt_regs *regs, int irq);
40extern void
41toshibaboards_irqdispatch(struct pt_regs *regs, int irq);
42
43extern struct irqaction *
44toshibaboards_get_irq_action(int irq);
45extern int
46toshibaboards_setup_irq(int irq, struct irqaction * new);
47
48
49#ifdef CONFIG_TX_BRANCH_LIKELY_BUG_WORKAROUND
50extern void tx_branch_likely_bug_fixup(struct pt_regs *regs);
51#endif
52
53extern int (*toshibaboards_gen_iack)(void);
54
55#endif /* !__ASSEMBLY__ */
56
57#define NR_ISA_IRQS 16
58#define TB_IRQ_IS_ISA(irq) \
59 (0 <= (irq) && (irq) < NR_ISA_IRQS)
60#define TB_IRQ_TO_ISA_IRQ(irq) (irq)
61
62#endif /* __ASM_TX3927_IRQ_H */
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
new file mode 100644
index 000000000000..86df317b4078
--- /dev/null
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -0,0 +1,325 @@
1/*
2 * Defines for the TJSYS JMR-TX3927/JMI-3927IO2/JMY-1394IF.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000-2001 Toshiba Corporation
9 */
10#ifndef __ASM_TX3927_JMR3927_H
11#define __ASM_TX3927_JMR3927_H
12
13#include <asm/jmr3927/tx3927.h>
14#include <asm/addrspace.h>
15#include <asm/jmr3927/irq.h>
16#ifndef __ASSEMBLY__
17#include <asm/system.h>
18#endif
19
20/* CS */
21#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
22#define JMR3927_ROMCE1 0x1e000000 /* 4M */
23#define JMR3927_ROMCE2 0x14000000 /* 16M */
24#define JMR3927_ROMCE3 0x10000000 /* 64M */
25#define JMR3927_ROMCE5 0x1d000000 /* 4M */
26#define JMR3927_SDCS0 0x00000000 /* 32M */
27#define JMR3927_SDCS1 0x02000000 /* 32M */
28/* PCI Direct Mappings */
29
30#define JMR3927_PCIMEM 0x08000000
31#define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */
32#define JMR3927_PCIIO 0x15000000
33#define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */
34
35#define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
36#define JMR3927_PORT_BASE KSEG1
37
38/* select indirect initiator access per errata */
39#define JMR3927_INIT_INDIRECT_PCI
40#define PCI_ISTAT_IDICC 0x1000
41#define PCI_IPCIBE_IBE_LONG 0
42#define PCI_IPCIBE_ICMD_IOREAD 2
43#define PCI_IPCIBE_ICMD_IOWRITE 3
44#define PCI_IPCIBE_ICMD_MEMREAD 6
45#define PCI_IPCIBE_ICMD_MEMWRITE 7
46#define PCI_IPCIBE_ICMD_SHIFT 4
47
48/* Address map (virtual address) */
49#define JMR3927_ROM0_BASE (KSEG1 + JMR3927_ROMCE0)
50#define JMR3927_ROM1_BASE (KSEG1 + JMR3927_ROMCE1)
51#define JMR3927_IOC_BASE (KSEG1 + JMR3927_ROMCE2)
52#define JMR3927_IOB_BASE (KSEG1 + JMR3927_ROMCE3)
53#define JMR3927_ISAMEM_BASE (JMR3927_IOB_BASE)
54#define JMR3927_ISAIO_BASE (JMR3927_IOB_BASE + 0x01000000)
55#define JMR3927_ISAC_BASE (JMR3927_IOB_BASE + 0x02000000)
56#define JMR3927_LCDVGA_REG_BASE (JMR3927_IOB_BASE + 0x03000000)
57#define JMR3927_LCDVGA_MEM_BASE (JMR3927_IOB_BASE + 0x03800000)
58#define JMR3927_JMY1394_BASE (KSEG1 + JMR3927_ROMCE5)
59#define JMR3927_PREMIER3_BASE (JMR3927_JMY1394_BASE + 0x00100000)
60#define JMR3927_PCIMEM_BASE (KSEG1 + JMR3927_PCIMEM)
61#define JMR3927_PCIIO_BASE (KSEG1 + JMR3927_PCIIO)
62
63#define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000)
64#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
65#define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000)
66#define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
67#define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000)
68#define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000)
69#define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000)
70#define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000)
71#define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000)
72#define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
73#define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
74
75#define JMR3927_ISAC_REV_ADDR (JMR3927_ISAC_BASE + 0x00000000)
76#define JMR3927_ISAC_EINTS_ADDR (JMR3927_ISAC_BASE + 0x00200000)
77#define JMR3927_ISAC_EINTM_ADDR (JMR3927_ISAC_BASE + 0x00300000)
78#define JMR3927_ISAC_NMI_ADDR (JMR3927_ISAC_BASE + 0x00400000)
79#define JMR3927_ISAC_LED_ADDR (JMR3927_ISAC_BASE + 0x00500000)
80#define JMR3927_ISAC_INTP_ADDR (JMR3927_ISAC_BASE + 0x00800000)
81#define JMR3927_ISAC_INTS1_ADDR (JMR3927_ISAC_BASE + 0x00900000)
82#define JMR3927_ISAC_INTS2_ADDR (JMR3927_ISAC_BASE + 0x00a00000)
83#define JMR3927_ISAC_INTM_ADDR (JMR3927_ISAC_BASE + 0x00b00000)
84
85/* Flash ROM */
86#define JMR3927_FLASH_BASE (JMR3927_ROM0_BASE)
87#define JMR3927_FLASH_SIZE 0x00400000
88
89/* bits for IOC_REV/IOC_BREV/ISAC_REV (high byte) */
90#define JMR3927_IDT_MASK 0xfc
91#define JMR3927_REV_MASK 0x03
92#define JMR3927_IOC_IDT 0xe0
93#define JMR3927_ISAC_IDT 0x20
94
95/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
96#define JMR3927_IOC_INTB_PCIA 0
97#define JMR3927_IOC_INTB_PCIB 1
98#define JMR3927_IOC_INTB_PCIC 2
99#define JMR3927_IOC_INTB_PCID 3
100#define JMR3927_IOC_INTB_MODEM 4
101#define JMR3927_IOC_INTB_INT6 5
102#define JMR3927_IOC_INTB_INT7 6
103#define JMR3927_IOC_INTB_SOFT 7
104#define JMR3927_IOC_INTF_PCIA (1 << JMR3927_IOC_INTF_PCIA)
105#define JMR3927_IOC_INTF_PCIB (1 << JMR3927_IOC_INTB_PCIB)
106#define JMR3927_IOC_INTF_PCIC (1 << JMR3927_IOC_INTB_PCIC)
107#define JMR3927_IOC_INTF_PCID (1 << JMR3927_IOC_INTB_PCID)
108#define JMR3927_IOC_INTF_MODEM (1 << JMR3927_IOC_INTB_MODEM)
109#define JMR3927_IOC_INTF_INT6 (1 << JMR3927_IOC_INTB_INT6)
110#define JMR3927_IOC_INTF_INT7 (1 << JMR3927_IOC_INTB_INT7)
111#define JMR3927_IOC_INTF_SOFT (1 << JMR3927_IOC_INTB_SOFT)
112
113/* bits for IOC_RESET (high byte) */
114#define JMR3927_IOC_RESET_CPU 1
115#define JMR3927_IOC_RESET_PCI 2
116
117/* bits for ISAC_EINTS/ISAC_EINTM (high byte) */
118#define JMR3927_ISAC_EINTB_IOCHK 2
119#define JMR3927_ISAC_EINTB_BWTH 4
120#define JMR3927_ISAC_EINTF_IOCHK (1 << JMR3927_ISAC_EINTB_IOCHK)
121#define JMR3927_ISAC_EINTF_BWTH (1 << JMR3927_ISAC_EINTB_BWTH)
122
123/* bits for ISAC_LED (high byte) */
124#define JMR3927_ISAC_LED_ISALED 0x01
125#define JMR3927_ISAC_LED_USRLED 0x02
126
127/* bits for ISAC_INTS/ISAC_INTM/ISAC_INTP (high byte) */
128#define JMR3927_ISAC_INTB_IRQ5 0
129#define JMR3927_ISAC_INTB_IRQKB 1
130#define JMR3927_ISAC_INTB_IRQMOUSE 2
131#define JMR3927_ISAC_INTB_IRQ4 3
132#define JMR3927_ISAC_INTB_IRQ12 4
133#define JMR3927_ISAC_INTB_IRQ3 5
134#define JMR3927_ISAC_INTB_IRQ10 6
135#define JMR3927_ISAC_INTB_ISAER 7
136#define JMR3927_ISAC_INTF_IRQ5 (1 << JMR3927_ISAC_INTB_IRQ5)
137#define JMR3927_ISAC_INTF_IRQKB (1 << JMR3927_ISAC_INTB_IRQKB)
138#define JMR3927_ISAC_INTF_IRQMOUSE (1 << JMR3927_ISAC_INTB_IRQMOUSE)
139#define JMR3927_ISAC_INTF_IRQ4 (1 << JMR3927_ISAC_INTB_IRQ4)
140#define JMR3927_ISAC_INTF_IRQ12 (1 << JMR3927_ISAC_INTB_IRQ12)
141#define JMR3927_ISAC_INTF_IRQ3 (1 << JMR3927_ISAC_INTB_IRQ3)
142#define JMR3927_ISAC_INTF_IRQ10 (1 << JMR3927_ISAC_INTB_IRQ10)
143#define JMR3927_ISAC_INTF_ISAER (1 << JMR3927_ISAC_INTB_ISAER)
144
145#ifndef __ASSEMBLY__
146
147#if 0
148#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned short *)(a)) = (d) << 8)
149#define jmr3927_ioc_reg_in(a) (((*(volatile unsigned short *)(a)) >> 8) & 0xff)
150#else
151#if defined(__BIG_ENDIAN)
152#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
153#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)(a))
154#elif defined(__LITTLE_ENDIAN)
155#define jmr3927_ioc_reg_out(d, a) ((*(volatile unsigned char *)((a)^1)) = (d))
156#define jmr3927_ioc_reg_in(a) (*(volatile unsigned char *)((a)^1))
157#else
158#error "No Endian"
159#endif
160#endif
161#define jmr3927_isac_reg_out(d, a) ((*(volatile unsigned char *)(a)) = (d))
162#define jmr3927_isac_reg_in(a) (*(volatile unsigned char *)(a))
163
164static inline int jmr3927_have_isac(void)
165{
166 unsigned char idt;
167 unsigned long flags;
168 unsigned long romcr3;
169
170 local_irq_save(flags);
171 romcr3 = tx3927_romcptr->cr[3];
172 tx3927_romcptr->cr[3] &= 0xffffefff; /* do not wait infinitely */
173 idt = jmr3927_isac_reg_in(JMR3927_ISAC_REV_ADDR) & JMR3927_IDT_MASK;
174 tx3927_romcptr->cr[3] = romcr3;
175 local_irq_restore(flags);
176
177 return idt == JMR3927_ISAC_IDT;
178}
179#define jmr3927_have_nvram() \
180 ((jmr3927_ioc_reg_in(JMR3927_IOC_REV_ADDR) & JMR3927_IDT_MASK) == JMR3927_IOC_IDT)
181
182/* NVRAM macro */
183#define jmr3927_nvram_in(ofs) \
184 jmr3927_ioc_reg_in(JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1))
185#define jmr3927_nvram_out(d, ofs) \
186 jmr3927_ioc_reg_out(d, JMR3927_IOC_NVRAMB_ADDR + ((ofs) << 1))
187
188/* LED macro */
189#define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
190#define jmr3927_io_led_set(n/*0-3*/) jmr3927_isac_reg_out((n), JMR3927_ISAC_LED_ADDR)
191
192#define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
193
194/* DIPSW4 macro */
195#define jmr3927_dipsw1() ((tx3927_pioptr->din & (1 << 11)) == 0)
196#define jmr3927_dipsw2() ((tx3927_pioptr->din & (1 << 10)) == 0)
197#define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
198#define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
199#define jmr3927_io_dipsw() (jmr3927_isac_reg_in(JMR3927_ISAC_LED_ADDR) >> 4)
200
201
202#endif /* !__ASSEMBLY__ */
203
204/*
205 * UART defines for serial.h
206 */
207
208/* use Pre-scaler T0 (1/2) */
209#define JMR3927_BASE_BAUD (JMR3927_IMCLK / 2 / 16)
210
211#define UART0_ADDR 0xfffef300
212#define UART1_ADDR 0xfffef400
213#define UART0_INT JMR3927_IRQ_IRC_SIO0
214#define UART1_INT JMR3927_IRQ_IRC_SIO1
215#define UART0_FLAGS ASYNC_BOOT_AUTOCONF
216#define UART1_FLAGS 0
217
218/*
219 * IRQ mappings
220 */
221
222/* These are the virtual IRQ numbers, we divide all IRQ's into
223 * 'spaces', the 'space' determines where and how to enable/disable
224 * that particular IRQ on an JMR machine. Add new 'spaces' as new
225 * IRQ hardware is supported.
226 */
227#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
228#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
229#define JMR3927_NR_IRQ_ISAC 8 /* ISA */
230
231
232#define JMR3927_IRQ_IRC NR_ISA_IRQS
233#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
234#define JMR3927_IRQ_ISAC (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
235#define JMR3927_IRQ_END (JMR3927_IRQ_ISAC + JMR3927_NR_IRQ_ISAC)
236#define JMR3927_IRQ_IS_IRC(irq) (JMR3927_IRQ_IRC <= (irq) && (irq) < JMR3927_IRQ_IOC)
237#define JMR3927_IRQ_IS_IOC(irq) (JMR3927_IRQ_IOC <= (irq) && (irq) < JMR3927_IRQ_ISAC)
238#define JMR3927_IRQ_IS_ISAC(irq) (JMR3927_IRQ_ISAC <= (irq) && (irq) < JMR3927_IRQ_END)
239
240#define JMR3927_IRQ_IRC_INT0 (JMR3927_IRQ_IRC + TX3927_IR_INT0)
241#define JMR3927_IRQ_IRC_INT1 (JMR3927_IRQ_IRC + TX3927_IR_INT1)
242#define JMR3927_IRQ_IRC_INT2 (JMR3927_IRQ_IRC + TX3927_IR_INT2)
243#define JMR3927_IRQ_IRC_INT3 (JMR3927_IRQ_IRC + TX3927_IR_INT3)
244#define JMR3927_IRQ_IRC_INT4 (JMR3927_IRQ_IRC + TX3927_IR_INT4)
245#define JMR3927_IRQ_IRC_INT5 (JMR3927_IRQ_IRC + TX3927_IR_INT5)
246#define JMR3927_IRQ_IRC_SIO0 (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
247#define JMR3927_IRQ_IRC_SIO1 (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
248#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
249#define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA)
250#define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO)
251#define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI)
252#define JMR3927_IRQ_IRC_TMR0 (JMR3927_IRQ_IRC + TX3927_IR_TMR0)
253#define JMR3927_IRQ_IRC_TMR1 (JMR3927_IRQ_IRC + TX3927_IR_TMR1)
254#define JMR3927_IRQ_IRC_TMR2 (JMR3927_IRQ_IRC + TX3927_IR_TMR2)
255#define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
256#define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
257#define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
258#define JMR3927_IRQ_IOC_PCID (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
259#define JMR3927_IRQ_IOC_MODEM (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
260#define JMR3927_IRQ_IOC_INT6 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
261#define JMR3927_IRQ_IOC_INT7 (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
262#define JMR3927_IRQ_IOC_SOFT (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
263#define JMR3927_IRQ_ISAC_IRQ5 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ5)
264#define JMR3927_IRQ_ISAC_IRQKB (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQKB)
265#define JMR3927_IRQ_ISAC_IRQMOUSE (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQMOUSE)
266#define JMR3927_IRQ_ISAC_IRQ4 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ4)
267#define JMR3927_IRQ_ISAC_IRQ12 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ12)
268#define JMR3927_IRQ_ISAC_IRQ3 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ3)
269#define JMR3927_IRQ_ISAC_IRQ10 (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_IRQ10)
270#define JMR3927_IRQ_ISAC_ISAER (JMR3927_IRQ_ISAC + JMR3927_ISAC_INTB_ISAER)
271
272#if 0 /* auto detect */
273/* RTL8019AS 10M Ether (JMI-3927IO2:JPW2:1-2 Short) */
274#define JMR3927_IRQ_ETHER1 JMR3927_IRQ_IRC_INT0
275#endif
276/* IOC (PCI, MODEM) */
277#define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1
278/* ISAC (ISA, PCMCIA, KEYBOARD, MOUSE) */
279#define JMR3927_IRQ_ISACINT JMR3927_IRQ_IRC_INT2
280/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
281#define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3
282/* Clock Tick (10ms) */
283#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0
284#define JMR3927_IRQ_IDE JMR3927_IRQ_ISAC_IRQ12
285
286/* IEEE1394 (Note that this may conflicts with RTL8019AS 10M Ether...) */
287#define JMR3927_IRQ_PREMIER3 JMR3927_IRQ_IRC_INT0
288
289/* I/O Ports */
290/* RTL8019AS 10M Ether */
291#define JMR3927_ETHER1_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x280)
292#define JMR3927_KBD_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x00800060)
293#define JMR3927_IDE_PORT (JMR3927_ISAIO_BASE - JMR3927_PORT_BASE + 0x001001f0)
294
295/* Clocks */
296#define JMR3927_CORECLK 132710400 /* 132.7MHz */
297#define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */
298#define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */
299
300#define jmr3927_tmrptr tx3927_tmrptr(0) /* TMR0 */
301
302
303/*
304 * TX3927 Pin Configuration:
305 *
306 * PCFG bits Avail Dead
307 * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3]
308 * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4]
309 * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF,
310 * GDBGE* PIO[2:1]
311 * SELDMA[2]:1 DMAREQ[2],DMAACK[2] PIO[13:12]
312 * SELTMR[2:0]:000 TIMER[1:0]
313 * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6],
314 * DMAREQ[1],DMAACK[1]
315 * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8]
316 * SELDMA[3]:1 DMAREQ[3],DMAACK[3] PIO[15:14]
317 * SELDONE:1 DMADONE PIO[7]
318 *
319 * Usable pins are:
320 * RXD[1;0],TXD[1:0],CTS[0],RTS[0],
321 * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
322 * INT[3:0]
323 */
324
325#endif /* __ASM_TX3927_JMR3927_H */
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
new file mode 100644
index 000000000000..b3d67c75d9ac
--- /dev/null
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -0,0 +1,365 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Toshiba Corporation
7 */
8#ifndef __ASM_TX3927_H
9#define __ASM_TX3927_H
10
11#include <asm/jmr3927/txx927.h>
12
13#define TX3927_SDRAMC_REG 0xfffe8000
14#define TX3927_ROMC_REG 0xfffe9000
15#define TX3927_DMA_REG 0xfffeb000
16#define TX3927_IRC_REG 0xfffec000
17#define TX3927_PCIC_REG 0xfffed000
18#define TX3927_CCFG_REG 0xfffee000
19#define TX3927_NR_TMR 3
20#define TX3927_TMR_REG(ch) (0xfffef000 + (ch) * 0x100)
21#define TX3927_NR_SIO 2
22#define TX3927_SIO_REG(ch) (0xfffef300 + (ch) * 0x100)
23#define TX3927_PIO_REG 0xfffef500
24
25#ifndef __ASSEMBLY__
26
27struct tx3927_sdramc_reg {
28 volatile unsigned long cr[8];
29 volatile unsigned long tr[3];
30 volatile unsigned long cmd;
31 volatile unsigned long smrs[2];
32};
33
34struct tx3927_romc_reg {
35 volatile unsigned long cr[8];
36};
37
38struct tx3927_dma_reg {
39 struct tx3927_dma_ch_reg {
40 volatile unsigned long cha;
41 volatile unsigned long sar;
42 volatile unsigned long dar;
43 volatile unsigned long cntr;
44 volatile unsigned long sair;
45 volatile unsigned long dair;
46 volatile unsigned long ccr;
47 volatile unsigned long csr;
48 } ch[4];
49 volatile unsigned long dbr[8];
50 volatile unsigned long tdhr;
51 volatile unsigned long mcr;
52 volatile unsigned long unused0;
53};
54
55struct tx3927_irc_reg {
56 volatile unsigned long cer;
57 volatile unsigned long cr[2];
58 volatile unsigned long unused0;
59 volatile unsigned long ilr[8];
60 volatile unsigned long unused1[4];
61 volatile unsigned long imr;
62 volatile unsigned long unused2[7];
63 volatile unsigned long scr;
64 volatile unsigned long unused3[7];
65 volatile unsigned long ssr;
66 volatile unsigned long unused4[7];
67 volatile unsigned long csr;
68};
69
70#include <asm/byteorder.h>
71
72#ifdef __BIG_ENDIAN
73#define endian_def_s2(e1,e2) \
74 volatile unsigned short e1,e2
75#define endian_def_sb2(e1,e2,e3) \
76 volatile unsigned short e1;volatile unsigned char e2,e3
77#define endian_def_b2s(e1,e2,e3) \
78 volatile unsigned char e1,e2;volatile unsigned short e3
79#define endian_def_b4(e1,e2,e3,e4) \
80 volatile unsigned char e1,e2,e3,e4
81#else
82#define endian_def_s2(e1,e2) \
83 volatile unsigned short e2,e1
84#define endian_def_sb2(e1,e2,e3) \
85 volatile unsigned char e3,e2;volatile unsigned short e1
86#define endian_def_b2s(e1,e2,e3) \
87 volatile unsigned short e3;volatile unsigned char e2,e1
88#define endian_def_b4(e1,e2,e3,e4) \
89 volatile unsigned char e4,e3,e2,e1
90#endif
91
92struct tx3927_pcic_reg {
93 endian_def_s2(did, vid);
94 endian_def_s2(pcistat, pcicmd);
95 endian_def_b4(cc, scc, rpli, rid);
96 endian_def_b4(unused0, ht, mlt, cls);
97 volatile unsigned long ioba; /* +10 */
98 volatile unsigned long mba;
99 volatile unsigned long unused1[5];
100 endian_def_s2(svid, ssvid);
101 volatile unsigned long unused2; /* +30 */
102 endian_def_sb2(unused3, unused4, capptr);
103 volatile unsigned long unused5;
104 endian_def_b4(ml, mg, ip, il);
105 volatile unsigned long unused6; /* +40 */
106 volatile unsigned long istat;
107 volatile unsigned long iim;
108 volatile unsigned long rrt;
109 volatile unsigned long unused7[3]; /* +50 */
110 volatile unsigned long ipbmma;
111 volatile unsigned long ipbioma; /* +60 */
112 volatile unsigned long ilbmma;
113 volatile unsigned long ilbioma;
114 volatile unsigned long unused8[9];
115 volatile unsigned long tc; /* +90 */
116 volatile unsigned long tstat;
117 volatile unsigned long tim;
118 volatile unsigned long tccmd;
119 volatile unsigned long pcirrt; /* +a0 */
120 volatile unsigned long pcirrt_cmd;
121 volatile unsigned long pcirrdt;
122 volatile unsigned long unused9[3];
123 volatile unsigned long tlboap;
124 volatile unsigned long tlbiap;
125 volatile unsigned long tlbmma; /* +c0 */
126 volatile unsigned long tlbioma;
127 volatile unsigned long sc_msg;
128 volatile unsigned long sc_be;
129 volatile unsigned long tbl; /* +d0 */
130 volatile unsigned long unused10[3];
131 volatile unsigned long pwmng; /* +e0 */
132 volatile unsigned long pwmngs;
133 volatile unsigned long unused11[6];
134 volatile unsigned long req_trace; /* +100 */
135 volatile unsigned long pbapmc;
136 volatile unsigned long pbapms;
137 volatile unsigned long pbapmim;
138 volatile unsigned long bm; /* +110 */
139 volatile unsigned long cpcibrs;
140 volatile unsigned long cpcibgs;
141 volatile unsigned long pbacs;
142 volatile unsigned long iobas; /* +120 */
143 volatile unsigned long mbas;
144 volatile unsigned long lbc;
145 volatile unsigned long lbstat;
146 volatile unsigned long lbim; /* +130 */
147 volatile unsigned long pcistatim;
148 volatile unsigned long ica;
149 volatile unsigned long icd;
150 volatile unsigned long iiadp; /* +140 */
151 volatile unsigned long iscdp;
152 volatile unsigned long mmas;
153 volatile unsigned long iomas;
154 volatile unsigned long ipciaddr; /* +150 */
155 volatile unsigned long ipcidata;
156 volatile unsigned long ipcibe;
157};
158
159struct tx3927_ccfg_reg {
160 volatile unsigned long ccfg;
161 volatile unsigned long crir;
162 volatile unsigned long pcfg;
163 volatile unsigned long tear;
164 volatile unsigned long pdcr;
165};
166
167#endif /* !__ASSEMBLY__ */
168
169/*
170 * SDRAMC
171 */
172
173/*
174 * ROMC
175 */
176
177/*
178 * DMA
179 */
180/* bits for MCR */
181#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
182#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
183#define TX3927_DMA_MCR_RSFIF 0x00000080
184#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
185#define TX3927_DMA_MCR_LE 0x00000004
186#define TX3927_DMA_MCR_RPRT 0x00000002
187#define TX3927_DMA_MCR_MSTEN 0x00000001
188
189/* bits for CCRn */
190#define TX3927_DMA_CCR_DBINH 0x04000000
191#define TX3927_DMA_CCR_SBINH 0x02000000
192#define TX3927_DMA_CCR_CHRST 0x01000000
193#define TX3927_DMA_CCR_RVBYTE 0x00800000
194#define TX3927_DMA_CCR_ACKPOL 0x00400000
195#define TX3927_DMA_CCR_REQPL 0x00200000
196#define TX3927_DMA_CCR_EGREQ 0x00100000
197#define TX3927_DMA_CCR_CHDN 0x00080000
198#define TX3927_DMA_CCR_DNCTL 0x00060000
199#define TX3927_DMA_CCR_EXTRQ 0x00010000
200#define TX3927_DMA_CCR_INTRQD 0x0000e000
201#define TX3927_DMA_CCR_INTENE 0x00001000
202#define TX3927_DMA_CCR_INTENC 0x00000800
203#define TX3927_DMA_CCR_INTENT 0x00000400
204#define TX3927_DMA_CCR_CHNEN 0x00000200
205#define TX3927_DMA_CCR_XFACT 0x00000100
206#define TX3927_DMA_CCR_SNOP 0x00000080
207#define TX3927_DMA_CCR_DSTINC 0x00000040
208#define TX3927_DMA_CCR_SRCINC 0x00000020
209#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
210#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
211#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
212#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
213#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
214#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
215#define TX3927_DMA_CCR_MEMIO 0x00000002
216#define TX3927_DMA_CCR_ONEAD 0x00000001
217
218/* bits for CSRn */
219#define TX3927_DMA_CSR_CHNACT 0x00000100
220#define TX3927_DMA_CSR_ABCHC 0x00000080
221#define TX3927_DMA_CSR_NCHNC 0x00000040
222#define TX3927_DMA_CSR_NTRNFC 0x00000020
223#define TX3927_DMA_CSR_EXTDN 0x00000010
224#define TX3927_DMA_CSR_CFERR 0x00000008
225#define TX3927_DMA_CSR_CHERR 0x00000004
226#define TX3927_DMA_CSR_DESERR 0x00000002
227#define TX3927_DMA_CSR_SORERR 0x00000001
228
229/*
230 * IRC
231 */
232#define TX3927_IR_MAX_LEVEL 7
233
234/* IRCER : Int. Control Enable */
235#define TX3927_IRCER_ICE 0x00000001
236
237/* IRCR : Int. Control */
238#define TX3927_IRCR_LOW 0x00000000
239#define TX3927_IRCR_HIGH 0x00000001
240#define TX3927_IRCR_DOWN 0x00000002
241#define TX3927_IRCR_UP 0x00000003
242
243/* IRSCR : Int. Status Control */
244#define TX3927_IRSCR_EIClrE 0x00000100
245#define TX3927_IRSCR_EIClr_MASK 0x0000000f
246
247/* IRCSR : Int. Current Status */
248#define TX3927_IRCSR_IF 0x00010000
249#define TX3927_IRCSR_ILV_MASK 0x00000700
250#define TX3927_IRCSR_IVL_MASK 0x0000001f
251
252#define TX3927_IR_INT0 0
253#define TX3927_IR_INT1 1
254#define TX3927_IR_INT2 2
255#define TX3927_IR_INT3 3
256#define TX3927_IR_INT4 4
257#define TX3927_IR_INT5 5
258#define TX3927_IR_SIO0 6
259#define TX3927_IR_SIO1 7
260#define TX3927_IR_SIO(ch) (6 + (ch))
261#define TX3927_IR_DMA 8
262#define TX3927_IR_PIO 9
263#define TX3927_IR_PCI 10
264#define TX3927_IR_TMR0 13
265#define TX3927_IR_TMR1 14
266#define TX3927_IR_TMR2 15
267#define TX3927_NUM_IR 16
268
269/*
270 * PCIC
271 */
272/* bits for PCICMD */
273/* see PCI_COMMAND_XXX in linux/pci.h */
274
275/* bits for PCISTAT */
276/* see PCI_STATUS_XXX in linux/pci.h */
277#define PCI_STATUS_NEW_CAP 0x0010
278
279/* bits for TC */
280#define TX3927_PCIC_TC_OF16E 0x00000020
281#define TX3927_PCIC_TC_IF8E 0x00000010
282#define TX3927_PCIC_TC_OF8E 0x00000008
283
284/* bits for IOBA/MBA */
285/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
286
287/* bits for PBAPMC */
288#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
289#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
290#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
291
292/* bits for LBSTAT/LBIM */
293#define TX3927_PCIC_LBIM_ALL 0x0000003e
294
295/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
296#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
297
298/* bits for LBC */
299#define TX3927_PCIC_LBC_IBSE 0x00004000
300#define TX3927_PCIC_LBC_TIBSE 0x00002000
301#define TX3927_PCIC_LBC_TMFBSE 0x00001000
302#define TX3927_PCIC_LBC_HRST 0x00000800
303#define TX3927_PCIC_LBC_SRST 0x00000400
304#define TX3927_PCIC_LBC_EPCAD 0x00000200
305#define TX3927_PCIC_LBC_MSDSE 0x00000100
306#define TX3927_PCIC_LBC_CRR 0x00000080
307#define TX3927_PCIC_LBC_ILMDE 0x00000040
308#define TX3927_PCIC_LBC_ILIDE 0x00000020
309
310#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
311#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
312
313/*
314 * CCFG
315 */
316/* CCFG : Chip Configuration */
317#define TX3927_CCFG_TLBOFF 0x00020000
318#define TX3927_CCFG_BEOW 0x00010000
319#define TX3927_CCFG_WR 0x00008000
320#define TX3927_CCFG_TOE 0x00004000
321#define TX3927_CCFG_PCIXARB 0x00002000
322#define TX3927_CCFG_PCI3 0x00001000
323#define TX3927_CCFG_PSNP 0x00000800
324#define TX3927_CCFG_PPRI 0x00000400
325#define TX3927_CCFG_PLLM 0x00000030
326#define TX3927_CCFG_ENDIAN 0x00000004
327#define TX3927_CCFG_HALT 0x00000002
328#define TX3927_CCFG_ACEHOLD 0x00000001
329
330/* PCFG : Pin Configuration */
331#define TX3927_PCFG_SYSCLKEN 0x08000000
332#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
333#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
334#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
335#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
336#define TX3927_PCFG_SELALL 0x0003ffff
337#define TX3927_PCFG_SELCS 0x00020000
338#define TX3927_PCFG_SELDSF 0x00010000
339#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
340#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
341#define TX3927_PCFG_SELSIO_ALL 0x00003000
342#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
343#define TX3927_PCFG_SELTMR_ALL 0x00000e00
344#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
345#define TX3927_PCFG_SELDONE 0x00000100
346#define TX3927_PCFG_INTDMA_ALL 0x000000f0
347#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
348#define TX3927_PCFG_SELDMA_ALL 0x0000000f
349#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
350
351#ifndef __ASSEMBLY__
352
353#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
354#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
355#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
356#define tx3927_ircptr ((struct tx3927_irc_reg *)TX3927_IRC_REG)
357#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
358#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
359#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
360#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
361#define tx3927_pioptr ((struct txx927_pio_reg *)TX3927_PIO_REG)
362
363#endif /* !__ASSEMBLY__ */
364
365#endif /* __ASM_TX3927_H */
diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h
new file mode 100644
index 000000000000..9d5792eab452
--- /dev/null
+++ b/include/asm-mips/jmr3927/txx927.h
@@ -0,0 +1,175 @@
1/*
2 * Common definitions for TX3927/TX4927
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2000 Toshiba Corporation
9 */
10#ifndef __ASM_TXX927_H
11#define __ASM_TXX927_H
12
13#ifndef __ASSEMBLY__
14
15struct txx927_tmr_reg {
16 volatile unsigned long tcr;
17 volatile unsigned long tisr;
18 volatile unsigned long cpra;
19 volatile unsigned long cprb;
20 volatile unsigned long itmr;
21 volatile unsigned long unused0[3];
22 volatile unsigned long ccdr;
23 volatile unsigned long unused1[3];
24 volatile unsigned long pgmr;
25 volatile unsigned long unused2[3];
26 volatile unsigned long wtmr;
27 volatile unsigned long unused3[43];
28 volatile unsigned long trr;
29};
30
31struct txx927_sio_reg {
32 volatile unsigned long lcr;
33 volatile unsigned long dicr;
34 volatile unsigned long disr;
35 volatile unsigned long cisr;
36 volatile unsigned long fcr;
37 volatile unsigned long flcr;
38 volatile unsigned long bgr;
39 volatile unsigned long tfifo;
40 volatile unsigned long rfifo;
41};
42
43struct txx927_pio_reg {
44 volatile unsigned long dout;
45 volatile unsigned long din;
46 volatile unsigned long dir;
47 volatile unsigned long od;
48 volatile unsigned long flag[2];
49 volatile unsigned long pol;
50 volatile unsigned long intc;
51 volatile unsigned long maskcpu;
52 volatile unsigned long maskext;
53};
54
55#endif /* !__ASSEMBLY__ */
56
57
58/*
59 * TMR
60 */
61/* TMTCR : Timer Control */
62#define TXx927_TMTCR_TCE 0x00000080
63#define TXx927_TMTCR_CCDE 0x00000040
64#define TXx927_TMTCR_CRE 0x00000020
65#define TXx927_TMTCR_ECES 0x00000008
66#define TXx927_TMTCR_CCS 0x00000004
67#define TXx927_TMTCR_TMODE_MASK 0x00000003
68#define TXx927_TMTCR_TMODE_ITVL 0x00000000
69
70/* TMTISR : Timer Int. Status */
71#define TXx927_TMTISR_TPIBS 0x00000004
72#define TXx927_TMTISR_TPIAS 0x00000002
73#define TXx927_TMTISR_TIIS 0x00000001
74
75/* TMTITMR : Interval Timer Mode */
76#define TXx927_TMTITMR_TIIE 0x00008000
77#define TXx927_TMTITMR_TZCE 0x00000001
78
79/*
80 * SIO
81 */
82/* SILCR : Line Control */
83#define TXx927_SILCR_SCS_MASK 0x00000060
84#define TXx927_SILCR_SCS_IMCLK 0x00000000
85#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020
86#define TXx927_SILCR_SCS_SCLK 0x00000040
87#define TXx927_SILCR_SCS_SCLK_BG 0x00000060
88#define TXx927_SILCR_UEPS 0x00000010
89#define TXx927_SILCR_UPEN 0x00000008
90#define TXx927_SILCR_USBL_MASK 0x00000004
91#define TXx927_SILCR_USBL_1BIT 0x00000004
92#define TXx927_SILCR_USBL_2BIT 0x00000000
93#define TXx927_SILCR_UMODE_MASK 0x00000003
94#define TXx927_SILCR_UMODE_8BIT 0x00000000
95#define TXx927_SILCR_UMODE_7BIT 0x00000001
96
97/* SIDICR : DMA/Int. Control */
98#define TXx927_SIDICR_TDE 0x00008000
99#define TXx927_SIDICR_RDE 0x00004000
100#define TXx927_SIDICR_TIE 0x00002000
101#define TXx927_SIDICR_RIE 0x00001000
102#define TXx927_SIDICR_SPIE 0x00000800
103#define TXx927_SIDICR_CTSAC 0x00000600
104#define TXx927_SIDICR_STIE_MASK 0x0000003f
105#define TXx927_SIDICR_STIE_OERS 0x00000020
106#define TXx927_SIDICR_STIE_CTSS 0x00000010
107#define TXx927_SIDICR_STIE_RBRKD 0x00000008
108#define TXx927_SIDICR_STIE_TRDY 0x00000004
109#define TXx927_SIDICR_STIE_TXALS 0x00000002
110#define TXx927_SIDICR_STIE_UBRKD 0x00000001
111
112/* SIDISR : DMA/Int. Status */
113#define TXx927_SIDISR_UBRK 0x00008000
114#define TXx927_SIDISR_UVALID 0x00004000
115#define TXx927_SIDISR_UFER 0x00002000
116#define TXx927_SIDISR_UPER 0x00001000
117#define TXx927_SIDISR_UOER 0x00000800
118#define TXx927_SIDISR_ERI 0x00000400
119#define TXx927_SIDISR_TOUT 0x00000200
120#define TXx927_SIDISR_TDIS 0x00000100
121#define TXx927_SIDISR_RDIS 0x00000080
122#define TXx927_SIDISR_STIS 0x00000040
123#define TXx927_SIDISR_RFDN_MASK 0x0000001f
124
125/* SICISR : Change Int. Status */
126#define TXx927_SICISR_OERS 0x00000020
127#define TXx927_SICISR_CTSS 0x00000010
128#define TXx927_SICISR_RBRKD 0x00000008
129#define TXx927_SICISR_TRDY 0x00000004
130#define TXx927_SICISR_TXALS 0x00000002
131#define TXx927_SICISR_UBRKD 0x00000001
132
133/* SIFCR : FIFO Control */
134#define TXx927_SIFCR_SWRST 0x00008000
135#define TXx927_SIFCR_RDIL_MASK 0x00000180
136#define TXx927_SIFCR_RDIL_1 0x00000000
137#define TXx927_SIFCR_RDIL_4 0x00000080
138#define TXx927_SIFCR_RDIL_8 0x00000100
139#define TXx927_SIFCR_RDIL_12 0x00000180
140#define TXx927_SIFCR_RDIL_MAX 0x00000180
141#define TXx927_SIFCR_TDIL_MASK 0x00000018
142#define TXx927_SIFCR_TDIL_MASK 0x00000018
143#define TXx927_SIFCR_TDIL_1 0x00000000
144#define TXx927_SIFCR_TDIL_4 0x00000001
145#define TXx927_SIFCR_TDIL_8 0x00000010
146#define TXx927_SIFCR_TDIL_MAX 0x00000010
147#define TXx927_SIFCR_TFRST 0x00000004
148#define TXx927_SIFCR_RFRST 0x00000002
149#define TXx927_SIFCR_FRSTE 0x00000001
150#define TXx927_SIO_TX_FIFO 8
151#define TXx927_SIO_RX_FIFO 16
152
153/* SIFLCR : Flow Control */
154#define TXx927_SIFLCR_RCS 0x00001000
155#define TXx927_SIFLCR_TES 0x00000800
156#define TXx927_SIFLCR_RTSSC 0x00000200
157#define TXx927_SIFLCR_RSDE 0x00000100
158#define TXx927_SIFLCR_TSDE 0x00000080
159#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e
160#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e
161#define TXx927_SIFLCR_TBRK 0x00000001
162
163/* SIBGR : Baudrate Control */
164#define TXx927_SIBGR_BCLK_MASK 0x00000300
165#define TXx927_SIBGR_BCLK_T0 0x00000000
166#define TXx927_SIBGR_BCLK_T2 0x00000100
167#define TXx927_SIBGR_BCLK_T4 0x00000200
168#define TXx927_SIBGR_BCLK_T6 0x00000300
169#define TXx927_SIBGR_BRD_MASK 0x000000ff
170
171/*
172 * PIO
173 */
174
175#endif /* __ASM_TXX927_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 11:58:27 -0500