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authorRalf Baechle <ralf@linux-mips.org>2007-10-14 09:02:26 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-16 13:23:45 -0400
commitdd67b1556ebea118b40986cdb8e70874b5454442 (patch)
tree167320a78cb4afb05d841027d2860f7c38346470 /include/asm-mips/ip32
parent65a6ec0d72a07f16719e9b7a96e1c4bae044b591 (diff)
[MIPS] IP32: Fix build by conversion to irq_cpu.c.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/ip32')
-rw-r--r--include/asm-mips/ip32/ip32_ints.h158
1 files changed, 88 insertions, 70 deletions
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
index c3c280e3d591..042f821899a8 100644
--- a/include/asm-mips/ip32/ip32_ints.h
+++ b/include/asm-mips/ip32/ip32_ints.h
@@ -9,86 +9,104 @@
9#ifndef __ASM_IP32_INTS_H 9#ifndef __ASM_IP32_INTS_H
10#define __ASM_IP32_INTS_H 10#define __ASM_IP32_INTS_H
11 11
12#include <asm/irq.h>
13
12/* 14/*
13 * This list reflects the assignment of interrupt numbers to 15 * This list reflects the assignment of interrupt numbers to
14 * interrupting events. Order is fairly irrelevant to handling 16 * interrupting events. Order is fairly irrelevant to handling
15 * priority. This differs from irix. 17 * priority. This differs from irix.
16 */ 18 */
17 19
18/* CPU */ 20enum ip32_irq_no {
19#define IP32_R4K_TIMER_IRQ 0 21 /*
22 * CPU interrupts are 0 ... 7
23 */
20 24
21/* MACE */ 25 /*
22#define MACE_VID_IN1_IRQ 1 26 * MACE
23#define MACE_VID_IN2_IRQ 2 27 */
24#define MACE_VID_OUT_IRQ 3 28 MACE_VID_IN1_IRQ = MIPS_CPU_IRQ_BASE + 8,
25#define MACE_ETHERNET_IRQ 4 29 MACE_VID_IN2_IRQ,
26/* SUPERIO, MISC, and AUDIO are MACEISA */ 30 MACE_VID_OUT_IRQ,
27#define MACE_PCI_BRIDGE_IRQ 8 31 MACE_ETHERNET_IRQ,
32 /* SUPERIO, MISC, and AUDIO are MACEISA */
33 __MACE_SUPERIO,
34 __MACE_MISC,
35 __MACE_AUDIO,
36 MACE_PCI_BRIDGE_IRQ,
28 37
29/* MACEPCI */ 38 /*
30#define MACEPCI_SCSI0_IRQ 9 39 * MACEPCI
31#define MACEPCI_SCSI1_IRQ 10 40 */
32#define MACEPCI_SLOT0_IRQ 11 41 MACEPCI_SCSI0_IRQ,
33#define MACEPCI_SLOT1_IRQ 12 42 MACEPCI_SCSI1_IRQ,
34#define MACEPCI_SLOT2_IRQ 13 43 MACEPCI_SLOT0_IRQ,
35#define MACEPCI_SHARED0_IRQ 14 44 MACEPCI_SLOT1_IRQ,
36#define MACEPCI_SHARED1_IRQ 15 45 MACEPCI_SLOT2_IRQ,
37#define MACEPCI_SHARED2_IRQ 16 46 MACEPCI_SHARED0_IRQ,
47 MACEPCI_SHARED1_IRQ,
48 MACEPCI_SHARED2_IRQ,
38 49
39/* CRIME */ 50 /*
40#define CRIME_GBE0_IRQ 17 51 * CRIME
41#define CRIME_GBE1_IRQ 18 52 */
42#define CRIME_GBE2_IRQ 19 53 CRIME_GBE0_IRQ,
43#define CRIME_GBE3_IRQ 20 54 CRIME_GBE1_IRQ,
44#define CRIME_CPUERR_IRQ 21 55 CRIME_GBE2_IRQ,
45#define CRIME_MEMERR_IRQ 22 56 CRIME_GBE3_IRQ,
46#define CRIME_RE_EMPTY_E_IRQ 23 57 CRIME_CPUERR_IRQ,
47#define CRIME_RE_FULL_E_IRQ 24 58 CRIME_MEMERR_IRQ,
48#define CRIME_RE_IDLE_E_IRQ 25 59 CRIME_RE_EMPTY_E_IRQ,
49#define CRIME_RE_EMPTY_L_IRQ 26 60 CRIME_RE_FULL_E_IRQ,
50#define CRIME_RE_FULL_L_IRQ 27 61 CRIME_RE_IDLE_E_IRQ,
51#define CRIME_RE_IDLE_L_IRQ 28 62 CRIME_RE_EMPTY_L_IRQ,
52#define CRIME_SOFT0_IRQ 29 63 CRIME_RE_FULL_L_IRQ,
53#define CRIME_SOFT1_IRQ 30 64 CRIME_RE_IDLE_L_IRQ,
54#define CRIME_SOFT2_IRQ 31 65 CRIME_SOFT0_IRQ,
55#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ 66 CRIME_SOFT1_IRQ,
56#define CRIME_VICE_IRQ 32 67 CRIME_SOFT2_IRQ,
68 CRIME_SYSCORERR_IRQ = CRIME_SOFT2_IRQ,
69 CRIME_VICE_IRQ,
57 70
58/* MACEISA */ 71 /*
59#define MACEISA_AUDIO_SW_IRQ 33 72 * MACEISA
60#define MACEISA_AUDIO_SC_IRQ 34 73 */
61#define MACEISA_AUDIO1_DMAT_IRQ 35 74 MACEISA_AUDIO_SW_IRQ,
62#define MACEISA_AUDIO1_OF_IRQ 36 75 MACEISA_AUDIO_SC_IRQ,
63#define MACEISA_AUDIO2_DMAT_IRQ 37 76 MACEISA_AUDIO1_DMAT_IRQ,
64#define MACEISA_AUDIO2_MERR_IRQ 38 77 MACEISA_AUDIO1_OF_IRQ,
65#define MACEISA_AUDIO3_DMAT_IRQ 39 78 MACEISA_AUDIO2_DMAT_IRQ,
66#define MACEISA_AUDIO3_MERR_IRQ 40 79 MACEISA_AUDIO2_MERR_IRQ,
67#define MACEISA_RTC_IRQ 41 80 MACEISA_AUDIO3_DMAT_IRQ,
68#define MACEISA_KEYB_IRQ 42 81 MACEISA_AUDIO3_MERR_IRQ,
69/* MACEISA_KEYB_POLL is not an IRQ */ 82 MACEISA_RTC_IRQ,
70#define MACEISA_MOUSE_IRQ 44 83 MACEISA_KEYB_IRQ,
71/* MACEISA_MOUSE_POLL is not an IRQ */ 84 /* MACEISA_KEYB_POLL is not an IRQ */
72#define MACEISA_TIMER0_IRQ 46 85 __MACEISA_KEYB_POLL,
73#define MACEISA_TIMER1_IRQ 47 86 MACEISA_MOUSE_IRQ,
74#define MACEISA_TIMER2_IRQ 48 87 /* MACEISA_MOUSE_POLL is not an IRQ */
75#define MACEISA_PARALLEL_IRQ 49 88 __MACEISA_MOUSE_POLL,
76#define MACEISA_PAR_CTXA_IRQ 50 89 MACEISA_TIMER0_IRQ,
77#define MACEISA_PAR_CTXB_IRQ 51 90 MACEISA_TIMER1_IRQ,
78#define MACEISA_PAR_MERR_IRQ 52 91 MACEISA_TIMER2_IRQ,
79#define MACEISA_SERIAL1_IRQ 53 92 MACEISA_PARALLEL_IRQ,
80#define MACEISA_SERIAL1_TDMAT_IRQ 54 93 MACEISA_PAR_CTXA_IRQ,
81#define MACEISA_SERIAL1_TDMAPR_IRQ 55 94 MACEISA_PAR_CTXB_IRQ,
82#define MACEISA_SERIAL1_TDMAME_IRQ 56 95 MACEISA_PAR_MERR_IRQ,
83#define MACEISA_SERIAL1_RDMAT_IRQ 57 96 MACEISA_SERIAL1_IRQ,
84#define MACEISA_SERIAL1_RDMAOR_IRQ 58 97 MACEISA_SERIAL1_TDMAT_IRQ,
85#define MACEISA_SERIAL2_IRQ 59 98 MACEISA_SERIAL1_TDMAPR_IRQ,
86#define MACEISA_SERIAL2_TDMAT_IRQ 60 99 MACEISA_SERIAL1_TDMAME_IRQ,
87#define MACEISA_SERIAL2_TDMAPR_IRQ 61 100 MACEISA_SERIAL1_RDMAT_IRQ,
88#define MACEISA_SERIAL2_TDMAME_IRQ 62 101 MACEISA_SERIAL1_RDMAOR_IRQ,
89#define MACEISA_SERIAL2_RDMAT_IRQ 63 102 MACEISA_SERIAL2_IRQ,
90#define MACEISA_SERIAL2_RDMAOR_IRQ 64 103 MACEISA_SERIAL2_TDMAT_IRQ,
104 MACEISA_SERIAL2_TDMAPR_IRQ,
105 MACEISA_SERIAL2_TDMAME_IRQ,
106 MACEISA_SERIAL2_RDMAT_IRQ,
107 MACEISA_SERIAL2_RDMAOR_IRQ,
91 108
92#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ 109 IP32_IRQ_MAX = MACEISA_SERIAL2_RDMAOR_IRQ
110};
93 111
94#endif /* __ASM_IP32_INTS_H */ 112#endif /* __ASM_IP32_INTS_H */
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