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author | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2006-06-10 14:47:26 -0400 |
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committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2006-06-10 14:47:26 -0400 |
commit | f0cd91a68acdc9b49d7f6738b514a426da627649 (patch) | |
tree | 8ad73564015794197583b094217ae0a71e71e753 /include/asm-mips/inst.h | |
parent | 60eef25701d25e99c991dd0f4a9f3832a0c3ad3e (diff) | |
parent | 128e6ced247cda88f96fa9f2e4ba8b2c4a681560 (diff) |
Merge ../linux-2.6
Diffstat (limited to 'include/asm-mips/inst.h')
-rw-r--r-- | include/asm-mips/inst.h | 33 |
1 files changed, 28 insertions, 5 deletions
diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h index e0745f4ff624..1ed8d0f62577 100644 --- a/include/asm-mips/inst.h +++ b/include/asm-mips/inst.h | |||
@@ -6,6 +6,7 @@ | |||
6 | * for more details. | 6 | * for more details. |
7 | * | 7 | * |
8 | * Copyright (C) 1996, 2000 by Ralf Baechle | 8 | * Copyright (C) 1996, 2000 by Ralf Baechle |
9 | * Copyright (C) 2006 by Thiemo Seufer | ||
9 | */ | 10 | */ |
10 | #ifndef _ASM_INST_H | 11 | #ifndef _ASM_INST_H |
11 | #define _ASM_INST_H | 12 | #define _ASM_INST_H |
@@ -21,14 +22,14 @@ enum major_op { | |||
21 | cop0_op, cop1_op, cop2_op, cop1x_op, | 22 | cop0_op, cop1_op, cop2_op, cop1x_op, |
22 | beql_op, bnel_op, blezl_op, bgtzl_op, | 23 | beql_op, bnel_op, blezl_op, bgtzl_op, |
23 | daddi_op, daddiu_op, ldl_op, ldr_op, | 24 | daddi_op, daddiu_op, ldl_op, ldr_op, |
24 | major_1c_op, jalx_op, major_1e_op, major_1f_op, | 25 | spec2_op, jalx_op, mdmx_op, spec3_op, |
25 | lb_op, lh_op, lwl_op, lw_op, | 26 | lb_op, lh_op, lwl_op, lw_op, |
26 | lbu_op, lhu_op, lwr_op, lwu_op, | 27 | lbu_op, lhu_op, lwr_op, lwu_op, |
27 | sb_op, sh_op, swl_op, sw_op, | 28 | sb_op, sh_op, swl_op, sw_op, |
28 | sdl_op, sdr_op, swr_op, cache_op, | 29 | sdl_op, sdr_op, swr_op, cache_op, |
29 | ll_op, lwc1_op, lwc2_op, pref_op, | 30 | ll_op, lwc1_op, lwc2_op, pref_op, |
30 | lld_op, ldc1_op, ldc2_op, ld_op, | 31 | lld_op, ldc1_op, ldc2_op, ld_op, |
31 | sc_op, swc1_op, swc2_op, rdhwr_op, | 32 | sc_op, swc1_op, swc2_op, major_3b_op, |
32 | scd_op, sdc1_op, sdc2_op, sd_op | 33 | scd_op, sdc1_op, sdc2_op, sd_op |
33 | }; | 34 | }; |
34 | 35 | ||
@@ -37,7 +38,7 @@ enum major_op { | |||
37 | */ | 38 | */ |
38 | enum spec_op { | 39 | enum spec_op { |
39 | sll_op, movc_op, srl_op, sra_op, | 40 | sll_op, movc_op, srl_op, sra_op, |
40 | sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */ | 41 | sllv_op, pmon_op, srlv_op, srav_op, |
41 | jr_op, jalr_op, movz_op, movn_op, | 42 | jr_op, jalr_op, movz_op, movn_op, |
42 | syscall_op, break_op, spim_op, sync_op, | 43 | syscall_op, break_op, spim_op, sync_op, |
43 | mfhi_op, mthi_op, mflo_op, mtlo_op, | 44 | mfhi_op, mthi_op, mflo_op, mtlo_op, |
@@ -55,6 +56,28 @@ enum spec_op { | |||
55 | }; | 56 | }; |
56 | 57 | ||
57 | /* | 58 | /* |
59 | * func field of spec2 opcode. | ||
60 | */ | ||
61 | enum spec2_op { | ||
62 | madd_op, maddu_op, mul_op, spec2_3_unused_op, | ||
63 | msub_op, msubu_op, /* more unused ops */ | ||
64 | clz_op = 0x20, clo_op, | ||
65 | dclz_op = 0x24, dclo_op, | ||
66 | sdbpp_op = 0x3f | ||
67 | }; | ||
68 | |||
69 | /* | ||
70 | * func field of spec3 opcode. | ||
71 | */ | ||
72 | enum spec3_op { | ||
73 | ext_op, dextm_op, dextu_op, dext_op, | ||
74 | ins_op, dinsm_op, dinsu_op, dins_op, | ||
75 | bshfl_op = 0x20, | ||
76 | dbshfl_op = 0x24, | ||
77 | rdhwr_op = 0x3f | ||
78 | }; | ||
79 | |||
80 | /* | ||
58 | * rt field of bcond opcodes. | 81 | * rt field of bcond opcodes. |
59 | */ | 82 | */ |
60 | enum rt_op { | 83 | enum rt_op { |
@@ -151,8 +174,8 @@ enum cop1x_func { | |||
151 | * func field for mad opcodes (MIPS IV). | 174 | * func field for mad opcodes (MIPS IV). |
152 | */ | 175 | */ |
153 | enum mad_func { | 176 | enum mad_func { |
154 | madd_op = 0x08, msub_op = 0x0a, | 177 | madd_fp_op = 0x08, msub_fp_op = 0x0a, |
155 | nmadd_op = 0x0c, nmsub_op = 0x0e | 178 | nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e |
156 | }; | 179 | }; |
157 | 180 | ||
158 | /* | 181 | /* |