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authorRalf Baechle <ralf@linux-mips.org>2005-07-14 09:25:05 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:31:53 -0400
commit86071b637db7baf599df26fdf820dce2fc55ca9f (patch)
tree71d91172984777b5b39908cbafad757d7a2556a6 /include/asm-mips/hazards.h
parent7e35952baa9d7424dfb95ca8aff7239a1f6ec011 (diff)
Cleanups.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/hazards.h')
-rw-r--r--include/asm-mips/hazards.h22
1 files changed, 12 insertions, 10 deletions
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index f63d824e6e48..6bd265b34a4c 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -148,15 +148,13 @@ __asm__(
148#endif 148#endif
149 149
150/* 150/*
151 * mtc0->mfc0 hazard 151 * Interrupt enable/disable hazards
152 * The 24K has a 2 cycle mtc0/mfc0 execution hazard. 152 * Some processors have hazards when modifying
153 * It is a MIPS32R2 processor so ehb will clear the hazard. 153 * the status register to change the interrupt state
154 */ 154 */
155 155
156#ifdef CONFIG_CPU_MIPSR2 156#ifdef CONFIG_CPU_MIPSR2
157/* 157
158 * Use a macro for ehb unless explicit support for MIPSR2 is enabled
159 */
160__asm__( 158__asm__(
161 " .macro\tirq_enable_hazard \n\t" 159 " .macro\tirq_enable_hazard \n\t"
162 " _ehb \n\t" 160 " _ehb \n\t"
@@ -164,19 +162,23 @@ __asm__(
164 " \n\t" 162 " \n\t"
165 " .macro\tirq_disable_hazard \n\t" 163 " .macro\tirq_disable_hazard \n\t"
166 " _ehb \n\t" 164 " _ehb \n\t"
165 " .endm \n\t"
166 " \n\t"
167 " .macro\tback_to_back_c0_hazard \n\t"
168 " _ehb \n\t"
167 " .endm"); 169 " .endm");
168 170
169#define irq_enable_hazard() \ 171#define irq_enable_hazard() \
170 __asm__ __volatile__( \ 172 __asm__ __volatile__( \
171 "_ehb\t\t\t\t# irq_enable_hazard") 173 "irq_enable_hazard")
172 174
173#define irq_disable_hazard() \ 175#define irq_disable_hazard() \
174 __asm__ __volatile__( \ 176 __asm__ __volatile__( \
175 "_ehb\t\t\t\t# irq_disable_hazard") 177 "irq_disable_hazard")
176 178
177#define back_to_back_c0_hazard() \ 179#define back_to_back_c0_hazard() \
178 __asm__ __volatile__( \ 180 __asm__ __volatile__( \
179 "_ehb\t\t\t\t# back_to_back_c0_hazard") 181 "back_to_back_c0_hazard")
180 182
181#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000) 183#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_RM9000)
182 184
@@ -218,7 +220,7 @@ __asm__(
218#define irq_enable_hazard() do { } while (0) 220#define irq_enable_hazard() do { } while (0)
219#define irq_disable_hazard() \ 221#define irq_disable_hazard() \
220 __asm__ __volatile__( \ 222 __asm__ __volatile__( \
221 "_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard") 223 "irq_disable_hazard")
222 224
223#define back_to_back_c0_hazard() \ 225#define back_to_back_c0_hazard() \
224 __asm__ __volatile__( \ 226 __asm__ __volatile__( \