diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
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committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-mips/gt64240.h |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/asm-mips/gt64240.h')
-rw-r--r-- | include/asm-mips/gt64240.h | 1235 |
1 files changed, 1235 insertions, 0 deletions
diff --git a/include/asm-mips/gt64240.h b/include/asm-mips/gt64240.h new file mode 100644 index 000000000000..8f9bd341ed49 --- /dev/null +++ b/include/asm-mips/gt64240.h | |||
@@ -0,0 +1,1235 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright - Galileo technology. | ||
7 | * Copyright (C) 2004 by Ralf Baechle | ||
8 | */ | ||
9 | #ifndef __ASM_MIPS_MV64240_H | ||
10 | #define __ASM_MIPS_MV64240_H | ||
11 | |||
12 | #include <asm/addrspace.h> | ||
13 | #include <asm/marvell.h> | ||
14 | |||
15 | /* | ||
16 | * CPU Control Registers | ||
17 | */ | ||
18 | |||
19 | #define CPU_CONFIGURATION 0x000 | ||
20 | #define CPU_MODE 0x120 | ||
21 | #define CPU_READ_RESPONSE_CROSSBAR_LOW 0x170 | ||
22 | #define CPU_READ_RESPONSE_CROSSBAR_HIGH 0x178 | ||
23 | |||
24 | /* | ||
25 | * Processor Address Space | ||
26 | */ | ||
27 | |||
28 | /* Sdram's BAR'S */ | ||
29 | #define SCS_0_LOW_DECODE_ADDRESS 0x008 | ||
30 | #define SCS_0_HIGH_DECODE_ADDRESS 0x010 | ||
31 | #define SCS_1_LOW_DECODE_ADDRESS 0x208 | ||
32 | #define SCS_1_HIGH_DECODE_ADDRESS 0x210 | ||
33 | #define SCS_2_LOW_DECODE_ADDRESS 0x018 | ||
34 | #define SCS_2_HIGH_DECODE_ADDRESS 0x020 | ||
35 | #define SCS_3_LOW_DECODE_ADDRESS 0x218 | ||
36 | #define SCS_3_HIGH_DECODE_ADDRESS 0x220 | ||
37 | /* Devices BAR'S */ | ||
38 | #define CS_0_LOW_DECODE_ADDRESS 0x028 | ||
39 | #define CS_0_HIGH_DECODE_ADDRESS 0x030 | ||
40 | #define CS_1_LOW_DECODE_ADDRESS 0x228 | ||
41 | #define CS_1_HIGH_DECODE_ADDRESS 0x230 | ||
42 | #define CS_2_LOW_DECODE_ADDRESS 0x248 | ||
43 | #define CS_2_HIGH_DECODE_ADDRESS 0x250 | ||
44 | #define CS_3_LOW_DECODE_ADDRESS 0x038 | ||
45 | #define CS_3_HIGH_DECODE_ADDRESS 0x040 | ||
46 | #define BOOTCS_LOW_DECODE_ADDRESS 0x238 | ||
47 | #define BOOTCS_HIGH_DECODE_ADDRESS 0x240 | ||
48 | |||
49 | #define PCI_0I_O_LOW_DECODE_ADDRESS 0x048 | ||
50 | #define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050 | ||
51 | #define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058 | ||
52 | #define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060 | ||
53 | #define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080 | ||
54 | #define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088 | ||
55 | #define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258 | ||
56 | #define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260 | ||
57 | #define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280 | ||
58 | #define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288 | ||
59 | |||
60 | #define PCI_1I_O_LOW_DECODE_ADDRESS 0x090 | ||
61 | #define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098 | ||
62 | #define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0 | ||
63 | #define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8 | ||
64 | #define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0 | ||
65 | #define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8 | ||
66 | #define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0 | ||
67 | #define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8 | ||
68 | #define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0 | ||
69 | #define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8 | ||
70 | |||
71 | #define INTERNAL_SPACE_DECODE 0x068 | ||
72 | |||
73 | #define CPU_0_LOW_DECODE_ADDRESS 0x290 | ||
74 | #define CPU_0_HIGH_DECODE_ADDRESS 0x298 | ||
75 | #define CPU_1_LOW_DECODE_ADDRESS 0x2c0 | ||
76 | #define CPU_1_HIGH_DECODE_ADDRESS 0x2c8 | ||
77 | |||
78 | #define PCI_0I_O_ADDRESS_REMAP 0x0f0 | ||
79 | #define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8 | ||
80 | #define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320 | ||
81 | #define PCI_0MEMORY1_ADDRESS_REMAP 0x100 | ||
82 | #define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328 | ||
83 | #define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8 | ||
84 | #define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330 | ||
85 | #define PCI_0MEMORY3_ADDRESS_REMAP 0x300 | ||
86 | #define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338 | ||
87 | |||
88 | #define PCI_1I_O_ADDRESS_REMAP 0x108 | ||
89 | #define PCI_1MEMORY0_ADDRESS_REMAP 0x110 | ||
90 | #define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340 | ||
91 | #define PCI_1MEMORY1_ADDRESS_REMAP 0x118 | ||
92 | #define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348 | ||
93 | #define PCI_1MEMORY2_ADDRESS_REMAP 0x310 | ||
94 | #define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350 | ||
95 | #define PCI_1MEMORY3_ADDRESS_REMAP 0x318 | ||
96 | #define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358 | ||
97 | |||
98 | /* | ||
99 | * CPU Sync Barrier | ||
100 | */ | ||
101 | |||
102 | #define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0 | ||
103 | #define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8 | ||
104 | |||
105 | |||
106 | /* | ||
107 | * CPU Access Protect | ||
108 | */ | ||
109 | |||
110 | #define CPU_LOW_PROTECT_ADDRESS_0 0X180 | ||
111 | #define CPU_HIGH_PROTECT_ADDRESS_0 0X188 | ||
112 | #define CPU_LOW_PROTECT_ADDRESS_1 0X190 | ||
113 | #define CPU_HIGH_PROTECT_ADDRESS_1 0X198 | ||
114 | #define CPU_LOW_PROTECT_ADDRESS_2 0X1a0 | ||
115 | #define CPU_HIGH_PROTECT_ADDRESS_2 0X1a8 | ||
116 | #define CPU_LOW_PROTECT_ADDRESS_3 0X1b0 | ||
117 | #define CPU_HIGH_PROTECT_ADDRESS_3 0X1b8 | ||
118 | #define CPU_LOW_PROTECT_ADDRESS_4 0X1c0 | ||
119 | #define CPU_HIGH_PROTECT_ADDRESS_4 0X1c8 | ||
120 | #define CPU_LOW_PROTECT_ADDRESS_5 0X1d0 | ||
121 | #define CPU_HIGH_PROTECT_ADDRESS_5 0X1d8 | ||
122 | #define CPU_LOW_PROTECT_ADDRESS_6 0X1e0 | ||
123 | #define CPU_HIGH_PROTECT_ADDRESS_6 0X1e8 | ||
124 | #define CPU_LOW_PROTECT_ADDRESS_7 0X1f0 | ||
125 | #define CPU_HIGH_PROTECT_ADDRESS_7 0X1f8 | ||
126 | |||
127 | |||
128 | /* | ||
129 | * Snoop Control | ||
130 | */ | ||
131 | |||
132 | #define SNOOP_BASE_ADDRESS_0 0x380 | ||
133 | #define SNOOP_TOP_ADDRESS_0 0x388 | ||
134 | #define SNOOP_BASE_ADDRESS_1 0x390 | ||
135 | #define SNOOP_TOP_ADDRESS_1 0x398 | ||
136 | #define SNOOP_BASE_ADDRESS_2 0x3a0 | ||
137 | #define SNOOP_TOP_ADDRESS_2 0x3a8 | ||
138 | #define SNOOP_BASE_ADDRESS_3 0x3b0 | ||
139 | #define SNOOP_TOP_ADDRESS_3 0x3b8 | ||
140 | |||
141 | /* | ||
142 | * CPU Error Report | ||
143 | */ | ||
144 | |||
145 | #define CPU_ERROR_ADDRESS_LOW 0x070 | ||
146 | #define CPU_ERROR_ADDRESS_HIGH 0x078 | ||
147 | #define CPU_ERROR_DATA_LOW 0x128 | ||
148 | #define CPU_ERROR_DATA_HIGH 0x130 | ||
149 | #define CPU_ERROR_PARITY 0x138 | ||
150 | #define CPU_ERROR_CAUSE 0x140 | ||
151 | #define CPU_ERROR_MASK 0x148 | ||
152 | |||
153 | /* | ||
154 | * Pslave Debug | ||
155 | */ | ||
156 | |||
157 | #define X_0_ADDRESS 0x360 | ||
158 | #define X_0_COMMAND_ID 0x368 | ||
159 | #define X_1_ADDRESS 0x370 | ||
160 | #define X_1_COMMAND_ID 0x378 | ||
161 | #define WRITE_DATA_LOW 0x3c0 | ||
162 | #define WRITE_DATA_HIGH 0x3c8 | ||
163 | #define WRITE_BYTE_ENABLE 0X3e0 | ||
164 | #define READ_DATA_LOW 0x3d0 | ||
165 | #define READ_DATA_HIGH 0x3d8 | ||
166 | #define READ_ID 0x3e8 | ||
167 | |||
168 | |||
169 | /* | ||
170 | * SDRAM and Device Address Space | ||
171 | */ | ||
172 | |||
173 | |||
174 | /* | ||
175 | * SDRAM Configuration | ||
176 | */ | ||
177 | |||
178 | #define SDRAM_CONFIGURATION 0x448 | ||
179 | #define SDRAM_OPERATION_MODE 0x474 | ||
180 | #define SDRAM_ADDRESS_DECODE 0x47C | ||
181 | #define SDRAM_TIMING_PARAMETERS 0x4b4 | ||
182 | #define SDRAM_UMA_CONTROL 0x4a4 | ||
183 | #define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8 | ||
184 | #define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac | ||
185 | #define SDRAM_CROSS_BAR_TIMEOUT 0x4b0 | ||
186 | |||
187 | |||
188 | /* | ||
189 | * SDRAM Parameters | ||
190 | */ | ||
191 | |||
192 | #define SDRAM_BANK0PARAMETERS 0x44C | ||
193 | #define SDRAM_BANK1PARAMETERS 0x450 | ||
194 | #define SDRAM_BANK2PARAMETERS 0x454 | ||
195 | #define SDRAM_BANK3PARAMETERS 0x458 | ||
196 | |||
197 | |||
198 | /* | ||
199 | * SDRAM Error Report | ||
200 | */ | ||
201 | |||
202 | #define SDRAM_ERROR_DATA_LOW 0x484 | ||
203 | #define SDRAM_ERROR_DATA_HIGH 0x480 | ||
204 | #define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490 | ||
205 | #define SDRAM_RECEIVED_ECC 0x488 | ||
206 | #define SDRAM_CALCULATED_ECC 0x48c | ||
207 | #define SDRAM_ECC_CONTROL 0x494 | ||
208 | #define SDRAM_ECC_ERROR_COUNTER 0x498 | ||
209 | |||
210 | |||
211 | /* | ||
212 | * SDunit Debug (for internal use) | ||
213 | */ | ||
214 | |||
215 | #define X0_ADDRESS 0x500 | ||
216 | #define X0_COMMAND_AND_ID 0x504 | ||
217 | #define X0_WRITE_DATA_LOW 0x508 | ||
218 | #define X0_WRITE_DATA_HIGH 0x50c | ||
219 | #define X0_WRITE_BYTE_ENABLE 0x518 | ||
220 | #define X0_READ_DATA_LOW 0x510 | ||
221 | #define X0_READ_DATA_HIGH 0x514 | ||
222 | #define X0_READ_ID 0x51c | ||
223 | #define X1_ADDRESS 0x520 | ||
224 | #define X1_COMMAND_AND_ID 0x524 | ||
225 | #define X1_WRITE_DATA_LOW 0x528 | ||
226 | #define X1_WRITE_DATA_HIGH 0x52c | ||
227 | #define X1_WRITE_BYTE_ENABLE 0x538 | ||
228 | #define X1_READ_DATA_LOW 0x530 | ||
229 | #define X1_READ_DATA_HIGH 0x534 | ||
230 | #define X1_READ_ID 0x53c | ||
231 | #define X0_SNOOP_ADDRESS 0x540 | ||
232 | #define X0_SNOOP_COMMAND 0x544 | ||
233 | #define X1_SNOOP_ADDRESS 0x548 | ||
234 | #define X1_SNOOP_COMMAND 0x54c | ||
235 | |||
236 | |||
237 | /* | ||
238 | * Device Parameters | ||
239 | */ | ||
240 | |||
241 | #define DEVICE_BANK0PARAMETERS 0x45c | ||
242 | #define DEVICE_BANK1PARAMETERS 0x460 | ||
243 | #define DEVICE_BANK2PARAMETERS 0x464 | ||
244 | #define DEVICE_BANK3PARAMETERS 0x468 | ||
245 | #define DEVICE_BOOT_BANK_PARAMETERS 0x46c | ||
246 | #define DEVICE_CONTROL 0x4c0 | ||
247 | #define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8 | ||
248 | #define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc | ||
249 | #define DEVICE_CROSS_BAR_TIMEOUT 0x4c4 | ||
250 | |||
251 | |||
252 | /* | ||
253 | * Device Interrupt | ||
254 | */ | ||
255 | |||
256 | #define DEVICE_INTERRUPT_CAUSE 0x4d0 | ||
257 | #define DEVICE_INTERRUPT_MASK 0x4d4 | ||
258 | #define DEVICE_ERROR_ADDRESS 0x4d8 | ||
259 | |||
260 | /* | ||
261 | * DMA Record | ||
262 | */ | ||
263 | |||
264 | #define CHANNEL0_DMA_BYTE_COUNT 0x800 | ||
265 | #define CHANNEL1_DMA_BYTE_COUNT 0x804 | ||
266 | #define CHANNEL2_DMA_BYTE_COUNT 0x808 | ||
267 | #define CHANNEL3_DMA_BYTE_COUNT 0x80C | ||
268 | #define CHANNEL4_DMA_BYTE_COUNT 0x900 | ||
269 | #define CHANNEL5_DMA_BYTE_COUNT 0x904 | ||
270 | #define CHANNEL6_DMA_BYTE_COUNT 0x908 | ||
271 | #define CHANNEL7_DMA_BYTE_COUNT 0x90C | ||
272 | #define CHANNEL0_DMA_SOURCE_ADDRESS 0x810 | ||
273 | #define CHANNEL1_DMA_SOURCE_ADDRESS 0x814 | ||
274 | #define CHANNEL2_DMA_SOURCE_ADDRESS 0x818 | ||
275 | #define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C | ||
276 | #define CHANNEL4_DMA_SOURCE_ADDRESS 0x910 | ||
277 | #define CHANNEL5_DMA_SOURCE_ADDRESS 0x914 | ||
278 | #define CHANNEL6_DMA_SOURCE_ADDRESS 0x918 | ||
279 | #define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C | ||
280 | #define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820 | ||
281 | #define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824 | ||
282 | #define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828 | ||
283 | #define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C | ||
284 | #define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920 | ||
285 | #define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924 | ||
286 | #define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928 | ||
287 | #define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C | ||
288 | #define CHANNEL0NEXT_RECORD_POINTER 0x830 | ||
289 | #define CHANNEL1NEXT_RECORD_POINTER 0x834 | ||
290 | #define CHANNEL2NEXT_RECORD_POINTER 0x838 | ||
291 | #define CHANNEL3NEXT_RECORD_POINTER 0x83C | ||
292 | #define CHANNEL4NEXT_RECORD_POINTER 0x930 | ||
293 | #define CHANNEL5NEXT_RECORD_POINTER 0x934 | ||
294 | #define CHANNEL6NEXT_RECORD_POINTER 0x938 | ||
295 | #define CHANNEL7NEXT_RECORD_POINTER 0x93C | ||
296 | #define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870 | ||
297 | #define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874 | ||
298 | #define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878 | ||
299 | #define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C | ||
300 | #define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970 | ||
301 | #define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974 | ||
302 | #define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978 | ||
303 | #define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C | ||
304 | #define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890 | ||
305 | #define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894 | ||
306 | #define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898 | ||
307 | #define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c | ||
308 | #define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990 | ||
309 | #define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994 | ||
310 | #define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998 | ||
311 | #define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c | ||
312 | #define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0 | ||
313 | #define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4 | ||
314 | #define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8 | ||
315 | #define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac | ||
316 | #define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0 | ||
317 | #define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4 | ||
318 | #define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8 | ||
319 | #define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac | ||
320 | #define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0 | ||
321 | #define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4 | ||
322 | #define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8 | ||
323 | #define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc | ||
324 | #define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0 | ||
325 | #define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4 | ||
326 | #define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8 | ||
327 | #define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc | ||
328 | |||
329 | /* | ||
330 | * DMA Channel Control | ||
331 | */ | ||
332 | |||
333 | #define CHANNEL0CONTROL 0x840 | ||
334 | #define CHANNEL0CONTROL_HIGH 0x880 | ||
335 | |||
336 | #define CHANNEL1CONTROL 0x844 | ||
337 | #define CHANNEL1CONTROL_HIGH 0x884 | ||
338 | |||
339 | #define CHANNEL2CONTROL 0x848 | ||
340 | #define CHANNEL2CONTROL_HIGH 0x888 | ||
341 | |||
342 | #define CHANNEL3CONTROL 0x84C | ||
343 | #define CHANNEL3CONTROL_HIGH 0x88C | ||
344 | |||
345 | #define CHANNEL4CONTROL 0x940 | ||
346 | #define CHANNEL4CONTROL_HIGH 0x980 | ||
347 | |||
348 | #define CHANNEL5CONTROL 0x944 | ||
349 | #define CHANNEL5CONTROL_HIGH 0x984 | ||
350 | |||
351 | #define CHANNEL6CONTROL 0x948 | ||
352 | #define CHANNEL6CONTROL_HIGH 0x988 | ||
353 | |||
354 | #define CHANNEL7CONTROL 0x94C | ||
355 | #define CHANNEL7CONTROL_HIGH 0x98C | ||
356 | |||
357 | |||
358 | /* | ||
359 | * DMA Arbiter | ||
360 | */ | ||
361 | |||
362 | #define ARBITER_CONTROL_0_3 0x860 | ||
363 | #define ARBITER_CONTROL_4_7 0x960 | ||
364 | |||
365 | |||
366 | /* | ||
367 | * DMA Interrupt | ||
368 | */ | ||
369 | |||
370 | #define CHANELS0_3_INTERRUPT_CAUSE 0x8c0 | ||
371 | #define CHANELS0_3_INTERRUPT_MASK 0x8c4 | ||
372 | #define CHANELS0_3_ERROR_ADDRESS 0x8c8 | ||
373 | #define CHANELS0_3_ERROR_SELECT 0x8cc | ||
374 | #define CHANELS4_7_INTERRUPT_CAUSE 0x9c0 | ||
375 | #define CHANELS4_7_INTERRUPT_MASK 0x9c4 | ||
376 | #define CHANELS4_7_ERROR_ADDRESS 0x9c8 | ||
377 | #define CHANELS4_7_ERROR_SELECT 0x9cc | ||
378 | |||
379 | |||
380 | /* | ||
381 | * DMA Debug (for internal use) | ||
382 | */ | ||
383 | |||
384 | #define DMA_X0_ADDRESS 0x8e0 | ||
385 | #define DMA_X0_COMMAND_AND_ID 0x8e4 | ||
386 | #define DMA_X0_WRITE_DATA_LOW 0x8e8 | ||
387 | #define DMA_X0_WRITE_DATA_HIGH 0x8ec | ||
388 | #define DMA_X0_WRITE_BYTE_ENABLE 0x8f8 | ||
389 | #define DMA_X0_READ_DATA_LOW 0x8f0 | ||
390 | #define DMA_X0_READ_DATA_HIGH 0x8f4 | ||
391 | #define DMA_X0_READ_ID 0x8fc | ||
392 | #define DMA_X1_ADDRESS 0x9e0 | ||
393 | #define DMA_X1_COMMAND_AND_ID 0x9e4 | ||
394 | #define DMA_X1_WRITE_DATA_LOW 0x9e8 | ||
395 | #define DMA_X1_WRITE_DATA_HIGH 0x9ec | ||
396 | #define DMA_X1_WRITE_BYTE_ENABLE 0x9f8 | ||
397 | #define DMA_X1_READ_DATA_LOW 0x9f0 | ||
398 | #define DMA_X1_READ_DATA_HIGH 0x9f4 | ||
399 | #define DMA_X1_READ_ID 0x9fc | ||
400 | |||
401 | /* | ||
402 | * Timer_Counter | ||
403 | */ | ||
404 | |||
405 | #define TIMER_COUNTER0 0x850 | ||
406 | #define TIMER_COUNTER1 0x854 | ||
407 | #define TIMER_COUNTER2 0x858 | ||
408 | #define TIMER_COUNTER3 0x85C | ||
409 | #define TIMER_COUNTER_0_3_CONTROL 0x864 | ||
410 | #define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 | ||
411 | #define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c | ||
412 | #define TIMER_COUNTER4 0x950 | ||
413 | #define TIMER_COUNTER5 0x954 | ||
414 | #define TIMER_COUNTER6 0x958 | ||
415 | #define TIMER_COUNTER7 0x95C | ||
416 | #define TIMER_COUNTER_4_7_CONTROL 0x964 | ||
417 | #define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968 | ||
418 | #define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c | ||
419 | |||
420 | /* | ||
421 | * PCI Slave Address Decoding | ||
422 | */ | ||
423 | |||
424 | #define PCI_0SCS_0_BANK_SIZE 0xc08 | ||
425 | #define PCI_1SCS_0_BANK_SIZE 0xc88 | ||
426 | #define PCI_0SCS_1_BANK_SIZE 0xd08 | ||
427 | #define PCI_1SCS_1_BANK_SIZE 0xd88 | ||
428 | #define PCI_0SCS_2_BANK_SIZE 0xc0c | ||
429 | #define PCI_1SCS_2_BANK_SIZE 0xc8c | ||
430 | #define PCI_0SCS_3_BANK_SIZE 0xd0c | ||
431 | #define PCI_1SCS_3_BANK_SIZE 0xd8c | ||
432 | #define PCI_0CS_0_BANK_SIZE 0xc10 | ||
433 | #define PCI_1CS_0_BANK_SIZE 0xc90 | ||
434 | #define PCI_0CS_1_BANK_SIZE 0xd10 | ||
435 | #define PCI_1CS_1_BANK_SIZE 0xd90 | ||
436 | #define PCI_0CS_2_BANK_SIZE 0xd18 | ||
437 | #define PCI_1CS_2_BANK_SIZE 0xd98 | ||
438 | #define PCI_0CS_3_BANK_SIZE 0xc14 | ||
439 | #define PCI_1CS_3_BANK_SIZE 0xc94 | ||
440 | #define PCI_0CS_BOOT_BANK_SIZE 0xd14 | ||
441 | #define PCI_1CS_BOOT_BANK_SIZE 0xd94 | ||
442 | #define PCI_0P2P_MEM0_BAR_SIZE 0xd1c | ||
443 | #define PCI_1P2P_MEM0_BAR_SIZE 0xd9c | ||
444 | #define PCI_0P2P_MEM1_BAR_SIZE 0xd20 | ||
445 | #define PCI_1P2P_MEM1_BAR_SIZE 0xda0 | ||
446 | #define PCI_0P2P_I_O_BAR_SIZE 0xd24 | ||
447 | #define PCI_1P2P_I_O_BAR_SIZE 0xda4 | ||
448 | #define PCI_0CPU_BAR_SIZE 0xd28 | ||
449 | #define PCI_1CPU_BAR_SIZE 0xda8 | ||
450 | #define PCI_0DAC_SCS_0_BANK_SIZE 0xe00 | ||
451 | #define PCI_1DAC_SCS_0_BANK_SIZE 0xe80 | ||
452 | #define PCI_0DAC_SCS_1_BANK_SIZE 0xe04 | ||
453 | #define PCI_1DAC_SCS_1_BANK_SIZE 0xe84 | ||
454 | #define PCI_0DAC_SCS_2_BANK_SIZE 0xe08 | ||
455 | #define PCI_1DAC_SCS_2_BANK_SIZE 0xe88 | ||
456 | #define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c | ||
457 | #define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c | ||
458 | #define PCI_0DAC_CS_0_BANK_SIZE 0xe10 | ||
459 | #define PCI_1DAC_CS_0_BANK_SIZE 0xe90 | ||
460 | #define PCI_0DAC_CS_1_BANK_SIZE 0xe14 | ||
461 | #define PCI_1DAC_CS_1_BANK_SIZE 0xe94 | ||
462 | #define PCI_0DAC_CS_2_BANK_SIZE 0xe18 | ||
463 | #define PCI_1DAC_CS_2_BANK_SIZE 0xe98 | ||
464 | #define PCI_0DAC_CS_3_BANK_SIZE 0xe1c | ||
465 | #define PCI_1DAC_CS_3_BANK_SIZE 0xe9c | ||
466 | #define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20 | ||
467 | #define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0 | ||
468 | #define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24 | ||
469 | #define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4 | ||
470 | #define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28 | ||
471 | #define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8 | ||
472 | #define PCI_0DAC_CPU_BAR_SIZE 0xe2c | ||
473 | #define PCI_1DAC_CPU_BAR_SIZE 0xeac | ||
474 | #define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c | ||
475 | #define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac | ||
476 | #define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c | ||
477 | #define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc | ||
478 | #define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48 | ||
479 | #define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8 | ||
480 | #define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48 | ||
481 | #define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8 | ||
482 | #define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c | ||
483 | #define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc | ||
484 | #define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c | ||
485 | #define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc | ||
486 | #define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50 | ||
487 | #define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0 | ||
488 | #define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50 | ||
489 | #define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0 | ||
490 | #define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58 | ||
491 | #define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8 | ||
492 | #define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54 | ||
493 | #define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4 | ||
494 | #define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54 | ||
495 | #define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4 | ||
496 | #define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c | ||
497 | #define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc | ||
498 | #define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60 | ||
499 | #define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0 | ||
500 | #define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64 | ||
501 | #define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4 | ||
502 | #define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68 | ||
503 | #define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8 | ||
504 | #define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c | ||
505 | #define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec | ||
506 | #define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70 | ||
507 | #define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0 | ||
508 | #define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00 | ||
509 | #define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0 | ||
510 | #define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04 | ||
511 | #define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84 | ||
512 | #define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08 | ||
513 | #define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88 | ||
514 | #define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c | ||
515 | #define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c | ||
516 | #define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10 | ||
517 | #define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90 | ||
518 | #define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14 | ||
519 | #define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94 | ||
520 | #define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18 | ||
521 | #define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98 | ||
522 | #define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c | ||
523 | #define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c | ||
524 | #define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20 | ||
525 | #define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0 | ||
526 | #define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24 | ||
527 | #define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4 | ||
528 | #define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28 | ||
529 | #define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8 | ||
530 | #define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c | ||
531 | #define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac | ||
532 | #define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30 | ||
533 | #define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0 | ||
534 | #define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34 | ||
535 | #define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4 | ||
536 | #define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38 | ||
537 | #define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8 | ||
538 | #define PCI_0ADDRESS_DECODE_CONTROL 0xd3c | ||
539 | #define PCI_1ADDRESS_DECODE_CONTROL 0xdbc | ||
540 | |||
541 | /* | ||
542 | * PCI Control | ||
543 | */ | ||
544 | |||
545 | #define PCI_0COMMAND 0xc00 | ||
546 | #define PCI_1COMMAND 0xc80 | ||
547 | #define PCI_0MODE 0xd00 | ||
548 | #define PCI_1MODE 0xd80 | ||
549 | #define PCI_0TIMEOUT_RETRY 0xc04 | ||
550 | #define PCI_1TIMEOUT_RETRY 0xc84 | ||
551 | #define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04 | ||
552 | #define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84 | ||
553 | #define MSI_0TRIGGER_TIMER 0xc38 | ||
554 | #define MSI_1TRIGGER_TIMER 0xcb8 | ||
555 | #define PCI_0ARBITER_CONTROL 0x1d00 | ||
556 | #define PCI_1ARBITER_CONTROL 0x1d80 | ||
557 | /* changing untill here */ | ||
558 | #define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08 | ||
559 | #define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c | ||
560 | #define PCI_0CROSS_BAR_TIMEOUT 0x1d04 | ||
561 | #define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18 | ||
562 | #define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c | ||
563 | #define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10 | ||
564 | #define PCI_0P2P_CONFIGURATION 0x1d14 | ||
565 | #define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00 | ||
566 | #define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04 | ||
567 | #define PCI_0ACCESS_CONTROL_TOP_0 0x1e08 | ||
568 | #define PCI_0ACCESS_CONTROL_BASE_1_LOW 0c1e10 | ||
569 | #define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14 | ||
570 | #define PCI_0ACCESS_CONTROL_TOP_1 0x1e18 | ||
571 | #define PCI_0ACCESS_CONTROL_BASE_2_LOW 0c1e20 | ||
572 | #define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24 | ||
573 | #define PCI_0ACCESS_CONTROL_TOP_2 0x1e28 | ||
574 | #define PCI_0ACCESS_CONTROL_BASE_3_LOW 0c1e30 | ||
575 | #define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34 | ||
576 | #define PCI_0ACCESS_CONTROL_TOP_3 0x1e38 | ||
577 | #define PCI_0ACCESS_CONTROL_BASE_4_LOW 0c1e40 | ||
578 | #define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44 | ||
579 | #define PCI_0ACCESS_CONTROL_TOP_4 0x1e48 | ||
580 | #define PCI_0ACCESS_CONTROL_BASE_5_LOW 0c1e50 | ||
581 | #define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54 | ||
582 | #define PCI_0ACCESS_CONTROL_TOP_5 0x1e58 | ||
583 | #define PCI_0ACCESS_CONTROL_BASE_6_LOW 0c1e60 | ||
584 | #define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64 | ||
585 | #define PCI_0ACCESS_CONTROL_TOP_6 0x1e68 | ||
586 | #define PCI_0ACCESS_CONTROL_BASE_7_LOW 0c1e70 | ||
587 | #define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74 | ||
588 | #define PCI_0ACCESS_CONTROL_TOP_7 0x1e78 | ||
589 | #define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88 | ||
590 | #define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c | ||
591 | #define PCI_1CROSS_BAR_TIMEOUT 0x1d84 | ||
592 | #define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98 | ||
593 | #define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c | ||
594 | #define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90 | ||
595 | #define PCI_1P2P_CONFIGURATION 0x1d94 | ||
596 | #define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80 | ||
597 | #define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84 | ||
598 | #define PCI_1ACCESS_CONTROL_TOP_0 0x1e88 | ||
599 | #define PCI_1ACCESS_CONTROL_BASE_1_LOW 0c1e90 | ||
600 | #define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94 | ||
601 | #define PCI_1ACCESS_CONTROL_TOP_1 0x1e98 | ||
602 | #define PCI_1ACCESS_CONTROL_BASE_2_LOW 0c1ea0 | ||
603 | #define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 | ||
604 | #define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8 | ||
605 | #define PCI_1ACCESS_CONTROL_BASE_3_LOW 0c1eb0 | ||
606 | #define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 | ||
607 | #define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8 | ||
608 | #define PCI_1ACCESS_CONTROL_BASE_4_LOW 0c1ec0 | ||
609 | #define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 | ||
610 | #define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8 | ||
611 | #define PCI_1ACCESS_CONTROL_BASE_5_LOW 0c1ed0 | ||
612 | #define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 | ||
613 | #define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8 | ||
614 | #define PCI_1ACCESS_CONTROL_BASE_6_LOW 0c1ee0 | ||
615 | #define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4 | ||
616 | #define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8 | ||
617 | #define PCI_1ACCESS_CONTROL_BASE_7_LOW 0c1ef0 | ||
618 | #define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4 | ||
619 | #define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8 | ||
620 | |||
621 | /* | ||
622 | * PCI Snoop Control | ||
623 | */ | ||
624 | |||
625 | #define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00 | ||
626 | #define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04 | ||
627 | #define PCI_0SNOOP_CONTROL_TOP_0 0x1f08 | ||
628 | #define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10 | ||
629 | #define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14 | ||
630 | #define PCI_0SNOOP_CONTROL_TOP_1 0x1f18 | ||
631 | #define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20 | ||
632 | #define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24 | ||
633 | #define PCI_0SNOOP_CONTROL_TOP_2 0x1f28 | ||
634 | #define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30 | ||
635 | #define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34 | ||
636 | #define PCI_0SNOOP_CONTROL_TOP_3 0x1f38 | ||
637 | #define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80 | ||
638 | #define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84 | ||
639 | #define PCI_1SNOOP_CONTROL_TOP_0 0x1f88 | ||
640 | #define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90 | ||
641 | #define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94 | ||
642 | #define PCI_1SNOOP_CONTROL_TOP_1 0x1f98 | ||
643 | #define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0 | ||
644 | #define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4 | ||
645 | #define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8 | ||
646 | #define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0 | ||
647 | #define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4 | ||
648 | #define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8 | ||
649 | |||
650 | /* | ||
651 | * PCI Configuration Address | ||
652 | */ | ||
653 | |||
654 | #define PCI_0CONFIGURATION_ADDRESS 0xcf8 | ||
655 | #define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc | ||
656 | #define PCI_1CONFIGURATION_ADDRESS 0xc78 | ||
657 | #define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c | ||
658 | #define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34 | ||
659 | #define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4 | ||
660 | |||
661 | /* | ||
662 | * PCI Error Report | ||
663 | */ | ||
664 | |||
665 | #define PCI_0SERR_MASK 0xc28 | ||
666 | #define PCI_0ERROR_ADDRESS_LOW 0x1d40 | ||
667 | #define PCI_0ERROR_ADDRESS_HIGH 0x1d44 | ||
668 | #define PCI_0ERROR_DATA_LOW 0x1d48 | ||
669 | #define PCI_0ERROR_DATA_HIGH 0x1d4c | ||
670 | #define PCI_0ERROR_COMMAND 0x1d50 | ||
671 | #define PCI_0ERROR_CAUSE 0x1d58 | ||
672 | #define PCI_0ERROR_MASK 0x1d5c | ||
673 | |||
674 | #define PCI_1SERR_MASK 0xca8 | ||
675 | #define PCI_1ERROR_ADDRESS_LOW 0x1dc0 | ||
676 | #define PCI_1ERROR_ADDRESS_HIGH 0x1dc4 | ||
677 | #define PCI_1ERROR_DATA_LOW 0x1dc8 | ||
678 | #define PCI_1ERROR_DATA_HIGH 0x1dcc | ||
679 | #define PCI_1ERROR_COMMAND 0x1dd0 | ||
680 | #define PCI_1ERROR_CAUSE 0x1dd8 | ||
681 | #define PCI_1ERROR_MASK 0x1ddc | ||
682 | |||
683 | |||
684 | /* | ||
685 | * Lslave Debug (for internal use) | ||
686 | */ | ||
687 | |||
688 | #define L_SLAVE_X0_ADDRESS 0x1d20 | ||
689 | #define L_SLAVE_X0_COMMAND_AND_ID 0x1d24 | ||
690 | #define L_SLAVE_X1_ADDRESS 0x1d28 | ||
691 | #define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c | ||
692 | #define L_SLAVE_WRITE_DATA_LOW 0x1d30 | ||
693 | #define L_SLAVE_WRITE_DATA_HIGH 0x1d34 | ||
694 | #define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60 | ||
695 | #define L_SLAVE_READ_DATA_LOW 0x1d38 | ||
696 | #define L_SLAVE_READ_DATA_HIGH 0x1d3c | ||
697 | #define L_SLAVE_READ_ID 0x1d64 | ||
698 | |||
699 | #if 0 /* Disabled because PCI_* namespace belongs to PCI subsystem ... */ | ||
700 | |||
701 | /* | ||
702 | * PCI Configuration Function 0 | ||
703 | */ | ||
704 | |||
705 | #define PCI_DEVICE_AND_VENDOR_ID 0x000 | ||
706 | #define PCI_STATUS_AND_COMMAND 0x004 | ||
707 | #define PCI_CLASS_CODE_AND_REVISION_ID 0x008 | ||
708 | #define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C | ||
709 | #define PCI_SCS_0_BASE_ADDRESS 0x010 | ||
710 | #define PCI_SCS_1_BASE_ADDRESS 0x014 | ||
711 | #define PCI_SCS_2_BASE_ADDRESS 0x018 | ||
712 | #define PCI_SCS_3_BASE_ADDRESS 0x01C | ||
713 | #define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020 | ||
714 | #define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024 | ||
715 | #define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C | ||
716 | #define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030 | ||
717 | #define PCI_CAPABILTY_LIST_POINTER 0x034 | ||
718 | #define PCI_INTERRUPT_PIN_AND_LINE 0x03C | ||
719 | #define PCI_POWER_MANAGEMENT_CAPABILITY 0x040 | ||
720 | #define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 | ||
721 | #define PCI_VPD_ADDRESS 0x048 | ||
722 | #define PCI_VPD_DATA 0X04c | ||
723 | #define PCI_MSI_MESSAGE_CONTROL 0x050 | ||
724 | #define PCI_MSI_MESSAGE_ADDRESS 0x054 | ||
725 | #define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058 | ||
726 | #define PCI_MSI_MESSAGE_DATA 0x05c | ||
727 | #define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058 | ||
728 | |||
729 | /* | ||
730 | * PCI Configuration Function 1 | ||
731 | */ | ||
732 | |||
733 | #define PCI_CS_0_BASE_ADDRESS 0x110 | ||
734 | #define PCI_CS_1_BASE_ADDRESS 0x114 | ||
735 | #define PCI_CS_2_BASE_ADDRESS 0x118 | ||
736 | #define PCI_CS_3_BASE_ADDRESS 0x11c | ||
737 | #define PCI_BOOTCS_BASE_ADDRESS 0x120 | ||
738 | |||
739 | /* | ||
740 | * PCI Configuration Function 2 | ||
741 | */ | ||
742 | |||
743 | #define PCI_P2P_MEM0_BASE_ADDRESS 0x210 | ||
744 | #define PCI_P2P_MEM1_BASE_ADDRESS 0x214 | ||
745 | #define PCI_P2P_I_O_BASE_ADDRESS 0x218 | ||
746 | #define PCI_CPU_BASE_ADDRESS 0x21c | ||
747 | |||
748 | /* | ||
749 | * PCI Configuration Function 4 | ||
750 | */ | ||
751 | |||
752 | #define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410 | ||
753 | #define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414 | ||
754 | #define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418 | ||
755 | #define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c | ||
756 | #define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420 | ||
757 | #define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424 | ||
758 | |||
759 | |||
760 | /* | ||
761 | * PCI Configuration Function 5 | ||
762 | */ | ||
763 | |||
764 | #define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510 | ||
765 | #define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514 | ||
766 | #define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518 | ||
767 | #define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c | ||
768 | #define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520 | ||
769 | #define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524 | ||
770 | |||
771 | |||
772 | /* | ||
773 | * PCI Configuration Function 6 | ||
774 | */ | ||
775 | |||
776 | #define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610 | ||
777 | #define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614 | ||
778 | #define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618 | ||
779 | #define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c | ||
780 | #define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620 | ||
781 | #define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624 | ||
782 | |||
783 | /* | ||
784 | * PCI Configuration Function 7 | ||
785 | */ | ||
786 | |||
787 | #define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710 | ||
788 | #define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714 | ||
789 | #define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718 | ||
790 | #define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c | ||
791 | #define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720 | ||
792 | #define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724 | ||
793 | #endif | ||
794 | |||
795 | /* | ||
796 | * Interrupts | ||
797 | */ | ||
798 | |||
799 | #define LOW_INTERRUPT_CAUSE_REGISTER 0xc18 | ||
800 | #define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68 | ||
801 | #define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c | ||
802 | #define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c | ||
803 | #define CPU_SELECT_CAUSE_REGISTER 0xc70 | ||
804 | #define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24 | ||
805 | #define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64 | ||
806 | #define PCI_0SELECT_CAUSE 0xc74 | ||
807 | #define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4 | ||
808 | #define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4 | ||
809 | #define PCI_1SELECT_CAUSE 0xcf4 | ||
810 | #define CPU_INT_0_MASK 0xe60 | ||
811 | #define CPU_INT_1_MASK 0xe64 | ||
812 | #define CPU_INT_2_MASK 0xe68 | ||
813 | #define CPU_INT_3_MASK 0xe6c | ||
814 | |||
815 | /* | ||
816 | * I20 Support registers | ||
817 | */ | ||
818 | |||
819 | #define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x010 | ||
820 | #define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x014 | ||
821 | #define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x018 | ||
822 | #define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x01C | ||
823 | #define INBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x020 | ||
824 | #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x024 | ||
825 | #define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x028 | ||
826 | #define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x02C | ||
827 | #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x030 | ||
828 | #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x034 | ||
829 | #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x040 | ||
830 | #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x044 | ||
831 | #define QUEUE_CONTROL_REGISTER_PCI0_SIDE 0x050 | ||
832 | #define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE 0x054 | ||
833 | #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x060 | ||
834 | #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x064 | ||
835 | #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x068 | ||
836 | #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x06C | ||
837 | #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x070 | ||
838 | #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x074 | ||
839 | #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x0F8 | ||
840 | #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x0FC | ||
841 | |||
842 | #define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x090 | ||
843 | #define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x094 | ||
844 | #define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x098 | ||
845 | #define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x09C | ||
846 | #define INBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0A0 | ||
847 | #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0A4 | ||
848 | #define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0A8 | ||
849 | #define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0AC | ||
850 | #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0B0 | ||
851 | #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0B4 | ||
852 | #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C0 | ||
853 | #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C4 | ||
854 | #define QUEUE_CONTROL_REGISTER_PCI1_SIDE 0x0D0 | ||
855 | #define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE 0x0D4 | ||
856 | #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E0 | ||
857 | #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0E4 | ||
858 | #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E8 | ||
859 | #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0EC | ||
860 | #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0F0 | ||
861 | #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0F4 | ||
862 | #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x078 | ||
863 | #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x07C | ||
864 | |||
865 | #define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C10 | ||
866 | #define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C14 | ||
867 | #define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C18 | ||
868 | #define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C1C | ||
869 | #define INBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C20 | ||
870 | #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C24 | ||
871 | #define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C28 | ||
872 | #define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C2C | ||
873 | #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C30 | ||
874 | #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C34 | ||
875 | #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C40 | ||
876 | #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C44 | ||
877 | #define QUEUE_CONTROL_REGISTER_CPU0_SIDE 0X1C50 | ||
878 | #define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE 0X1C54 | ||
879 | #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C60 | ||
880 | #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C64 | ||
881 | #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C68 | ||
882 | #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C6C | ||
883 | #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C70 | ||
884 | #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C74 | ||
885 | #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1CF8 | ||
886 | #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1CFC | ||
887 | |||
888 | #define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C90 | ||
889 | #define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C94 | ||
890 | #define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C98 | ||
891 | #define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C9C | ||
892 | #define INBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CA0 | ||
893 | #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CA4 | ||
894 | #define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CA8 | ||
895 | #define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CAC | ||
896 | #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CB0 | ||
897 | #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CB4 | ||
898 | #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC0 | ||
899 | #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC4 | ||
900 | #define QUEUE_CONTROL_REGISTER_CPU1_SIDE 0X1CD0 | ||
901 | #define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE 0X1CD4 | ||
902 | #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE0 | ||
903 | #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CE4 | ||
904 | #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE8 | ||
905 | #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CEC | ||
906 | #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CF0 | ||
907 | #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CF4 | ||
908 | #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1C78 | ||
909 | #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1C7C | ||
910 | |||
911 | /* | ||
912 | * Communication Unit Registers | ||
913 | */ | ||
914 | |||
915 | #define ETHERNET_0_ADDRESS_CONTROL_LOW | ||
916 | #define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204 | ||
917 | #define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208 | ||
918 | #define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c | ||
919 | #define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210 | ||
920 | #define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214 | ||
921 | #define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218 | ||
922 | #define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220 | ||
923 | #define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224 | ||
924 | #define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228 | ||
925 | #define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c | ||
926 | #define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230 | ||
927 | #define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234 | ||
928 | #define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238 | ||
929 | #define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240 | ||
930 | #define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244 | ||
931 | #define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248 | ||
932 | #define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c | ||
933 | #define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250 | ||
934 | #define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254 | ||
935 | #define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258 | ||
936 | #define MPSC_0_ADDRESS_CONTROL_LOW 0xf280 | ||
937 | #define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284 | ||
938 | #define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288 | ||
939 | #define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c | ||
940 | #define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290 | ||
941 | #define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294 | ||
942 | #define MPSC_1_ADDRESS_CONTROL_LOW 0xf2a0 | ||
943 | #define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2a4 | ||
944 | #define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2a8 | ||
945 | #define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2ac | ||
946 | #define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b0 | ||
947 | #define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b4 | ||
948 | #define MPSC_2_ADDRESS_CONTROL_LOW 0xf2c0 | ||
949 | #define MPSC_2_ADDRESS_CONTROL_HIGH 0xf2c4 | ||
950 | #define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8 | ||
951 | #define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc | ||
952 | #define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0 | ||
953 | #define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4 | ||
954 | #define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320 | ||
955 | #define SERIAL_INIT_LAST_DATA 0xf324 | ||
956 | #define SERIAL_INIT_STATUS_AND_CONTROL 0xf328 | ||
957 | #define COMM_UNIT_ARBITER_CONTROL 0xf300 | ||
958 | #define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304 | ||
959 | #define COMM_UNIT_INTERRUPT_CAUSE 0xf310 | ||
960 | #define COMM_UNIT_INTERRUPT_MASK 0xf314 | ||
961 | #define COMM_UNIT_ERROR_ADDRESS 0xf314 | ||
962 | |||
963 | /* | ||
964 | * Cunit Debug (for internal use) | ||
965 | */ | ||
966 | |||
967 | #define CUNIT_ADDRESS 0xf340 | ||
968 | #define CUNIT_COMMAND_AND_ID 0xf344 | ||
969 | #define CUNIT_WRITE_DATA_LOW 0xf348 | ||
970 | #define CUNIT_WRITE_DATA_HIGH 0xf34c | ||
971 | #define CUNIT_WRITE_BYTE_ENABLE 0xf358 | ||
972 | #define CUNIT_READ_DATA_LOW 0xf350 | ||
973 | #define CUNIT_READ_DATA_HIGH 0xf354 | ||
974 | #define CUNIT_READ_ID 0xf35c | ||
975 | |||
976 | /* | ||
977 | * Fast Ethernet Unit Registers | ||
978 | */ | ||
979 | |||
980 | /* Ethernet */ | ||
981 | |||
982 | #define ETHERNET_PHY_ADDRESS_REGISTER 0x2000 | ||
983 | #define ETHERNET_SMI_REGISTER 0x2010 | ||
984 | |||
985 | /* Ethernet 0 */ | ||
986 | |||
987 | #define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400 | ||
988 | #define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408 | ||
989 | #define ETHERNET0_PORT_COMMAND_REGISTER 0x2410 | ||
990 | #define ETHERNET0_PORT_STATUS_REGISTER 0x2418 | ||
991 | #define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420 | ||
992 | #define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428 | ||
993 | #define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430 | ||
994 | #define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438 | ||
995 | #define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440 | ||
996 | #define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448 | ||
997 | #define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450 | ||
998 | #define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458 | ||
999 | #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480 | ||
1000 | #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484 | ||
1001 | #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488 | ||
1002 | #define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c | ||
1003 | #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0 | ||
1004 | #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4 | ||
1005 | #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8 | ||
1006 | #define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac | ||
1007 | #define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0 | ||
1008 | #define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4 | ||
1009 | #define ETHERNET0_MIB_COUNTER_BASE 0x2500 | ||
1010 | |||
1011 | /* Ethernet 1 */ | ||
1012 | |||
1013 | #define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800 | ||
1014 | #define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808 | ||
1015 | #define ETHERNET1_PORT_COMMAND_REGISTER 0x2810 | ||
1016 | #define ETHERNET1_PORT_STATUS_REGISTER 0x2818 | ||
1017 | #define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820 | ||
1018 | #define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828 | ||
1019 | #define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830 | ||
1020 | #define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838 | ||
1021 | #define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840 | ||
1022 | #define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848 | ||
1023 | #define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850 | ||
1024 | #define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858 | ||
1025 | #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880 | ||
1026 | #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884 | ||
1027 | #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888 | ||
1028 | #define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c | ||
1029 | #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0 | ||
1030 | #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4 | ||
1031 | #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8 | ||
1032 | #define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac | ||
1033 | #define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0 | ||
1034 | #define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4 | ||
1035 | #define ETHERNET1_MIB_COUNTER_BASE 0x2900 | ||
1036 | |||
1037 | /* Ethernet 2 */ | ||
1038 | |||
1039 | #define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00 | ||
1040 | #define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08 | ||
1041 | #define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10 | ||
1042 | #define ETHERNET2_PORT_STATUS_REGISTER 0x2c18 | ||
1043 | #define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20 | ||
1044 | #define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28 | ||
1045 | #define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30 | ||
1046 | #define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38 | ||
1047 | #define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40 | ||
1048 | #define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48 | ||
1049 | #define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50 | ||
1050 | #define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58 | ||
1051 | #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80 | ||
1052 | #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84 | ||
1053 | #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88 | ||
1054 | #define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c | ||
1055 | #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0 | ||
1056 | #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4 | ||
1057 | #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8 | ||
1058 | #define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac | ||
1059 | #define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0 | ||
1060 | #define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4 | ||
1061 | #define ETHERNET2_MIB_COUNTER_BASE 0x2d00 | ||
1062 | |||
1063 | /* | ||
1064 | * SDMA Registers | ||
1065 | */ | ||
1066 | |||
1067 | #define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0 | ||
1068 | #define CHANNEL0_CONFIGURATION_REGISTER 0x4000 | ||
1069 | #define CHANNEL0_COMMAND_REGISTER 0x4008 | ||
1070 | #define CHANNEL0_RX_CMD_STATUS 0x4800 | ||
1071 | #define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804 | ||
1072 | #define CHANNEL0_RX_BUFFER_POINTER 0x4808 | ||
1073 | #define CHANNEL0_RX_NEXT_POINTER 0x480c | ||
1074 | #define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810 | ||
1075 | #define CHANNEL0_TX_CMD_STATUS 0x4C00 | ||
1076 | #define CHANNEL0_TX_PACKET_SIZE 0x4C04 | ||
1077 | #define CHANNEL0_TX_BUFFER_POINTER 0x4C08 | ||
1078 | #define CHANNEL0_TX_NEXT_POINTER 0x4C0c | ||
1079 | #define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10 | ||
1080 | #define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14 | ||
1081 | #define CHANNEL1_CONFIGURATION_REGISTER 0x6000 | ||
1082 | #define CHANNEL1_COMMAND_REGISTER 0x6008 | ||
1083 | #define CHANNEL1_RX_CMD_STATUS 0x6800 | ||
1084 | #define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x6804 | ||
1085 | #define CHANNEL1_RX_BUFFER_POINTER 0x6808 | ||
1086 | #define CHANNEL1_RX_NEXT_POINTER 0x680c | ||
1087 | #define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 | ||
1088 | #define CHANNEL1_TX_CMD_STATUS 0x6C00 | ||
1089 | #define CHANNEL1_TX_PACKET_SIZE 0x6C04 | ||
1090 | #define CHANNEL1_TX_BUFFER_POINTER 0x6C08 | ||
1091 | #define CHANNEL1_TX_NEXT_POINTER 0x6C0c | ||
1092 | #define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810 | ||
1093 | #define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10 | ||
1094 | #define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x6c14 | ||
1095 | |||
1096 | /* SDMA Interrupt */ | ||
1097 | |||
1098 | #define SDMA_CAUSE 0xb820 | ||
1099 | #define SDMA_MASK 0xb8a0 | ||
1100 | |||
1101 | |||
1102 | /* | ||
1103 | * Baude Rate Generators Registers | ||
1104 | */ | ||
1105 | |||
1106 | /* BRG 0 */ | ||
1107 | |||
1108 | #define BRG0_CONFIGURATION_REGISTER 0xb200 | ||
1109 | #define BRG0_BAUDE_TUNING_REGISTER 0xb204 | ||
1110 | |||
1111 | /* BRG 1 */ | ||
1112 | |||
1113 | #define BRG1_CONFIGURATION_REGISTER 0xb208 | ||
1114 | #define BRG1_BAUDE_TUNING_REGISTER 0xb20c | ||
1115 | |||
1116 | /* BRG 2 */ | ||
1117 | |||
1118 | #define BRG2_CONFIGURATION_REGISTER 0xb210 | ||
1119 | #define BRG2_BAUDE_TUNING_REGISTER 0xb214 | ||
1120 | |||
1121 | /* BRG Interrupts */ | ||
1122 | |||
1123 | #define BRG_CAUSE_REGISTER 0xb834 | ||
1124 | #define BRG_MASK_REGISTER 0xb8b4 | ||
1125 | |||
1126 | /* MISC */ | ||
1127 | |||
1128 | #define MAIN_ROUTING_REGISTER 0xb400 | ||
1129 | #define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404 | ||
1130 | #define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408 | ||
1131 | #define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c | ||
1132 | #define WATCHDOG_CONFIGURATION_REGISTER 0xb410 | ||
1133 | #define WATCHDOG_VALUE_REGISTER 0xb414 | ||
1134 | |||
1135 | |||
1136 | /* | ||
1137 | * Flex TDM Registers | ||
1138 | */ | ||
1139 | |||
1140 | /* FTDM Port */ | ||
1141 | |||
1142 | #define FLEXTDM_TRANSMIT_READ_POINTER 0xa800 | ||
1143 | #define FLEXTDM_RECEIVE_READ_POINTER 0xa804 | ||
1144 | #define FLEXTDM_CONFIGURATION_REGISTER 0xa808 | ||
1145 | #define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c | ||
1146 | #define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810 | ||
1147 | #define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814 | ||
1148 | #define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818 | ||
1149 | |||
1150 | /* FTDM Interrupts */ | ||
1151 | |||
1152 | #define FTDM_CAUSE_REGISTER 0xb830 | ||
1153 | #define FTDM_MASK_REGISTER 0xb8b0 | ||
1154 | |||
1155 | |||
1156 | /* | ||
1157 | * GPP Interface Registers | ||
1158 | */ | ||
1159 | |||
1160 | #define GPP_IO_CONTROL 0xf100 | ||
1161 | #define GPP_LEVEL_CONTROL 0xf110 | ||
1162 | #define GPP_VALUE 0xf104 | ||
1163 | #define GPP_INTERRUPT_CAUSE 0xf108 | ||
1164 | #define GPP_INTERRUPT_MASK 0xf10c | ||
1165 | |||
1166 | #define MPP_CONTROL0 0xf000 | ||
1167 | #define MPP_CONTROL1 0xf004 | ||
1168 | #define MPP_CONTROL2 0xf008 | ||
1169 | #define MPP_CONTROL3 0xf00c | ||
1170 | #define DEBUG_PORT_MULTIPLEX 0xf014 | ||
1171 | #define SERIAL_PORT_MULTIPLEX 0xf010 | ||
1172 | |||
1173 | /* | ||
1174 | * I2C Registers | ||
1175 | */ | ||
1176 | |||
1177 | #define I2C_SLAVE_ADDRESS 0xc000 | ||
1178 | #define I2C_EXTENDED_SLAVE_ADDRESS 0xc040 | ||
1179 | #define I2C_DATA 0xc004 | ||
1180 | #define I2C_CONTROL 0xc008 | ||
1181 | #define I2C_STATUS_BAUDE_RATE 0xc00C | ||
1182 | #define I2C_SOFT_RESET 0xc01c | ||
1183 | |||
1184 | /* | ||
1185 | * MPSC Registers | ||
1186 | */ | ||
1187 | |||
1188 | /* | ||
1189 | * MPSC0 | ||
1190 | */ | ||
1191 | |||
1192 | #define MPSC0_MAIN_CONFIGURATION_LOW 0x8000 | ||
1193 | #define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004 | ||
1194 | #define MPSC0_PROTOCOL_CONFIGURATION 0x8008 | ||
1195 | #define CHANNEL0_REGISTER1 0x800c | ||
1196 | #define CHANNEL0_REGISTER2 0x8010 | ||
1197 | #define CHANNEL0_REGISTER3 0x8014 | ||
1198 | #define CHANNEL0_REGISTER4 0x8018 | ||
1199 | #define CHANNEL0_REGISTER5 0x801c | ||
1200 | #define CHANNEL0_REGISTER6 0x8020 | ||
1201 | #define CHANNEL0_REGISTER7 0x8024 | ||
1202 | #define CHANNEL0_REGISTER8 0x8028 | ||
1203 | #define CHANNEL0_REGISTER9 0x802c | ||
1204 | #define CHANNEL0_REGISTER10 0x8030 | ||
1205 | #define CHANNEL0_REGISTER11 0x8034 | ||
1206 | |||
1207 | /* | ||
1208 | * MPSC1 | ||
1209 | */ | ||
1210 | |||
1211 | #define MPSC1_MAIN_CONFIGURATION_LOW 0x9000 | ||
1212 | #define MPSC1_MAIN_CONFIGURATION_HIGH 0x9004 | ||
1213 | #define MPSC1_PROTOCOL_CONFIGURATION 0x9008 | ||
1214 | #define CHANNEL1_REGISTER1 0x900c | ||
1215 | #define CHANNEL1_REGISTER2 0x9010 | ||
1216 | #define CHANNEL1_REGISTER3 0x9014 | ||
1217 | #define CHANNEL1_REGISTER4 0x9018 | ||
1218 | #define CHANNEL1_REGISTER5 0x901c | ||
1219 | #define CHANNEL1_REGISTER6 0x9020 | ||
1220 | #define CHANNEL1_REGISTER7 0x9024 | ||
1221 | #define CHANNEL1_REGISTER8 0x9028 | ||
1222 | #define CHANNEL1_REGISTER9 0x902c | ||
1223 | #define CHANNEL1_REGISTER10 0x9030 | ||
1224 | #define CHANNEL1_REGISTER11 0x9034 | ||
1225 | |||
1226 | /* | ||
1227 | * MPSCs Interupts | ||
1228 | */ | ||
1229 | |||
1230 | #define MPSC0_CAUSE 0xb804 | ||
1231 | #define MPSC0_MASK 0xb884 | ||
1232 | #define MPSC1_CAUSE 0xb80c | ||
1233 | #define MPSC1_MASK 0xb88c | ||
1234 | |||
1235 | #endif /* __ASM_MIPS_MV64240_H */ | ||